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基于IGBT的变频电源设计资料,基于,igbt,变频,电源,设计,资料
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I目 录1 引言 .12 方案论证与比较 .32.1 SPWM方案论证与选择 .32.2 驱动电路的设计方案论证与选择 .43 系统组成 .54 单元电路的设计 .64.1 光电隔离电路设计 .64.2 驱动电路设计 .74.3 IGBT电路设计 .84.3.1 IGBT介绍 .84.3.2 桥式电路 .94.4 低通滤波电路设计 .104.5 电源电路设计 .114.6 SPWM单元电路 .124.6.1 SPWM发展 .124.6.2 SPWM波形生成方法 .134.6.3 ATMEGA8单片机介绍 .144.6.4 ATMEGA8单片机引脚及功能 .154.6.5 ATMEGA8单片机的最小系统电路及软件流程 .174.7 电压采集单元电路 .194.7.1 89S52单片机的管脚说明 .194.7.2 ADC0809介绍 .234.7.3 ADC0809管脚说明 .234.7.4 ADC0809电路及软件流程 .265 测试结果 .29结 论 .30参考文献 .31附录 1 系统电路 .32附录 2 SPWM 程序 .33附录 3 电压采集程序 .37致 谢 .4111 引言众所周知，我们所使用的市电频率是 50Hz，但是，在实际生活中，有时需要的电源频率不是 50Hz。电气化铁路是我国铁路发展的方向，25Hz 电源是电气化铁路区段信号系统的关键设备。在航空航天领域大量使用的电源是 400Hz的电源。由此可以看出在很多场合，需要电源的频率并不是市电所提供的 50Hz。结果造就变频电源的产生。在现实生活中变频电源广泛应用于航空、机械、轻工等行业。1969 年世界上诞生第一台逆变电源，由于其具有调节特性优良、而且体积小、重量轻、功耗低，在电子和电气领域得到了迅速的推广应用。逆变器从1969年发展到今天，经历了几十年的发展过程。其控制方法也出现了许多，大致可以分为：变压和变频控制方法。目前采用较多的是变压中的脉宽调制技术即PWM控制技术，即利用控制输出电压的脉冲宽度，将直流电压调制成等幅宽度可变的交流输出电压脉冲，来控制输出电压的有效值、控制输出电压谐波的分布和抑制谐波。PWM技术可以迅速地控制输出电压，及其有效地进行谐波抑制，它的动态响应好，在输出电压质量、效率等诸方面有着明显的优点。根据形成PWM波原理的不同，可以分为以下几种：矩形波PWM、正弦波SPWM、空间相量PWM(SVM)、特定谐波消除PWM、电流滞环PWM等。这四类PWM波各有优缺点，因而适用于不同的场合。SPWM的全称是Sine Pulse Width Modulation，意思是正弦脉冲宽度调制 1，简称为SPWM,是调制波为正弦波、载波为三角波或锯齿波的一种脉宽调制法，它是1964年由A.Schonung和H.Stemmler把通讯系统的调制技术应用到逆变器而产生的。后来由Bristol大学的S.R. Bo wer等于1975年对该技术正式进行了推广应用。这项技术的特点是原理简单，通用性强，控制和调节性能好，具有消除谐波、调节和稳定输出电压的多种作用，是一种比较好的波形改善法。它的出现为中小型逆变器的发展起了重要的推动作用。传统的电源采用都是模拟控制系统，模拟控制经过多年的发展，己经非常成熟。然而，模拟控制有着固有的缺点：控制电路的元器件比较多，电路复杂，所占体积大，制造成本比较高；灵活性不够，硬件电路设计好了，控制策略就无法改变；最主要的是逆变电源不便于调试，大量的模拟元器件使其之间的连接相当复杂，从而使系统的故障检测与维修比较困难。模拟器件的老化问题和不可补偿的温漂问题，以及易受环境(如电磁噪声，上作环境温度等)干扰等因素都会影响控制系统的长期稳定性。近年来高速MCU技术的成熟和普遍，与其采用哈佛结构、流水线操作，即程2序、数据存储器彼此相互独立，在每一时钟周期中能完成取指、译码、读数据以及执行指令等多个操作从而大大减少指令执行周期。高速数字MCU的发展，正弦波逆变器的控制技术方案也由传统的模拟控制向现代数字化控制的方向发展。采用数字化控制，不仅可以大大降低控制电路的复杂程度，提高电源设计和制造的灵活性，而且可以采用更先进的控制方法，从而提高逆变电源系统输出波形的质量和可靠性。基于MCU的发展上逆变电源技术正朝者以下几种趋势发展：1 高频化 理论分析和实践经验表明：电器产品的变压器、电感和电容的体积重量与供电频率的平方根成反比。所以当我们把频率从工频50Hz提高到20khz，提高400倍的话，用电设备的体积重量大体下降至工频设计的5-10%，其主要材料可以节约90%甚至更高，还可以节电30%甚至更多。由于功率电子器件工作频率上限的逐步提高，促使许多原来采用电子管的传统高频设备固态化，原材料消耗显著降低、电源装置小型化、系统的动态反应加快，更可以深刻体现技术含量的价值。2 数字化 现在数字式信号，数字电路越来越重要，数字信号处理技术日趋完善成熟，显示出越来越多的优点，便于计算机处理控制、避免模拟信号的畸变失真、提高系统抗干扰能力、便于软件包调试、也便于自诊断，容错等技术的植入，同时也为电源的并联技术发展提供了方便。3 绿色化 随着各种政策法规的出台，对无污染的绿色电源的呼声越来越高。绿色电源的含义有两层：首先是显著节电，这意味着发电容量的节约，而发电是造成环境污染的重要原因，所以节电就可以减少对环境的污染；其次这些电源不能对电网产生污染。为了使电源系统绿色化，电源应加装高效滤波器，还应在电网输入端采用功率因数校正技术和软开关技术。提高输入功率因数具有重要意义，不仅可以减少对电网的污染，降低市电的无功损耗，起到环保和节能的效果，而且还能减少相应的投资，提高运行可靠性。提高功率因数的传统方法是采用无源功率因数校正技术，目前较先进的方法是：单相输入的采用有源功率因数校正技术。本设计主要是采用等效面积算法来计算逆变产生 SPWM波形 2，保持输出波形不失真。同时，通过 89S52单片机控制 ADC0809采集输出的电压值并在数码管上作相对应的显示。设计的主要要求是方案成本低，体积小，无需调外部元件，接口简单。SPWM的产生是通过单片机 ATMEGA8根据算法产生。再经隔离驱动放大，最后滤波输出，得到所需要的正弦波形。ATMEGA8 单片机是 ATMEL公司推出的高速最小型高速单片机，它是一个 28脚的小型单片机，在内部已经集成晶体振荡器，无须外接晶振就可以以最高速度 8MHz的时钟执行程序。是目前速度较高的最小型单片机，它为高速率低成本的数字变频电源提出了解决方案。本课题的实用性非常强，在许多的领域中都用到，如：用于交流电机调速系统、舰船、航空航天、邮电通讯、军事装备、交通设施、仪器仪表、工业设备等。32 方案论证与比较2.1 SPWM 方案论证与选择方案 1：采用比较器对正弦波和三角波进行比较 3得到 PWM波，基本框图如图 1所示，将比较后得到 PWM送入驱动电路放大后再驱动 IGBT。图 1 正弦波与三角波比较电路框图该方法实现比较困难，并且受运放参数影响较大，调试困难，稳定性较差而且，不易灵活控制。方案 2：采用间接生成法即使用专用的 PWM芯片与单片机进行通讯，基本框图如图 2所示。图 2 单片机控制 PWM芯片框图用单片机去指令控制 PWM的移相或倒相。该方法优点是单片机的工作量并不大运算速度要求不高，可以用一般的单片机实现。缺点是专用 PWM芯片难以控制，增加了系统的复杂程度成本较高，不易于在实际中应用。方案 3：运用单片机通过等效面积算法来计算逆变产生 SPWM波形，此种方法实现简单，易于控制和改变，并且具有较强的抗干扰能力。由于单片机输出的是数字信号，使其具有数字化的特点。综上所述，方案 3具有更优良的性能和更简单的电路构成，所以使用方案 3作正弦波输入三角波输入PWM输出输出滤波比较电路电源电路PWM输出输出滤波PWM芯片电源电路单片机4为本次设计的方案。2.2 驱动电路的设计方案论证与选择方案 1：使用专用驱动芯片如 M57962，EXB840，IR2110 4等，如图 3所示。驱动芯片配合少数的外围元件完成，该方法优点是系统的集成度高，有良好的过载和短路保护功能。缺点是此类芯片几乎都存在一个共同的特点，本身不能产生负电压，抗干扰能力差，并且有一定的延迟时间，芯片反应速度较慢，不适合在高频电源中使用并且其一般价格较高。图 3 控制驱动芯片框图方案 2：采用分立元件搭建驱动电路。电路中选用高速开关三极管 8050和8550，其反应速度可以达到微秒级，能很好的抑制在传输中出现的新的频率成分, 并且避免了信号在传输过程中的累加延迟，有利于减少输出波形的失真度。开关三极管具有开关速度快,输出电流大，单电源供电等优点完全可以应用于高频段，满足系统的要求。在需要更大电流驱动的场合，三极管还可以接成推挽输出模式以提高输出电流，分立元件的驱动电路具有良好的性价比。综上所述，选择方案 2即采用分立元件搭建驱动电路。PWM输出输出滤波驱动芯片电源电路53 系统组成本变频器电源系统的结构原理如图4所示。单相交流电源经过EMI线滤波器后，再经单相桥式整流和大容滤波后可在直流母线上获得稳定的直流电压。该直流电压在电压可调电路的控制下，经过桥式逆变电路逆变后，可输出由驱动电路送来的SPWM信号，在经过一级小容量的LC滤波网络后，即可在输出端获得较为理想的正弦波输出电压信号。以单片机为主的控制系统主要用来产生逆变电路开关器件的驱动信号，另一单片机通过对直流母线电压的采样，实时的监测并显示直流母线电压值，使整个系统方便用户的操作。图4 变频器结构原理图电压显示 电源电路2EMI滤波 整流滤波 电压可调电压采集显示驱动 单片机 驱动电路桥式逆变输出滤波单片机产生 SPWM生chacheng生电源电路1输出AC64 单元电路的设计4.1 光电隔离电路设计光电隔离也叫光电藕荷器，就是把电的信号转换成光的信号，然后再把光的强弱转换成相对应的电压信号，从而实现高压和低压的电气隔离。一般是由发光二极管和光敏三极管构成，光敏三极管是特殊的三极管，把基极电流大小做成受发光二极管光强弱控制。因此，光电隔离事实是一种电信号光强弱电信号变换器。常见的光电藕荷器内部电路如图 4-1所示：U10图 4-1 常用光电耦合器内部电路光电藕荷器一般应用在信号不匹配，输入的信号可能是交流信号、高压信号、按键等干接点信号，比较长的连接线路容易引进干扰、雷击、感应电等，不经过隔离不可靠或容易对人体造成伤害。一般情况下光电藕荷器输入端是靠一定的电流来触发光耦管，从而产生一个输入信号，电流一般为 4mA- 22mA。TTL 输入则是靠高、低电平来产生一个输入信号。其中，#include unsigned char i=0,k=0,out_date=0; /*unsigned char timer_long40=0x01,0x39, ;此段为测试输出，实际中不用0x02,0x64,0x03,0x84,0x04,0x94,0x05,0x86,0x06,0x52,0x06,0xf6,0x07,0x6e,0x07,0xb7,0x07,0xd0,0x07,0xd0,0x07,0xb7,0x07,0x6e,0x06,0xf6,0x06,0x52,0x05,0x86,0x04,0x94,0x03,0x84,0x02,0x64,0x01,0x39 ;*/unsigned char timer_long20=0x01,0x37,/0x35,0x02,0xc5,/0xc3,0x03,0x7d,/0x7b,350x03,0xb9,/0xb7,0x03,0xdd,/0xdb,0x03,0xdd,/0xdb,x03,0xb9,/0xb7,0x03,0x7d,/0x7b,0x02,0xc5,/0xc3,0x01,0x37,/0x35, ;void port_init(void)PORTB = 0xff;DDRB = 0xFF;PORTC = 0x00; /m103 output onlyDDRC = 0x00;PORTD = 0x00;DDRD = 0x00;/TIMER1 initialize - prescale:1/ WGM: 0) Normal, TOP=0xFFFF/ desired value: 0.125uSec/ actual value: 0.125uSec (0.0%)void timer1_init(void)TCCR1B = 0x00; /stopTCNT1H = 0xFF; /setupTCNT1L = 0xFF;OCR1AH = 0x00;OCR1AL = 0x01;OCR1BH = 0x00;OCR1BL = 0x01;ICR1H = 0x00;ICR1L = 0x01;TCCR1A = 0x00;TCCR1B = 0x01; /start Timer36#pragma interrupt_handler timer1_ovf_isr:9void timer1_ovf_isr(void) /TIMER1 has overflowedk+;if(k=2)k=0;if(k=1) TCNT1H = 0xff-timer_long2*i; /reload counter high valueTCNT1L = 0xff-timer_long2*i+1; /reload counter low valueif(out_date=0) PORTB =PORTB|0x01;PORTB =PORTBelse PORTB =PORTB|0x02;PORTB =PORTBi+;else TCNT1H =0xfc+timer_long2*i; /reload counter high valueTCNT1L =0xff+timer_long2*i+1; /reload counter low value/TCNT1L =0x19+timer_long2*i+1; /reload counter low value/ TCNT1H =0xf8+timer_long2*i; /reload counter high value;16M/ TCNT1L =0x2f+timer_long2*i+1; /reload counter low value/TCNT1H =0xe0+8*timer_long2*i; /reload counter high value/ TCNT1L =0xbf+8*timer_long2*i+1; /reload counter low valueif(out_date=0) PORTB =PORTBelse PORTB =PORTB if(i=10)i=0;out_date+;if(out_date=2)out_date=0;/call this routine to initialize all peripheralsvoid init_devices(void)/stop errant interrupts until set upCLI(); /disable all interruptsport_init();timer1_init();MCUCR = 0x00;GICR = 0x00;TIMSK = 0x04; /timer interrupt sourcesSEI(); /re-enable interrupts37/all peripherals are now initialized/void main(void)init_devices();/insert your functional code here.38附录 3 电压采集程序;*;模拟数据采集显示电路; 2001.10.08编 ;*;70H-77H存放采样值，78H-7BH 存放显示数据，依次为个位、十位、百位、通道标志;*;* *;* 主程序和中断程序入口 *;* *;*ORG 0000H ;程序执行开始地址LJMP START ;跳至 START执行ORG 0003H ;外中断 0中断入口地址LJMP INT0ORG 0030H;*;* *;* 初始化程序中的各变量 *;* *;*CLEARMEMIO: CLR A ;MOV P2,A ;P2口置 0MOV R0,#70H ;内存循环清 0（70H-7BH）MOV R2,#0CH ;LOOPMEM: MOV R0,A ;INC R0 ;DJNZ R2,LOOPMEM ;MOV A,#0FFH ;MOV P0,A ;P0、P1、P3 端口置 1MOV P1,A ;39MOV P3,A ;RET ;子程序返回;*; ; * 主 程 序 *;*;*;START: LCALL CLEARMEMIO ;初始化MAIN: LCALL DISPLAY ;显示数据一次LCALL TEST ;测量一次AJMP MAIN ;返回 MAIN循环NOP ;PC值出错处理NOP ;空操作NOP ;空操作LJMP START ;重新复位起动DISPLAY: MOV R3,#08H ;8路信号循环显示控制MOV R0,#70H ;显示数据初址（70H-77H）MOV 7BH,#00H ;显示通道路数（0-7）DISLOOP1: MOV A,R0 ;显示数据转为三位十进制 BCD码存入MOV B,#100 ;7AH、79H、78H 显示单元内DIV AB ;显示数据除 100MOV 7AH,A ;商入 7AHMOV A,#10 ;A放入数 10XCH A,B ;余数与数 10交换DIV AB ;余数除 10MOV 79H,A ;商入 79HMOV 78H,B ;余数入 78HMOV R2,#0FFH ;每路显示时间控制 4MS*255DISLOOP2: LCALL DISP ;调四位 LED显示程序DJNZ R2,DISLOOP2 ;每路显示时间控制INC R0 ;显示下一路INC 7BH ;通道显示数值加 1DJNZ R3,DISLOOP1 ;8路显示未完转 DISLOOP1再循环RET ;8路显示完子程序结束; LED共阳显示子程序，显示内容在 78H-7BH，数据在 P1输出，列扫描在 P3.0-P3.3 40DISP: MOV R1,#78H ;赋显示数据单元首址MOV R5,#0FEH ;扫描字PLAY: MOV P1,#0FFH ;关显示MOV A,R5 ;取扫描字ANL P3,A ;开显示MOV A,R1 ;取显示数据MOV DPTR,#TAB ;取段码表首址MOVC A,A+DPTR ;查显示数据对应段码MOV P1,A ;段码放入 P1口LCALL DL1MS ;显示 1MSINC R1 ;指向下一地址MOV A,P3 ;取 P3口扫描字JNB ACC.3,ENDOUT ;四位显示完转 ENDOUT结束RL A ;扫描字循环左移MOV R5,A ;扫描字放入 R5暂存MOV P3,#0FFH ;显示暂停AJMP PLAY ;转 PLAY循环ENDOUT: MOV P3,#0FFH ;显示结束，端口置 1MOV P1,#0FFH RET ;子程序返回;LED数码显示管用共阳段码表，分别对应 0-9，最后一个是熄灭符TAB: DB 0C0H,0F9H,0A4H,0B0H,99H,92H,82H,0F8H,80H,90H,0FFH; 1MS延时子程序，LED 显示用DL1MS: MOV R6,#14H ;DL1: MOV R7,#19HDL2: DJNZ R7,DL2DJNZ R6,DL1RET;模数转换测量子程序TEST: CLR A ;清累加器 AMOV P2,A ;清 P2口MOV R0,#70H ;转换值存放首址MOV R7,#08H ;转换 8次控制LCALL TESTART ;启动测试41WAIT: JB P3.7,MOVD ;等 A/D转换结束信号后转 MOVDAJMP WAIT ;P3.7为 0等待TESTART: SETB P2.3 ;锁存测试通道地址NOP ; 延时 2微秒NOP CLR P2.3 ;测试通道地址锁存完毕SETB P2.4 ; 启动测试，发开始脉冲NOP ; 延时 2微秒NOP CLR P2.4 ; 发启动脉冲完毕NOP ;延时 4微秒NOP NOP RET ;子程序调用结束; 取 A/D转换数据至 70H-77H内存单元MOVD: SETB P2.5 ;8090输出允许MOV A,P0 ;将 A/D转换值移入 AMOV R0,A ;放入内存单元CLR P2.5 ;关闭 8090输出INC R0 ;内存地址加 1MOV A,P2 ;通道地址移入 AINC A ;通道地址加 1MOV P2,A ; 通道地址送 8090CLR C ;清进位标志CJNE A,#08H,TESTCON ; 通道地址不等于 8转 TESTCONT再测试JC TESTCON ; 通道地址小于 8转 TESTCONT再测试CLR A ; 大于或等于 8，A/D 转换结束恢复端口MOV P2,A ; P2口置 0MOV A,#0FFH ;MOV P0,A ; P0口置 1MOV P1,A ; P1口置 1MOV P3,A ; P3口置 1RET ; 取 A/D转换数据结束TESTCON: LCALL TESTART ; 再发测试启动脉冲42LJMP WAIT ; 跳至 WAIT等待 A/D转换结束信号END ; 程序结束致 谢转瞬之间大学五年的生活已经接近尾声，从上学期毕业设计题目的选择到现在顺利的完成，在此过程中我非常感谢我的指导老师李杰老师和胡建明老师，他们给予了我极大的帮助，使我本身受益匪浅。在不久的几个月，我也要踏上教师的工作岗位，老师们那种踏实勤恳、一丝不苟、认真求实的优良品质和学习作风是值得我去学习和发扬的。毕业设计是对我大学五年学习的总结和概括，基本融会了我所学到的知识，在本课题的研究上，虽然我遇到很多麻烦和困难，但是李老师和胡老师都给予了我很大支持和鼓励。从最初的实物制作到程序的编写，一遍一遍的重复调试，使我深深的感受到在任何时候都不要轻言放弃，做人如此，做事亦如此。设计过程加深了我对所学知识的掌握，同时也接触到不少新的知识，既增长了见识，又开阔了眼界。我还要感谢在毕业设计期间帮助过我的同学，在我最需帮助的时候，是他们无私的帮助解决了我的实际困难。同时，我要感谢我的母校天津工程师范学院，大学五年，这里给我留下了美好的回忆。给了我这样一个锻炼的机会，使我加深了对以前知识的理解，拓宽了知识面，也提高了我对所学知识的综合的应用能力。祝愿母校的将来更美好。最后我要对我的老师们说一句老师您辛苦了，衷心的谢谢您！ 毕 业 设 计 开 题 报 告基于 IGBT的变频电源设计 系 别： 电子工程系 班 级： 应用电子技术教育 0201 学生姓名： 梁贵海 指导教师： 李 杰 2006 年 11 月 9 日1毕业论文开题报告课题题目 基于 IGBT的变频电源设计课题性质 A B C D E 课题来源 A B C D 成果形式 A B C D E 同组同学 无开题报告内容（可另附页）指导教师意见（课题难度是否适中、工作量是否饱满、进度安排是否合理、工作条件是否具备等）指导教师签名： 月 日 专家组及系里意见（选题是否适宜、各项内容是否达到毕业设计（论文）大纲要求、整改意见等）专 家 组 成 员签 字： 教学主任（ 签 章）： 月 日2附页：开题报告基于 IGBT的变频电源设计一选题依据：电源设备广泛应用于科学研究、经济建设、国防设施及人民生活等各个方面，是电子设备和机电设备的基础，它与国民经济各个部门相关，在工农业生产中应用的最为广泛。可以说，凡是涉及电子和电工技术的一切领域都要用到电源设备，它不仅提供优质电能，还对科学技术的发展产生巨大的影响。所有用电设备对供电电压、频率、功率都有一定的要求。如一般的电子设备要求电网 220V电压的变化在10%以内频率 50Hz供电系统的功率要足够的大，如果达不到这个要求，设备就不能保证正常工作，甚至可能损坏。一些精密电子仪器对电压稳定、频率、功率的要求更为严格。变频电源正是为满足负载的稳压、频率、功率需求而产生的，其功能是在输入电压或负载在一定范围内变化时自动保持输出电压、功率基本不变并且频率不随负载的性质而变化。变频电源已形成了一个独立的技术领域和一个巨大的市场，在工业、科研、国防等各个方面得到越来越广泛的应用。现在，电源技术的发展使得用新型、高效的开关电源取代传统电源已成为必然。传统的稳压电源一般都是线性电源，这种电源效率低、体积大。随着技术的发展，开关电源的开关频率越来越高，使得电源的小型、轻量化成为可能。电源工作在开关状态，从原理上讲是低损耗的。本课题设计的基于 IGBT的变频电源设计就是用新型的开关电源取代传统电源，其特点就是效率高、体积小、保护完善等。变频电源的分类： 根据输出波形方式，可分为正弦波、方波、三角波等。 根据输出功率大小方式，可分为大功率、中功率、小功率等。二变频电源组成：电源功能及整体结构市电单相电压(220V)经整流滤波后供给逆变电路，IGBT 在驱动信号作用下将整流滤波后的直流电变成一定电压、一定频率的交流电，经隔离滤波后供给负载。输出电压经过取样后送给单片机处理，单片机对取样信号经控制算法处理后输出修正后的SPWM控制信号，使输出电压稳定在所设定的期望值上。电源的基本功能有：输出电3压的显示、过热、过载保护等。电源整体结构图及功能如下图所示：图4 电源整体结构图三关键技术：1.IGBT特性对驱动电路的要求： (1) 提供适当的正反向电压，使 IGBT能可靠地开通和关断。当正偏压增大时 IGBT通态压降和开通损耗均下降，但若 UGE过大，则负载短路时其 IC随 UGE增大而增大，对其安全不利，使用中选 UGE15V为好。负偏电压可防止由于关断时浪涌电流过大而使 IGBT误导通，一般选 UGE=5V 为宜。 (2)IGBT的开关时间应综合考虑。快速开通和关断有利于提高工作频率，减小开关损耗。但在大电感负载下，IGBT 的开频率不宜过大，因为高速开断和关断会产生很高的尖峰电压，及有可能造成 IGBT自身或其他元件击穿。 (3)IGBT开通后，驱动电路应提供足够的电压、电流幅值，使 IGBT在正常工作及过载情况下不致退出饱和而损坏。 (4)驱动电路应具有对 IGBT的保护功能。IGBT 的控制、驱动及保护电路等应与其高速开关特性相匹配，在未采取适当的防静电措施情况下，GE 段不能开路。电压显示 电源电路2EMI滤波 整流滤波 电压可调电压采集显示驱动 单片机 驱动电路桥式逆变输出滤波单片机产生 SPWM生chacheng生电源电路1输出AC4(5)SPWM波的产生，利用单片机用软件产生一个 SPWM波送给 IGBT的驱动电路。2.硬件方案：一般情况下，电源技术的主要内容包括以下几个部分:电力电子器件、功率变换电路、电源整机及系统等。(1)电力电子器件：1)不控性器件：主要是各种功率二极管，包括工频下工作的整流管、整流桥模块、快恢复二极管、功率肖特基二极管等。2)全控型器件：其控制端不但具有控制器件导通的能力，还有控制其关断的能力.例如双极型功率晶体管(GTR)、功率场效应晶体管(MOSFET) 、可关断晶闸管(GTO)还有新型的绝缘门极双极晶体管(IGBT)、静电感应晶体管(SIT) 等。(2)功率变换技术：从电能变换功能来看，有下列二类：1)AC/DC将交流电变为直流电,实现这一功能的变换电路一般称为整流电路。2)DC/AC变换，将直流电变为交流电。实现这一功能的变换电路一般称为逆变电路。(3)控制方式：在变换过程中，使 IGBT功率器件工作在开关状态，在控制信号作用下按设定的时序轮流导通(关断)，从而实现电能的变换。对于控制 IGBT功率器件工作在开关状态方式，可以归纳出下列二种：1）频率控制方式：指控制信号幅度的变化转换成功率器件的触发脉冲频率的变化，在逆变电源中常用这种控制方式。2）斩波控制方式：指控制信号幅度的变化转换成功率器件“导通时间比”的变化，在直流变换电路中常用这种控制方式。本设计使用以上两种组合方式，构成正弦波脉冲宽度调制方式(SPWM)，这是交流变换器中常用的方式。 53.软件方案：图 2 软件控制主程序流程图 3 软件控制子程序流程四主要技术指：（1） IGBT/SPWM脉波宽度调变方式 （2） 单相交流输入电压 AC220V10% 频率 50/60Hz5%（3） 65V-115V/400Hz正弦波交流输出（4） LED四位数码管显示电压预期可以达到输出一个 220V/400Hz无明显失真的正弦波信号，IGBT 的驱动能力为 100W,并且具有完善的保护措施的变频电源。装载定时器初始化开中断结束关中断输出口取反中断入口重新装载定时器开中断退出中断6五准备情况及进度计划：序号 毕业设计阶段性工作及成果 时间安排1 查找资料，确定方案 早期进入阶段2了解毕业设计涉及的问题，及硬件电路的基本设计1周3 学习单片机的相关知识 2周4 购买元器件及焊接一些单元电路 3-4周5 调试电路板 5-6周6 调试硬件和软件，完成系统的组合 7-9周7 完成毕业论文、答辩 10-12周六参考文献：1 张燕宾.SPWM 变频调速应用技术.北京:机械工业出版社,2003.2 钟福金,钱昱明.面积等效法生成SPWM波形的控制算法及软件研究.电气自动化.1999(6),14-18. 3 童诗白主编.模拟电子技术基础.北京：高等教育出版社，1998.4 周志敏,周纪海等.IGBT 和 IPM及其应用电路.北京:人民邮电出版社,2006.5 WU Xunwei,HANG Guoqiang,Massoud Pedram. Low power DC circuits employing AC power supply, SCIENCE IN CHINA (INFORMATION SCIENCES), 2002 Vol.45 No.3, 232.6 陈国呈.PWM变频调速技术.北京:机械工业出版社,1999. 7 刘瑞新,赵全利等.单片机原理及应用教程.北京:机械工业出版社,2003. 8 梅丽风,王艳秋等.单片机原理及接口技术.北京:清华大学出版社,2004.9 李广弟,朱月秀等.单片机基础.北京:北京航空航天大学出版社,2001.10 徐爱钧.8051 单片机实践教程,北京:电子工业出版社,2001 年11 康华光,邹寿彬.电子技术基础（数字部分）,北京:高等教育出版社,200312 秦玲,刘敬波.一种用于 D/A转换电路的带隙基准电压源的设计,电子设计应用.2006(5)35-42.13 吴国经.单片机应用技术,北京:中国电力出版社,200414 吴运昌.模拟集成电路原理与应用.广东:华南理工大学出版社,2001.15 高吉祥,黄智伟等.数字电子技术.北京:电子工业出版社,2003.16 吴金戎.8051 单片机实践与应用.北京:清华大学出版社,2002.17 李序葆,赵永健.电力电子器件及其应用.北京:机械工业出版社,2003.718 王志良.电力电子新器件及其应用技术.北京:国防工业出版社,1995. 天津工程师范学院毕业设计（论文）中期报告系别 电子工程系 班级 应教 0201 学生姓名 梁贵海 指导教师 李杰课题名称： 基于 IGBT 的变频电源设计简述开题以来所做的具体工作、取得的进展及下一步主要工作：在毕业设计的最初阶段, 认真阅读资料，了解 IGBT 的基本原理及应用前景、其工作原理以及控制方法。并进行了以下几步工作：（1） 、查找整理资料，学习相关知识。（2） 、经过查阅相关资料，选择比较可取的电路,对所设计的电路进行分析论证。（3） 、画出系统的流程，画出硬件设计图。之后,分析各部分模块电路的具体作用，分析工作原理。查找元器件的主要功能特性、内部结构及各引脚的作用，尽量选择最适合的元器件，列元件清单，购买器件。根据之前整理的资料进行电路焊接。分模块的对电路进行调试，成功的调试完一些基本的单元电路，总结调试经验。下一步的主要任务:（1） 、对未完成的电路继续制作。（2） 、对单片机软件进行初始的编程。（3） 、软件的后期调试及硬件电路的故障排除。（4） 、对整个电路进行系统调试，达到稳定，最后实现本课题所要实现的目标。一周的时间进行毕业论文的准备,最后准备毕业答辩。学生签字：年 月 日指导教师的建议与要求：指导教师签字：年 月 日注：本表格同毕业设计（论文）一同装订成册，由所在单位归档保存。1英文资料及中文翻译 The Design of a Rapid Prototype Platform for ARM Based Embedded SystemHardware prototype is a vital step in the embedded system design. In this paper, we discuss our design of a fast prototyping platform for ARM based embedded systems, providing a low-cost solution to meet the request of flexibility and testability in embedded system prototype development. It also encourages concurrent development of different parts of system hardware as well as module reusing. Though the fast prototyping platform is designed for ARM based embedded system, our idea is general and can be applied to embedded system of other types. I.INTRODUCTIONEmbedded systems are found everywhere, including in cellular telephones, pagers, VCRs, camcorders, thermostats, curbside rental-car check-in devices, automated supermarket stockers, computerized inventory control devices, digital thermometers, telephone answering machines, printers, portable video games, TV set-top boxes - the list goes on. Demand for embedded system is large, and is growing rapidly. In order to deliver correct-the-first-time products with complex system requirements and time-to-market pressure, design verification is vital in the embedded system design process. A possible choice for verification is to simulate the system being designed. If a high-level model for the system is used, simulation is fast but may not be accurate enough, with a low-level model too much time may be required to achieve the desired level of confidence in the quality of the evaluation. Since debugging of real systems has to take into account the behavior of the target system as well as its environment, runtime information is extremely important. Therefore, static analysis with simulation methods is too slow and not sufficient. And simulation cannot reveal deep issues 2in real physical system. A hardware prototype is a faithful representation of the final design, guarantying its real-time behavior. And it is also the basic tool to find deep bugs in the hardware. For these reasons, it has become a crucial step in the whole design flow. Traditionally, a prototype is designed similarly to the target system with all the connections fixed on the PCB (printed circuit boards).As embedded systems are getting more complex, the needs for thorough testing become increasingly important. Advances in surface-mount packaging and multiple-layer PCB fabrication have resulted in smaller boards and more compact layout, making traditional test methods, e.g., external test probes and bed-of-nails test fixtures, harder to implement. As a result, acquiring signals on boards, which is beneficial to hardware testing and software development, becomes infeasible, and tracking bugs in prototype becomes increasingly difficult. Thus the prototype design has to take account of testability. However, simply adding some test points is not enough. If errors on the prototype are detected, such as misconnections of signals, it could be impossible to correct them on the multiple-layer PCB board with all the components mounted. All these would lead to another round of prototype fabrication, making development time extend and cost increase.Besides testability, it is important to maintain high flexibility during development of the prototype as design specification changes are common. Nowadays complex systems are often not built from scratch but are assembled by reusing previously designed modules or off-the-shelf components such as processors, memories or peripheral circuitry in order to cope with more aggressive time-to-market constraints. Following the top-down design methodology, lots of effort in the design process is spent on decomposing the customers, requirements into proper functional modules and interfacing them to compose the target system.Some previous research works have suggested that FPLDs (field programmable logic device) could be added to the final design to provide flexibility as FPLDs can offer programmable interconnections among their pins and many more advantages. However, extra devices may increase 3production cost and power dissipation, weakening the market competition power of the target system. To address these problems, there are also suggestions that FPLDs could be used in hardware prototype as an intermediate approach 1-3, whereas this would still bring much additional work to the prototype design. Moreover, modules on the prototype cannot be reused directly. In industry, there have been companies that provide commercial solutions based on FPLDs for rapid prototyping 4. Their products are aimed at SOC (system on a chip) functional verification instead of embedded system design and development.In this paper, we discuss our design of a Rapid Prototyping Platform for ARM based Embedded System, providing a low cost solution to meet the request of flexibility and testability in embedded system prototype development. It also encourages concurrent development of different parts of system hardware as well as module reusing. The rest of the paper is organized as follows. In section 2, we discuss the details of our rapid prototyping platform. Section 3 shows the experimental results, followed by an overall conclusion in section 4.II. THE DESIGN OF A RAPID PROTOTYPING PLATFORMA. OverviewARM based embedded processors are wildly used in embedded systems due to their low-cost, low-power consumption and high performance. An ARM based embedded processor is a highly integrated SOC including an ARM core with a variety of different system peripherals5. Many arm based embedded processors, e.g.6-8, adopt a similar architecture as the one shown in Fig. 1.4The integrated memory controller provides an external memory bus interface supporting various memory chips and various operation modes (synchronous, asynchronous, burst modes). It is also possible to connect bus-extended peripheral chips to the memory bus. The on-chip peripherals may include interrupt controller, OS timer, UART, I2C, PWM, AC97, and etc. Some of these peripherals signals are multiplexed with general-purpose digital I/O pins to provide flexibility to user while other on-chip peripherals, e.g. USB host/client, may have dedicated peripheral signal pins. By connecting or extending these pins, user may use these onchip peripherals. When the on-chip peripherals cannot fulfill the requirement of the target system, extra peripheral chips have to be extended.The architecture of an ARM based embedded system is shown in Fig. 2. The whole system is composed of embedded processor, memory devices, and peripheral devices. To enable rapid prototyping, the platform should be capable of quickly assembling parts of the system into a whole through flexible interconnection. Our basic idea is to insert a reconfigurable interconnection module composed by FPLD into the system to provide adjustable connections between signals, and to provide testability as well. To determine where to place this module, we first analyze the architecture of the system.The embedded system shown in Fig. 2 can be divided into two parts. One is the minimal system composed of the embedded processor and memory devices. The other is made up of peripheral devices extended directly 5from on-chip peripheral interfaces of the embedded processor, and specific peripheral chips and circuits extended by the bus.The minimal system is the core of the embedded system, determining its processing capacity. The embedded processors are now routinely available at clock speeds of up to 400MHz, and will climb still further. The speed of the bus connecting the processor and the memory chips is exceeding 100MHz. As pin-to-pin propagation delay of a FPLD is in the magnitude of a few nanoseconds, inserting such a device will greatly impair the system performance.The peripherals enable the embedded system to communicate and interactive with the circumstance in the real world. In general, peripheral circuits are highly modularized and independent to each other, and there are hardly needs for flexible connections between them.Here we apply a reconfigurable interconnection module to substitute the connections between microcomputer and the peripherals, which enables flexible adjusting of connections to facilitate interfacing extended peripheral circuits and modules. As the speed of the data communication between the peripherals and the processor is much slower than that in the minimal system, the FPLD solution is feasible.Following this idea, we design the Rapid Prototyping Platform as shown in Fig. 3. We define the interface ICB between the platform and the embedded processor core boar that holds the minimal system of the target embedded system. The interface IPB between the platform and peripheral 6boards that hold extended peripheral circuits and modules is also defined. These enable us to develop different parts of the target embedded system concurrently and to compose them into a prototype rapidly, and encourage module reusing as well. The two interfaces are connected by a reconfigurable interconnect module. There are also some commonly used peripheral modules, e.g. RS232 transceiver module, bus extended Ethernet module, AC97 codec, PCMCIA/CompactFlash Card slot, and etc, on the platform which can be interfaced through the reconfigurable interconnect module to expedite the embedded system development.B. Reconfigurable Interconnect ModuleWith the facility of state-of-arts FPLDs, we design a reconfigure interconnection module to interconnect, monitor and test the bus and I/O signals between the minimal system and peripherals.As the bus accessing obeys specific protocol and has control signals to identify the data direction, the interconnection of the bus can be easily realized by designing a corresponding bus transceiver into the FPLD, whereas the interconnection of the I/Os is more complex. As I/Os are multiplexed with on-chip peripherals signals, there may be I/Os with bi-direction signals, e.g. the signals for on-chip I2C9 interface, or signals for on-chip MMC (Multi Media Card10) interface. The data 7direction on these pins may alter without an external indication, making it difficult to connect them via a FPLD. One possible solution is to design a complex state machine according to corresponding accessing protocol to control the data transfer direction. In our design we assign specific locations on the ICB and IPB interfaces to these bi-direction signals and use some jumpers to directly connect these signals when needed. The problem is circumvented at the expense of losing some flexibility.The use of FPLD to build the interconnection module not only offers low cost and simple architecture for fast prototyping, but also provides many more advantages. First, interconnections can be changed dynamically through internal logic modification and pin re-assignment to the FPLD. Second, as FPLD is connected with most pins from the embedded processor, it is feasible to detect interconnection problems due to design or physical fabricate fault in the minimal system with BST (Boundary-Scan Test, IEEE Standard 1149.1 specification). Third, it is possible to route the FPLD internal signals and data to the FPLDs I/O pins for quick and easy access without affecting the whole system design and performance. It is even possible to implement an embedded logical analyzer into the FPLD to smooth the progress of the hardware verification and software development.C. Power SupplyPower dissipation has a great impact on system cost and reliability. It is an increasingly important problem in embedded systems designs not only for the portableelectronics industry but in other areas including consumer electronics, industry control, communications, etc. In order to facilitate the design of power supply for the target embedded system, power supply issues have also been considered in the design of the platform.First, the power supplies to the devices on the platform are separated from those to the core board and peripheral expand boards, which makes it more realistic to measure and verify the power dissipation on the platform for the target embedded system. Second, the power supplies for the core board and peripheral expand boards are built on a 8separate board and connected to the platform through a slot. As a result, it provides flexibility for power system design while speeding up the whole design process.To meet the demand for higher system speed and lower power consumption in data communications and processing, embedded processor vendors use increasingly advanced processing technologies requiring lower core operating voltages, and keep the interface voltage compatible with most low voltage semiconductor devices on market. Consequently, almost every embedded processor requires more than one power supply, such as power supply for internal logic, for PLLs and oscillators, for memory bus interface, and for other I/Os. Further, different embedded processors may have different requirements on power supply, such as different power supply voltage, power-up sequence, and different strategies to adjust the core voltage in different CPU run mode for minimizing power dissipation.A survey of some widely used ARM based embedded processor suggests that most of them need no more than 3 groups of separated power supply, as shown in Table 1. As the peripherals may require different supply voltages for special purpose, such as +5V for powering the USB ports, we divide the power supply from the power supply slot into 4 separated channels, which is connected to both the core board slot and the peripheral board slot. Each channel of power supplies has a “power good” signal to indicate power output status of the channel, and a shutdown signal to shut the power supply of the channel down. And these 9signals are directly connected to the core board slot to accommodate the embedded processors requirement of power-up sequence. In order to enable dynamic voltage adjusting, some control signals are routed to the power supply board by the reconfigurable interconnect module.III. EXPERIMENTAL RESULTSAs the Rapid Prototyping Platform is still under development, we present an example applied with the same considerations in the Rapid Prototyping Platform. It is an embedded system prototype based on Intel XScale PXA255, which is an ARM based embedded processor. The diagram of the prototype is illustrated in Fig. 5(a). The photo is shown in Fig. 5(b), where a Bluetooth module is connected to the prototype USB port and a CF LAN card is inserted.10The FPGA (an Altera Cyclone EP1C6F256) here offers the same function as the reconfigurable interconnection module shown in Fig. 3. Most of the peripheral devices are expanded to the system through the FPGA, and more peripherals can be easily interfaced when needed. As both of the FPGA and PXA255 support the BST, we can detect faults, e.g. short-circuit and open-circuit faults, on the connections between the two devices by chaining their JTAG ports and performing BST. Here, we use an open source software package 11 to perform the BST.The FPGA internal signals can be routed to the debugging LED matrix for easy access, which is helpful in some simple testing and debugging. We also insert an embedded logical analyzer, the SignalTap II embedded logic analyzer 12 provided in Alteras Quartus II software, into the FPGA for handling more complicated situations. With the help of the logical analyzer, we are able to capture and monitor data passing through over a period of time, which expedites the debugging process for the prototype system. Fig. 6 shows the captured data communication between the embedded processor and the USB host module during the initialization process of the Philips ISP1161 USB host chip13. It can be seen clearly from the figure that the embedded processor writes the command code of 0027H to address 01H (the ISP1161s host controller command port) to access the HcChipID register, and reads 6120H (the chips ID) from 11address 00H (the ISP1161s host controller data port).The power supply module of the prototype system is held on a separate board connected to the system via a socket. We designed two power supply modules for the prototype system (shown in Fig. 7). One is a large module providing fixed output composed with simple but low-efficiency linear regulator (the upside one in the Fig. 7), the other is a compact module, capable of dynamic voltage adjusting, made up of complex high-efficiency switch regulator(the downside one in the Fig. 7). The former module is
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