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基于单片机的指纹识别电子密码锁设计,基于,单片机,指纹识别,电子,密码锁,设计
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毕业设计（论文）中期报告系别 班级 学生姓名 指导教师课题名称：基于单片机的指纹识别电子密码锁设计从开题以来我所做的具体工作以及取得的进展和下一步主要工作：从开题以来，我就已经开始从网上、图书馆等搜集有关指纹识别模块、密码锁的各种相关资料，为系统方案的论证和系统的总体设计以及最后的论文撰写收集所需材料。对系统的方案论证和元件选择等重新做了论证。在论证结束后，我就开始根据收集的资料进行密码锁系统硬件电路的设计，根据系统的基本要求选择器件。系统的控制采用 ATmeg16 单片机，指纹识别模块采用ZAZ-010 深圳指昂公司生产的 UART 型指纹识别模块。在硬件电路设计完成后，我列出了所需的元件清单准备购买元件。在元件购买结束后，就开始进行硬件电路的焊接。到目前为止，硬件电路已经焊接完毕，对照设计的原理图进行硬件电路检查已完成，正开始参照查阅的相关资料进行程序的设计。等程序设计完成后进行电路的调试。下一步的重点工作就是继续电路的调试,使其尽可能的达到所有技术指标。并撰写毕业设计论文，完成设计任务。按照目前的工作进度，在串口通信和识别率方面不太理想化。是目前存在的最大问题。在接下来的时间准备在程序调试方面进行努力！。在基本功能实现的基础上尽量添加实用的功能，终取实现系统的最大利用率。学生签字：2010 年 5 月 14 日指导教师的建议与要求：指导教师签字：年 月 日注：本表格同毕业设计（论文）一同装订成册，由所在单位归档保存。毕业设计（论文）任务书题 目(包括副标题)基于单片机的指纹识别电子密码锁教师姓名 职 称 系 别学生姓名 学 号 班 级成果形式A 论文 B 设计说明书 C 实物 D 软件 E 作品 任务下达时间2009 年 12 月 18日1毕业设计（论文）课题任务的内容和要求：（包括原始数据、技术要求、工作要求以及图纸、程序、实物等要求）（1）毕业设计主要内容 搜集 ATMEG16 单片机知识、单片机外围电路设计的相关资料 单片机控制的软硬件设计与实现 本专业英语译文 5000 字符以上写论文（10000 字以上） 、毕业答辩（2）毕业设计的主要技术指标 设计基于单片机的指纹识别电子密码锁（3）毕业设计基本要求 完成软硬件设计、画出硬件原理图、软件程序编写调试电路及程序、 翻译相关英文资料 收集的文献资料（包括 ATMEG 16 单片机及模块资料） 写出完整的设计论文2毕业设计（论文）工作进度计划：周 次 工作内容12-46-88-10收集参考资料设计制作硬件电路软件测试、完成电路调试完成论文，准备答辩教研室（学科组）主任签字： 毕 业 设 计 开 题 报 告基于单片机的指纹识别电子密码锁系 别： 班 级： 学生姓名： 指导教师： 2009 年 12 月 18 日开题报告填写要求1开题报告作为毕业设计答辩委员会对学生答辩资格审查的依据材料之一，应在指导教师指导下，由学生在毕业设计工作前期完成，经指导教师签署意见、专家组及系主任审查后生效；2开题报告必须用黑墨水笔工整书写或按教务处统一设计的电子文档标准格式（可从教务处网页上下载）打印，禁止打印在其它纸上后剪贴；3毕业设计的开题报告应包括以下内容：（1）主要技术指标；（2）工作思路；（3）课题的准备情况及进度计划；（4）参考文献。4开题报告的撰写应符合科技文献规范，且不少于 2000 字；参考文献应不少于 15 篇，包括中外文科技期刊、教科书、专著等。 5开题报告正文字体采用宋体小四号，1.5 倍行距。附页为 A4 纸型，左边距 3cm，右边距 2cm，上下边距为 2.5cm，字体采用宋体小四号，1.5 倍行距。6 “课题性质”一栏： 理工类：A.理论研究 B.应用研究 C 工程设计 D.软件开发 E.其它 经管文教类：A.理论研究 B.应用研究 C.实证研究 D.艺术创作 E.其它“课题来源”一栏：A.科研立项 B.社会生产实践 C.教师自拟 D.学生自选“成果形式”一栏：A.论文 B.设计说明书 C.实物 D.软件 E.作品毕业设计开题报告课题题目 基于单片机的指纹识别电子密码锁设计课题性质 A B C D E 课题来源 A B C D 成果形式 A B C D E 同组同学 无开题报告内容（可另附页）指导教师意见（课题难度是否适中、工作量是否饱满、进度安排是否合理、工作条件是否具备等）指导教师签名： 月 日 专家组及系里意见（选题是否适宜、各项内容是否达到毕业设计（论文）大纲要求、整改意见等）专 家 组 成 员签 字： 教学主任（ 签 章）： 月 日基于单片机的指纹识别电子密码锁设计一、 研究目的 随着社会的发展和技术的进步，传统的安全防盗系统面临极大的挑战。生物识别技术是根据人的体貌、声音等生物特征进行身份验证的科学解决方案，现有的生物识别技术大致上包括指纹识别技术、掌纹识别技术、视网膜识别技术、虹膜识别技术、面相识别技术等。生物识别技术优势主要有：1、减少、消除身份假冒进行真实身份的确认 ：2、降低管理的成本，取代了身份人工人证的的过程：3、方便使用者，减少或消除了使用卡、钥匙或者密码的麻烦。生物识别技术的发展起始于指纹研究，它亦是目前应用最广泛的生物识别技术。为了有效地的防止信息资料，财产的安全生物识别技术的安全系数较传统意义上的身份验证机制有了很大提高，越来越得到社会的重视。指纹锁和指纹门禁是应用最广的生物识别技术。随着计算机技术的广泛应用和指纹识别技术的迅速成熟，物美价廉的指纹识别产品广泛应用于商业市场同时逐渐进入家庭。国内外科研人员很早就致力于指纹识别的检测方法，研制各式各样的指纹识别的模块及其应用产品，用于保险箱、实验室、楼道的身份确认等。二、 主要任务及主要技术指标：1设计单片机指纹识别电子密码锁。2学习掌握主控 Atmeg16 单片机的工作原理及内部。 3了解指纹识别的原理。4选择合适的指纹识别模块。5程序联机调试。6完成单片机指纹识别电子密码锁使之达到存储 3 个指纹，并能准确识别显示。三、 器件选择：1主要控制 Atmeg16 单片机具有下列主要性能高性能、低功耗的 8 位AVR 微处理器先进的RISC 结构 131 条指令 大多数指令执行时间为单个时钟周期32个可编程的I/O口两个可编程的串行USARTAtmeg16 单片机的管脚说明如图所示RESET9XTAL212 XTAL113GND31PD7(OC2)21 PD6(ICP1)20 PD5(OC1A)19PD4(OC1B)18 PD3(INT1)17 PD2(INT0)16PD1(TXD)15 PD0(RXD)14GND 11AREF 32AVCC30VCC 10PC7(TOSC2) 29PC6(TOSC1)28PC5(TDI) 27PC4(TDO) 26PC3(TMS)25PC2(TCK) 24PC1(SDA) 23PC0(SCL)22PB5(MOSI)6 PB6(MISO)7PB7(SCK)8 PA7(ADC7) 33PA6(ADC6)34PA5(ADC5) 35PA4(ADC4) 36PA3(ADC3)37PA2(ADC2) 38PA1(ADC1) 39PA0(ADC0)40PB0(XCK/T0)1PB1(T1)2 PB2(INT2/AIN0)3PB3(OC0/AIN1)4 PB4(SS)5MEG162.指纹模块选择指纹采集比对搜索模板采用 ZAZ-010 系列独立式指纹识别模块是深圳市指昂科技有限公司研发和制造推出的体积一体化指纹模块。以高速 DSP 处理器为核心. 具有指纹录入、图像处理、指纹比对、搜索和模板储存等功能的智能型模块.。指纹模块技术参数:供电电压：DC 3.66.0V 供电电流： 工作电流：100mA（典型值） 峰值电流：150mA 指纹图像录入时间：小于 0.5 秒 窗口面积：1418mm 比对方式（1：1） 存储容量：100 枚 认假率（FAR）：小于 0.001拒真率（FAR）：小于 0.1上位机接口：UART（TTL 逻辑电平）通讯波特率（UART）：（9600N）bps 其中 N112（默认值 N6，即57600bps） 模块：28198.5mm 指纹传感器：562021.5m 上电延时：500ms 进行初始化3. 单片机最小系统所需元器件单片机最小系统所需元器件，另需一 4 个按键，继电器 和状态指示二极管，在显示部分采用 HS12864-15C 系列通用型液晶显示模块.带中文简体字库液晶显示模块：内含 16*16 中文点阵字库和 8*8 及 8*16ASCII 码字库、编码调用字库、可图文混排显示、采用 ST7920 控制芯片、实现无时序握手协议、编程简单方便功耗低、显示清晰、功能强大、单一 5V 驱动、是智能型仪器仪表的较佳显示方式。 四、 工作思路以 Atmeg16 单片机作为核心微控制器通过单片机串口通信发送指令控制指纹识别模块进行存贮指纹比对指纹的作业。具体工作原理如下1.指纹登陆的过程指纹登陆时通过 at98s52 单片机发出指令，通过光学传感器对每一枚指纹录入两次，将两次录入的图象进行处理，合成模板存储于模块中。2.指纹匹配的过程通过指纹头传感器录入要验证指纹的图像并进行处理，然后于模块中的指纹模板进行进行匹配比较（若与模块中指定的一个模板进行匹配，称为指纹比对方式，即1：1 方式。若与多个模板进行匹配，称为指纹搜索方式即 1：N 方式） ，模块给出匹配结果（即通过或失败） 。通过串口传输给单片机，同时单片机做出相应的反映控制液晶显示或控制继电器吸和指使灯点亮。3.系统的具体组成单元框图 AT MEG16 单片机 LCD指纹模块4 个独立按键以及继电器和指示灯五、 课题的准备情况及进度计划序号毕业设计阶段性工作及成果 时间安排1 查找资料，确定方案 早期进入阶段2 资料的收集、整理，了解毕业设计涉及的问题 1 周3 学习单片机的相关知识 2-3 周4 购买元气件 4 周5 焊接、调试电路板 5-6 周6 调试硬件、软件、完成系统组合 7-8 周7 完成毕业论文、答辩 9-10 周六、 参考文献1 何希才，薛永毅,传感器及应用实例M，第 1 版，北京：机械工业出版社.2004 年2 吕泉，张洪润.现代传感器原理及应用M，第 1 版，北京：清华大学出版社.2006 年3 吴金戌 ，沈庆阳，郭庭吉.8051 单片机实践与应用M，第 1 版，北京：清华大学出版社.2006 年4 李广弟，朱月秀，王秀山.单片机基础M, 第 2 版，北京：北京航空航天大学出版社.2003 年5 楼然苗，李光飞.51 系列单片机设计实例M，第 2 版，北京：北京航空航天大学出版社.2006 年6 李序葆,赵永健.电力电子器件及其应用M,第 1 版,北京：机械工业出版社,2003 年7 王志良.电力电子新器件及其应用技术M.第 3 版,北京：国防工业出版社 1995 年8 吴运昌.模拟集成电路原理与应用M,第 1 版,广东：华南理工大学出版社,2001 年9 高吉祥,黄智伟,丁文霞.数字电子技术M,第 1 版,北京：电子工业出版社,2003 年10 周兴华.单片机智能化产品 C 语言设计实例详解M.北京：北京航空航天大学出版社，2006 年11 肖金球. 单片机原理与接口技术M. 清华大学出版社，2004-11 月12 李朝青. 单片机学习指导M. 北京航空航天大学出版社，2002-1 月13 徐煜明，韩雁. 单片机原理及接口技术M.电子工业出版社，2005 年14 高锋单片机系统设计与实用技术M北京：机械工业出版社，2002年15 李朝青 . 单片机原理及接口技术 M. 北京航空航天大学出版社，2003年摘要近年来，指纹识别技术在国内外发展很快，由于其良好的安全性目前该技术已被广泛应用于生活和工作中。随着成本的下降，指纹识别技术呈现全面推广和普遍应用的趋势。指纹识别技术是目前国际公认的应用广泛、价格低廉、易用性高的生物人证技术。指纹只是人体皮肤的一小部分，但是它却蕴涵了大量的信息。皮肤的纹路在图案断点交叉点是个不相同的。医学上已经证明这些特征对于每个手指都是不同的，而且这些特征具有唯一性和永久性。因此我们就可以把一个人同他的指纹对应起来，通过比较他的指纹特征和预先保存的指纹特征，就可以验证他的真实身份。本设计开发了一款基于单片机的指纹识别电子密码锁系统。该系统以 ATmeg16单片机作为模块核心，通过串口通信控制 ZAZ-010 指纹模块实现录取指纹并存储指纹数据，并通过 HS12864-15C 液晶显示比对流程及比对结果，辅以直流继电器与发光二极管模拟开锁的动作。本系统具有体积小、性价比高、传输速度快、适合家庭及单位使用。关键词：单片机；指纹识别；液晶屏ABSTRACTIn recent years, fingerprint identification technology has developed rapidly in China and abroad, because of its good security now that the technology has been widely used in daily life and work. With the decline in the cost of the fingerprint recognition technology and the comprehensive promotion and general trends should be. Fingerprint recognition technology is a technology of biology-authentication widely used and legalized in international today because of its low-price and finer application. Fingerprint just is a small part of the skin, but it contains a great deal of information .The veins of the skin are different in pattern and cross point and break point. Medicine has proven that these characteristics are different for each finger and these characteristics are unique and permanent. So we can put a persons fingerprints correspond with him by comparing his fingerprint characteristics and pre-stored fingerprint features, you can verify his true identity. The system design of fingerprint recognition electron password lock based on Single-chip microprocessor is developed in the thesis. The system ATmeg16 MCU as the core module, through the serial communication control ZAZ-010 fingerprint module for taking fingerprints and store fingerprint data and liquid crystal display by HS12864-15C ratio than on the processes and results, supported by simulation of DC relays and LEDs unlock action. The system is small, cost-effective, and fast and suitable for families and units.Key Words：Single-chip microprocessor; fingerprint detection; LCD 1英文资料及中文翻译A hybrid ASIC and FPGA ArchitectureFPGA is English Field Programmable Gate Array abbreviation, namely the scene programmable gate array, it is the product which in PAL, GAL, EPLD and so on in the programmable component foundation further develops. It is took in the special-purpose integrated circuit (ASIC) domain one kind partly has custom-made, both solves has had custom-made the electric circuit which the electric circuit appears the insufficiency, and has overcome the original programmable component gate number limited shortcoming. FPGA used logical unit array LCA (Logic Cell Array) this kind of new concept, the interior including has been possible to dispose logical module CLB (Configurable Logic Block), output load module IOB (Input Output Block) and internal segment (Interconnect) three parts. The FPGA essential feature mainly has:1) Uses FPGA to design the ASIC electric circuit, the user does not need to throw the piece production, can obtain the chip which comes in handy. - - 2) FPGA may make other all to have custom-made or partly to have custom-made the ASIC electric circuit the experimental preview.2) The FPGA interior has the rich trigger and the I/O pin. 3) FPGA is in the ASIC electric circuit designs the cycle to be shortest, the development cost is lowest, one of risk smallest components.4) FPGA is in the ASIC electric circuit designs the cycle to be shortest, the development cost is lowest, one of risk smallest components.5) FPGA uses the high speed CHMOS craft, the power loss is low, may and CMOS, the TTL level is compatible. It can be said that, the FPGA chip is the small batch system enhances the system integration rate, one of reliable best choices. FPGA is by deposits the procedure establishes its active status in internal RAM, therefore, time work needs to carry on the programming to internal RAM .The user may act according to the different disposition pattern, selects the different programming method. When adds the electricity, the FPGA chip the data read-in internal programs 2EPROM in RAM, after the disposition completes, FPGA thrust build-up .After falls the electricity, FPGA restores the unsoldered glass, internal logic relations vanishing, therefore, FPGA can use repeatedly. The FPGA programming does not need the special-purpose FPGA programmer, only must use general EPROM, the PROM programmer then. When needs to revise the FPGA function, only must trade piece of EPROM then. Thus, identical piece FPGA, the different programming data, may have the different electric circuit function. Therefore the FPGA use is extremely flexible. FPGA has many kinds of disposition pattern: Parallel principal-mode -like is piece of FPGA adds piece of EPROM the way; The host may support piece of PROM from the pattern to program multi-piece FPGA; The serial pattern may use serial PROM to program FPGA; The peripheral pattern may FPGA take the microprocessor the peripheral, programs by the microprocessor to it.In the electrical observation and control system, needs to gather each kind of simulation quantity signal, the digital quantity signal frequently, and carries on corresponding processing to them. In the ordinary circumstances, in the observation and control system with ordinary MCU (for example 51, 196 and so on monolithic integrated circuits or control DSP) is may complete the system task.。But when in the system must gather the signal quantity are specially many when (is specially each kind of signal quantity, condition quantity), depends on merely with the ordinary MCU resources on often with difficulty completes the task。This time, generally only can adopt the multi-MCU in-line processing pattern, or depends on other chip expansion system resources to complete the system the monitor duty. Not only did this increased the massive exterior electric circuits and the system cost, moreover increased the system complexity greatly, thus the system reliability could receive certain influence, this was not obviously the designer is willing to see. One kind based on the FPGA technology simulation quantity, digital quantity gathering and the processing system, uses FPGA the I/O port to be many, also may program the control freely, define its function the characteristic, matches by VHDL the compilation FPGA interior execution software, can solve gathering signal way many problems well。Because compiles with VHDL the execution software interior to each group of digital quantity is according to the parallel processing, moreover the FPGA hardware speed is the ns level, this 3is a speed which current any MCU all with difficulty achieved, therefore this system compared to other systems can real-time, monitor the signal quantity fast the change。Therefore in the condition quantity specially many monitor system, this system will be able to display own superiority.The practice proved that, Designs the DDS electric circuit with FPGA to use the special-purpose DDS chip to be more nimble. Because, so long as changes in FPGA the ROM data, DDS may have the random profile, thus has the quite big flexibility。Comparatively: The FPGA function is decided completely by the design demand, may complex also be possible to be simple, moreover the FPGA chip also supports in the system scene promotes, although has the insufficiency slightly in the precision and the speed, but also can satisfy the overwhelming majority system basically the operation requirements. Moreover, inserts the DDS design in the system which constitutes to the FPGA chip, its system cost cannot increase how many, but purchases the special-purpose chip the price is the former very many times. Therefore uses FPGA to design the DDS system to have the very high performance-to-price ratio.1 Applications Emerge for Hybrid DevicesImplementation using an ASIC approach typically yields a faster, smaller, and lower power design than implementation in FPGA technology. The growing requirements in the marketplace for design flexibility however, are driving the need for hybrid ASIC/FPGA devices. The potential to change hardware configuration in real time, to support multiple design options with a single mask set, and to prolong a products usable life, all compel designers to look for a blending of high density ASIC circuits along with the inherent FPGA circuit flexibility.The ability to create a “base design” and then reuse the base with minimal changes for subsequent devices helps reduce design time and encourages standardization. Since many consumer and office products are offered with a range of low to high-end options, this base design concept can be effectively used-with features added to each successive model. Printers, fax machines, PC s and digital imaging equipment are example where this concept can be usefulDSP applications are also well suited to FPGA fast multiply and accumulate (MAC) processing capability. When building a DSP system, the design can take advantage of parallel structures and arithmetic algorithms to minimize 4resources and exceed performance of single or multiple purpose DSP devices. DSP designers using both ASIC and FOGA within the same design can optimize a system for performance beyond the capabilities of either separate circuit technology.Other applications that lend themselves to the hybrid ASIC/FPGA approach are designs that support multiple standards such as USB, Fire Wire and Camera LINK, in a single device. Similarly, designs that are finalized, with the exception of any undefined features or emerging standard, are excellent candidates for this technology. Without the benefit of programmable logic, the designer must decide between taping-out the chip knowing that the PCI logic has a high probability for change, or waiting until the design requirements are firm-potentially impacting the end products schedule. With both programmable logic and ASIC working together on a single device, some situation like these can be accommodated. Other similar issues like differing geographic or I/O standards could also be incorporated within the FPGA cores, without requiring mask and fabrication updates for each change.10.2 Economics Play a Role in Using Hybrid DevicesWhile technical applications are emerging for the hybrid architecture, it is unlikely that design teams would utilize this new capability unless it is also economically viable. We will now explore the economics behind this new architecture.To realize the performance and density advantages of an ASIC ,design teams must accept higher NRE and longer TAT than a FPGA. Unlike off-the-shift FPGA, each ASIC design requires a custom set of masks for silicon fabrication. The custom mask set allows circuitility and interconnections to be tailored to the requirements of each unique application-yielding high performance and density .However, the cost of the mask sets is rapidly increasing(nearly doubling with each successive technology node).as a result, mask costs are becoming as significant portion of the per-die cost in many cases.For example, consider the case wherere mask set costs $1,000,000.For applications where only 1,000 chip are required, each chip will over $1000, since the mask cost (plus many other expenses) must be amortized over the volume of chip sold. As the volume for this same ASIC rise, effective cost of each die decrease.Conversely, FPGA are standard products, where the mask charges for 5small number of design passes are amortized over a large number of customers and chips, so the mask cost per chip sold is minimal. As a result, for each technology node there is a volume threshold, below which it more cost-effective to buy an FPGA chip vs. a smaller ASIC chip. TAT is another primary economic driver, having a direct impact on time-to-market for many applications. The time required for ASIC layout and fabrication is typically in the range 2-5months-much longer than FPGA, which generally require 1-4weeks once a customers RTL is firm.These NRE and TAT issues are compounded by customers needs for multiple design passes. Since each ASIC design requires a unique mask set, if a custom discover logic error or need to add features after tape out, they must initiate another ASIC design pass, requiring additional NRE charges and silicon fabrication time. As silicon technologies progress and chip become more complex, design verification becomes increasingly difficult, and the chance for logic errors grows. In many cases, time to market pressures drive design teams to continue verification well into layout and sometimes beyond chip tape out. This increases the risk that logic updates will be required, and therefore cost per chip will increase.In summary, ASIC to date have offered higher performance in smaller chip sizes than FPGA. However, the NRE for current technology nodes has rendered them very expensive for applications that require low quantities of chips-particularly when multiple design passes are required.10.3 T he Hybrid ASIC/FPGA SolutionEnter the hybrid ASIC/FPGA. Like an ASIC, the initial mask set must be purchased. But with the incorporation of FPGA cores into the ASIC, it is now possible to use the programmable circuitry to enable a single physical chip designs to satisfy several different applications .This has the potential to eliminate multiple design and in some cases, avoid costly repines. In the case where a customer requires similar ASIC for a family of products, FPGA circuitry can be added to the base ASIC logic and configured as needed to satisfy the multiple applications. Similarly, logic updates required to correct bugs discovered late in the verification process, or to accommodate changing market needs, can be handled with appropriately placed FPGA cores.The question must be asked: why embed FPGA into an ASIC if a two chips solution could achieve the same results? The answer is both technical and 6economic. Technically, for a certain class of applications, the embedded solution offers greater performance with lower power dissipation. By embedding the FPGA into the ASIC, signals that must propagate from the ASIC through the FPGA, then back to the ASIC can avoid four chip boundary delays, two card crossings, and the associated power dissipation. By keeping the ASIC to FPGA interconnections on the die, valuable ASIC I/O pins are also conserved.Economically, the embedded solution can be the less expensive option. As we will discuss, the FPGA fabric does not require any unique semiconductor processing above and beyond the base ASIC (unlike embedded flash or embedded DRAM). The resulting increase in ASIC cost is associated with the area occupied by the embedded FPGA core. In addition, the cost of assembly, test and packaging of a secong chip are eliminated.In certain cases, it can be advantageous to include embedded FPGA on an ASIC if that FPGA eliminates the need for additional design passes. For example, at volumes of up to 250000 pieces, 50K gates of embedded FPGA are cost effectives. Similarly, 10K gates of embedded FPGA are cost effective versus a 2 pass ASIC design at volume of up to 1M. In general, if mask costs rise, volumes decrease, or more design passes are avoided, then the embedded FPGA approach becomes progressively more cost-effective compared to the ASIC approach. This is because at low volumes, the mask costs (and NRE) for additional design passes becomes a significant adder to per-chip cost, and this can outweigh the cost impact of the larger die area required by the embedded FPGA circuitry. This analysis leads us to conclude that technology and market trends have created a need for the development of the hybrid ASIC/FPGA product. Mask costs for advanced technologies are growing marking multiple design passes too costly for many applications. Fortunately, the technology advancements that have driven this trend have also opened up the potential to embed significant amounts of FPGA gates onto an ASIC die enough to handle some of the design updates that would otherwise require additional design passes.104 Hybrid Offering Overview The IBM/Xilinx hybrid will first be available in IBMs Cu-08 90nm ASIC offering, and will consist of three FPGA block sizes. Multiple blocks used can be mixed and matched.Physically, the FPGA cores are being ported to the same semiconductor 7process that the ASIC product uses. The issues encountered in doing this porting are similar to those of other 3rd party IP ports. One of the largest challenges is full chip physical verification. Common design rules and transistor design points are critical in blending of IP between suppliers. Minor difference in design rules can be accommodated, assuming that checking decks and other verification software are able to handle the mixture of design rules. Designing these tools for increased flexibility will likely be needed as more companies share IP.To ensure that the FPGA can be integrated with the rest of the ASIC power, agreement must be reached on metal stack options. In the case of the Cu-08 hybrid offering,5 level of metal were allocated to the FPGA blocks. This requires a re-layout of the FPGA cores, which were originally designed for a standard product with 9 levels of metal.As part of the re-layout, the power distribution of the FPGA blocks will be designed to integrate easily into the ASIC power distribution methodology. Care needs to be taken to ensure the power density required by the FPGA blocks are within the capability of the ASIC power supply routing. Due to extensive use of pass-gate structures, the FPGA blocks require standard 1.2V levels, while the bulk of the chip operates at lower levels.The embedded FPGA blocks consist of programmable logic blocks, configuration logic, test interface logic, and simplified IO buffers for use in driving and receiving on-chip nets. Multiple end user configuration mode are supported including FPGA, serial and parallel modes. Individual cores can be configured asynchronously, allowing for “on-the-fly” reconfiguration.To design the new hybrid chips, a modified design methodology is being developed as shown in Figure 10.1. This hybrid design flow incorporates two proven design methodologies, the IBM ASIC flow and the XILINX FPGA flow, including several third party vendor synthesis options. The ASIC methodology integrates the embedded FPGA as a hard core with appropriate ASIC label models. The FPGA flow, including timing closure of the FPGA configuration, is done using XILINX tools, the designer has the choice of using constraints or detailed timing from the Xilinx tool flow to close the ASIC timing at the FPGA cote interfaces. If an FPGA configuration is known prior to the design of the ASIC, actual timing information can be passed to the ASIC tools from the FPGA tools. If the logic content of the embedded FPGA is unknown, the ASIC design can be 8completed using timing assertions and the embedded FPGA design can be completed later. If the embedded FPGA design is being reconfigured after the ASIC is in manufacturing, the final timing constraints from the completed ASIC can be passed to the FPGA tools for the new FPGA design.The logic design of the chip must be partitioned prior to final synthesis. The logic destined for an FPGA block is processed indepen
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