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天津工程师范学院2009届本科生毕业设计附录9：整体实物图附录10：英文原文Memory Subsystem Organization and InterfacingIn this section we examine the construction and functions of the memory subsystem of a computer. We review the different types of physical memory and the internal organization of their chips. We discuss the construction of the memory subsystem, as well as multibyte word organizations and advanced memory organizations.1 Types of MemoryThere are two types of memory chips ; read only memory(ROM) and random access memory(RAM). Read Only Memory(ROM) chips are designed for applications in which data is only read. (This data can include program instructions.)These chips are programmed with data by an external programming unit before they are added to the computer system. Once this is done, the data usually does not change. A ROM chip always retains its data, even when power to the chip is turned off. As an example, an embedded controller for a microwave oven might continuously run one program that does not change. That program would be stored in a ROM.Random Access Memory (RAM), also called read/write memory, can be used to store data that change. This is the type of memory referred to as X MB of memory in ads for PCs. Unlike ROM,RAM chips lose their data once power is shut off. Many computer system, including personal computers, include both ROM and RAM.2 Internal Chip OrganizationThe internal organizations of ROM and RAM chips are similar. To illustrate the simplest organization, a linear organization, consider an 8x2 ROM chip. For simplicity, programming components are not shown。 This chip has three address inputs and two data outputs, and 16 bits of internal storage arranged as eight 2-bit locations.The three address bits are decoded to select one of the eight locations, but only if the chip enable is active. If CE=0, the decoder id disabled and no location is selected. The tri-state buffers for that locations cells are enabled, allowing data to pass to the output buffers. If both CE and OE set to 1, these buffers are enabled and the data is output from the chip; otherwise the outputs are tri-stated.As the number of the locations increases, the size of the address decoder needed in a linear organization becomes prohibitively large. To remedy this problem, the memory chip can be designed using multiple dimensions of decoding.In large memory chips, this savings can be significant. Consider a 4096x1 chip. The linear organization will require a 12 to 4096 decoder, the size of which is proportional to the number of outputs. (The size of an n to decoder id thus said to be O ().) If the chip is organized as a 64x64 two dimensional array instead, it will have two 6 to 64 decoders: one to select one of the 64 rows and the other to select one of the 64cells within the row. The size of the decoders is proportional to 2x64,or O (2x)=O (). For this chip, the two decoders together are about 3 percent of the size of the one large decoder.3 Memory Subsystem ConfigurationIt is very easy to set up a memory system that consists of a single chip. We simpley connect the address, data, and control signals from their system buses and the job is done. However, most memory systems require more than one chip. Following are some methods for combining memory chips to form a memory subsystem.Two or more chips can be combined to create memory with more bits per location. This is done by connecting the corresponding address and control signals of the chips, and connecting their data pins to different bits of the data bus. For example, two 8x2 chips can be combined to create an 8x4 memory, as shown in Figure 2-4. Both chips receive the same three address inputs from the bus, as well as the same chip enable and output enable signals. (For now it is only important to know that the signals are the same for both chips; we show the logic to generate these signals shortly.) The data pins of the first chip are connected to bits 3 and 2 of the data bus, and those of the other chip are connected to bits 1 and 0.Figure 4 An 8x4 memory subsystem constructed from two 8x2 ROM ChipsWhen the CPU reads data, it places the address on the address bus. Both chips read in address bits A2, A1, and Ao and perfonn their intemal decoding. If the CE and OE signals are activated, the chips output their data onto the fom bits of the data bus. Since the address and enable signals are the same for both chips, either both chips or neither chip is active at any given time. The computer never has only one of the two active. For this reason, they act just as a single 8x4 chip, at least as far as the CPU is concerned.Instead of creating wider words, chips can be combined to create more words. The same two 8 x2 chips could instead be configured as a 16x2 memory subsystem. This is illustrated in Figure 2-5(a). The upper chip is configured as memory locations 0 to 7 (0000 to OI II) and the lower chip as locations 8 to 15 (IOOO to l l Il). The upper chip always has A3 = 0 and the lower chip has A3=I . This difference is used to select one of the two chips. When A3 =0, the upper chip is enabled and the lower chip is disabled; when A3 = 1, the opposite occurs. (As shown in the figure9 other conditions must also occur or neither chip will be selected.) The output enables can be connected, since only the chip that is enabled will output data. Since both chips correspond to the same data bits, both are connected to DI and Do of the data bus.This configuration uses high-order interleaving. All memory locations within a chip are contiguous within system memory. However, this does not have to be the case. Consider the configuration shown in Figure 2-5(b), which uses low-order interleaving. The upper chip is enabled when A0=0 or by addresses XXX0, in this case 0,2,4,6,8,10,12, and 14. The lower chip is enabled when. A0=1, which is true for addresses 1, 3, 5, 7, 9, 11, 13 and 15. Both look the same to the CPU, but low-order interleaving can offer some speed advantages for pipelined memory access, and for CPUs that can read data from more than one memory location simultaneously.(a) high-order interleaving (b) low-order interleavingFigure 5 A 16x2 memory subsystem constructed from two 8x2 ROM ChipsThe next step in these designs is to develop the CE or OE input logic. Of these, the output enable is more straightforward. The CPU generally outputs a control signal called RD or RD, or something similar, which it sets active when it wants to read data from memory. This signal is sufficient to drive OE; the logic to drive CE ensures that only the correct chip output data.The chip enable signal makes use of the unused address bits. To illustrate, assume that the 8x4 memory of Figure 2-4 is used in a system with 6-bit address bus. Furthermore, assume this chip corresponds to locations 0 to 7(00 0000 to 00 0111). Address bits A2,A1,and A0 select a location within the memory chips; bits A5,A4,and A3 must be 000 for the chips to be active.4 Multibyte Data OrganizationMany data format use more than one 8-bit byte to represent a value, whether it is an integer, floating point number, or character string. Most CPUs assign addresses to 8-bit memory locations, so these values must be stored in more than one location. It is necessary for every CPU to define the order it expects for the data in these locations.These are two commonly used organizations for multibyte data: big endian and little endian. In big endain format, the most significant byte of a value is stored in location X, the following byte in location X+1, and so on. For example, the hexadecimal value 0102 0304H (H for hexadecimal) would be stored, starting in location 100H, as shown in Table 1(a).In little endian, the order is reversed. The least significant byte is stored in location X, the next byte in location X+1, and so on. The same value, in little endian format, is shown in Table 1(a).Memory AddressData(in hex)10010110210304030201（a）big endian formatsMemory AddressData(in hex)10010110210301020304(b) little endian formatsThe same organizations can be used for bits within a byte. In big endian organization, bit 0 is the rightmost bit of a byte: the left most bit is bit 7. In little endian organization, the leftmost bit is bit 0 and bit 7 is the rightmost bit. Table 1 Data organization in big and little endian formats.Which endian organization is used for bytes and words does not impact the performance of the CPU and computer system. As long as the CPU is designed to handle a specific format，never is better than the other. The main problem comes in transferring data between computers with different endian organizationsFor example，if a computer within little endian organizations transfer the value 0102 0304H to a computer with big endian organization without converting the data，the big endian computer will read the value as 0403 0201H There are programs which can convert data files from one format to the other, and some microprocessors have special instructions to perform the conversion0ne other issue of concern for multibyte words is alignmentModern microprocessors can read in more than one byte of data at a timeFor example，the Motorola 68040 microprocessor can read in four bytes simultaneously. However the four bytes must be in consecutive locations that have the same address expect for the two least significant bits. This CPU could read locations 100，101，102，and l03 simultaneously. but not locations l01，102，103，and l04This case would require two read operations，one for locations 100(not needed),101，102，and l03，and the other for 104，105(not needed),106(not needed),and l07(not needed).Alignment simply means storing mu1tibyte values in locations such that they begin at a 1ocation that also begins a multibyte read blockIn this example，this means beginning multibyte values at memory locations that have addresses evenly divisible by four, thus guaranteeing that a four-byte value can be accessed by a single operation.Some CPUs，particularly RISC CPUs，require all data to be a1ignedOther CPUs do not；they can usually align data internally. In general, nonaligned CPUs have more compact programs, because no locations are left unused by alignment. However, aligned CPUs can have better performance because they may need fewer memory read operations to fetch data and instructions.5 Beyond the BasicsThe memory subsystem describe in this chapter is sufficient for small, embedded computers. Personal computers and mainframes, however, require more complex hierarchical configurations. These computers include small, high-speed cache; the processor can access data in the cache more quickly than it can access the same data in physical memory. Many microprocessors include some cache memory right on the processor chip. A computer that includes cache memory must also have a cache controller to move data between the cache and physical memory.At the other extreme, modern computers include virtual memory. This mechanism uses a hard disk as a part of the computers memory, expending the memory space of the computer while minimizing cost, since a byte of hard disk costs less than a byte of Ram. As with the cache virtual memory needs a controller to move data between physical memory and the hard disk.附录11：英文译文存储器子系统的组成与接口本节我们将讨论计算机中存储器子系统的结构和功能，我们将会回顾不同类型的物理存储器及其芯片的内部组成，讨论存储器子系统的结构，以及多字节的组织和高级存储器的组成。1 存储器的种类存储器芯片有两种类型：只读存储器（ROM）和随机存取存储器（RAM）。只读存储器芯片是为数据（此数据可包括程序的指令）只读的应用而设计的。这些芯片在加入系统之前，就已经被某个外部编成器装好数据了。这个工作一旦完成，其数据通常不再改变。ROM芯片总是保存有数据，甚至在芯片断电以后。例如，一个微波炉的嵌入式控制器可以连续运行一个不变的数据。这就是我们在个人电脑广告上经常看到的X MB的内存所指的那种类型。不像ROM，RAM芯片一旦掉电，数据就会消失。许多计算机系统，包括个人电脑，都同时拥有ROM和RAM。2 芯片的内部组成ROM和RAM芯片的内部组成是相似的。为了说明一个简单的组成线性组成，我们来考虑一个8x2的ROM芯片。为了简化，编程器件没有画出来。这个芯片有三个地址输入端和两个数据输出端，以及16位的内部存储元件，它排成8个单元，每个单元2位。三个地址位经过译码，可以选择8个中的一个，但只有芯片的使能要有效才行。如果CE=0，译码器被禁止，则不选择任何单元。该单元上的三态缓冲器是有效的，允许数据输出到缓冲器中。如果CE=1且OE=1，则这些缓冲器有效，数据从芯片中输出；否则，输出是高阻态。随着单元数量的增加，线性组成中地址译码器的规模变得相当大。为了补救这一问题，存储器芯片可以设计成使用多维译码方式。在大型存储器芯片中，这种节省显得至关重要。考虑一个4096x1芯片 其线性组成将需要一个124096译码器,译码器大小与输出的数量成正比(假定一个n译码器的大小是O()。如果芯片排列成64x64的二维数组，它将有两个664译码器：一个用来选择64行中的一行，另一个用来在选定行中选择64个单元中的一个单元，该译码器的大小正比于2x64,或写成O(2x)O()。对于这个芯片，两个译码器总的大小约是那个大译码器大小的3.3 存储器子系统配置构造包含一个简单芯片的存储器系统是非常容易的，我们只需要简单地从系统总线上连接地址信号线、数据信号线和控制信号线就完成了。然而。大多数的存储器系统需要多个芯片，下面是通过存储器芯片组合来形成存储器子系统的一些方法。两个或多个芯片可以组合起来构造一个每单元有多位的存储器。这可以通过连接芯片相应的地址信号线和控制信号线，井将它们的数据引脚连到数据总线的不同位上来完成。例如，2个8X2芯片可以组合产生一个8X4存储器，如图4所示。两个芯片从总线上接收相同的三位地址输入，还有共同的芯片使能信号和输出使能信号(目前我们只要了解两个芯片使用的是同一信号就可以了，稍后我们将说明产生这些信号的逻辑)。第一个芯片的数据引脚连到数据总线的第3位和第2位，第二个芯片的数据引脚则连接在第1位和第0位。当CPU读取数据时，它将地址放在地址总线上。两个芯片读取地址位A2、A1、A0，并执行内部译码操作。如果CE和OE信号是有效的，两个芯片则输出数据到数据总线的四位上。因为两个芯片的地址和使能信号是相同的，因此在任一时刻两个芯片要么同时有效，要么同时无效。正因如此，它们的行为就像一个单一的8x4芯片，至少就CPU而言是这样的。除了构造更宽的字以外，芯片组合还可以构造出更多的字。两样的两个8x2芯片能够组成一个16x2存储子系统。如图5(a)所示。上面的芯片构成存储器的0到7(0000到0111)单元，下面的芯片作为单元8到15(1000到1111)。上面的芯片总是设置A3=0，而下面的芯片A3=1。通过这一区别来选择芯片，当A3=0时，上面的芯片有效，而下面的芯片无效；当A3=1时，情况刚好相反。(如图所示，另一种情况必定会发生，否则没有芯片被选中)输出使能端需要连接起来，因为只有芯片有效才可以输出数据。由于两个芯片对应相同的数据位，因此都可以连接到数据总线的D1和Do位上。这种配置使用的是高位交叉技术。同一芯片的所有存储单元在系统内存中是连续的。然而，不一定非得如此。考虑如图5(b)所示的情况，它用的是低位交叉技术。上面的芯片当A0=0或者当地址位为XXX0时有效，此时，地址为0、2、4、6、8、10、12和14；下面的芯片当A0=1时有效，地址为1、3、5、7、9、11、13和15。对CPU而言，两者是相同的。但低位交叉能为流水线存储器访问提供速度上的优势，对于能够同时从多于一个存储器单元中读取数据的CPU来说，低位交叉也存在速度上的优势。设计的下一步是指制定CE和OE的输入逻辑。输出使能更直接一些，CPU通常输出一个控制信号，称作RD或RD或别的什么，当它想要从主存读取数据时就将其设为有效，用此信号驱动OE就足够了，而驱动CE的逻辑务必确保只有正确的芯片方可输出数据。芯片使能信号可利用未使用的地址位。为了说明这一点，假设图2-4中的8x4存储器被用到一个6位地址总线的系统中，而且，进一步假设这个芯片对应的单元为0到7(00 000到00 0111)。则地址位 A2、Al和Ao可以用于选中存储芯片中的某个单元，而A5、A4和A3在芯片有效时一定要是000。 4 多字节数据组成 许多数据格式使用多个字节(一个字节8位)来表示一个数据，而不管此数值是整型数、浮点数还是字符串。由于大多数CPU给8位的存储器单元分配地址，因此这些值必须存储在多个单元中，每个CPU 必须定义数据在这些单元中的顺序。有两种常用的多字节数据排列顺序：高位优先和低位优先。依照高位优先格式，一个数值的最高字节存储在单元X中，次高字节存储在单元X+1中，依次类推。例如，十六进制数01020304H(H表示十六进制)从单元100h开始存储，则存储结果如表l(a)所示。依照低位优先格式，顺序正好相反。最低字节存储在单元X中，次字节存储在单元X+I中，依次类推。上例中的同一值，以低位优先格式存储，如表1b)所示。 同样的组织方式可用于一个字节中的不同位上。在高位优先结构中，位0代表字节中最右边的位
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