用VHDL语言实现拔河电路功能

实验实验四四 基于基于 Quartus 的硬件描述的硬件描述语语言的拔河言的拔河电电路路设计设计 1 实验内容 基于前期原理图电子拔河电路 甲 乙双方分别按动己方按键 按键的次 数分别在双方的两个数码管上显示 当喊停止的时候 数码管数字较大的一方 获胜 连续比赛多局以定胜负 二 实验工具 1 DE0 开发板一个 2 Quartus 2 16 软件 3 VHDL 语言 三 实验准备 1 学习 VHDL 语言 了解基本语法规则和基本语句 2 明确所实现的电路所需要的器件 并且明确用 VHDL 实现该器件的基本 逻辑关系和基本语句 实验所需要的器件为百进制计数器 比较器和译码器 3 明确 VHDL 实体的定义 明确实体的输入输出 并且明确实现该实体的 基本语法和基本步骤 4 必须明确实体层次的概念 在低层次实体中 必须明确各个输入输出之 间的联系 以结构的方式构建高层次实体 四 实验程序 LIBRARY IEEE USE IEEE STD LOGIC 1164 ALL USE IEEE STD LOGIC UNSIGNED ALL ENTITY test4 IS PORT KEY1 KEY2 KEY3 CLOCK IN IN STD LOGIC HEX0 HEX1 HEX2 HEX3 HEX4 HEX5 OUT STD LOGIC VECTOR 6 DOWNTO 0 com OUT STD LOGIC VECTOR 2 DOWNTO 0 END test4 以下为百进制计数器设计实体 LIBRARY IEEE USE IEEE STD LOGIC 1164 ALL USE IEEE STD LOGIC UNSIGNED ALL ENTITY COUNT 100 IS PORT clk clr IN STD LOGIC date in IN STD LOGIC VECTOR 3 DOWNTO 0 lo out hi out OUT STD LOGIC VECTOR 3 DOWNTO 0 END COUNT 100 ARCHITECTURE fwm OF COUNT 100 IS SIGNAL hi tmp lo tmp STD LOGIC VECTOR 3 DOWNTO 0 SIGNAL load cnt STD LOGIC VECTOR 1 DOWNTO 0 BEGIN load cnt load 数据写入与置数位控制的并置 PROCESS clk clr hi lo 1 时为高位置数 hi lo 0 时 为低位置数 VARIABLE q tmp STD LOGIC VECTOR 3 DOWNTO 0 BEGIN IF clr 0 THEN hi tmp 0000 lo tmp 1010 THEN lo tmp 1001 ELSE lo tmp 1010 THEN hi tmp 1001 ELSE hi tmp date in END IF ELSIF load cnt 01 OR load cnt 00 THEN IF lo tmp 1001 THEN 低位等于 9 IF hi tmp 1001 THEN 如果高 位不等于 9 lo tmp 0000 hi tmp hi tmp 1 那么高位加 1 ELSE hi tmp 0000 lo tmp 0000 ELSE lo tmp 1001 除 此之外 低位 9 保持不变 END IF ELSE lo tmp lo tmp 1 如果低位 不是 9 那么低位加 1 END IF END IF END IF END PROCESS lo out lo tmp 低位信号赋值给低位输出端 hi out hi tmp 高位信号赋值给高位输出端 END fwm 以下为计算胜的局数的 10 进制计数器 LIBRARY IEEE USE IEEE STD LOGIC 1164 ALL USE IEEE STD LOGIC UNSIGNED ALL ENTITY COUNT 10 IS PORT clk clr IN STD LOGIC COUNT 10 OUT OUT STD LOGIC VECTOR 3 DOWNTO 0 END COUNT 10 ARCHITECTURE fwm OF COUNT 10 IS SIGNAL COUNT 10 TMP STD LOGIC VECTOR 3 DOWNTO 0 BEGIN PROCESS clk clr BEGIN IF clr 0 THEN COUNT 10 TMP 0000 异步清零 ELSIF clk EVENT AND clk 1 THEN COUNT 10 TMP COUNT 10 TMP 1 IF COUNT 10 TMP 1001 THEN 如果加到十 归零 COUNT 10 TMP 0000 END IF END IF END PROCESS COUNT 10 OUT COUNT 10 TMP END fwm 以下为分频器实体电路 LIBRARY IEEE USE IEEE STD LOGIC 1164 ALL USE IEEE STD LOGIC UNSIGNED ALL ENTITY FP IS PORT clk in IN STD LOGIC clk out OUT STD LOGIC END FP ARCHITECTURE fwm OF FP IS CONSTANT M INTEGER 25000000 50M 分频到 1HZ SIGNAL FP TMP STD LOGIC BEGIN PROCESS clk in VARIABLE COUNT INTEGER 0 BEGIN IF clk in EVENT AND clk in 1 THEN COUNT COUNT 1 计数器 1 IF COUNT M THEN FP TMP 0 ELSIF COUNT M 5 THEN FP TMP 1 ELSE COUNT 0 END IF END IF END PROCESS clk out dis out dis out dis out dis out dis out dis out dis out dis out dis out dis outdis out 1111111 不显示 END CASE END PROCESS END fwm 以下为 8 位无符号整数比较器设计实体 LIBRARY IEEE USE IEEE STD LOGIC 1164 ALL USE IEEE STD LOGIC UNSIGNED ALL ENTITY COMPARE IS PORT a b IN STD LOGIC VECTOR 7 DOWNTO 0 eq lt gt OUT STD LOGIC END COMPARE ARCHITECTURE fwm OF COMPARE IS BEGIN PROCESS a b BEGIN eq 0 lt 0 gt 0 IF a b THEN eq 1 END IF IF a b THEN ltb THEN gtCLOCK IN clk out CLK OUT U1 COUNT 100 PORT MAP clk KEY1 CLR CLK OUT lo out tem lo 1 hi out tem hi 1 U2 COUNT 100 PORT MAP clk KEY2 CLR CLK OUT lo out tem lo 2 hi out tem hi 2 U3 DIS PORT MAP date in tem lo 1 dis out HEX0 U4 DIS PORT MAP date in tem hi 1 dis out HEX1 U5 DIS PORT MAP date in tem lo 2 dis out HEX2 U6 DIS PORT MAP date in tem hi 2 dis out HEX3 U7 COMPARE PORT MAP a 0 tem lo 1 0 a 1 tem lo 1 1 a 2 tem lo 1 2 a 3 tem l o 1 3 a 4 tem hi 1 0 a 5 tem hi 1 1 a 6 tem hi 1 2 a 7 tem hi 1 3 b 0 tem lo 2 0 b 1 tem lo 2 1 b 2 tem lo 2 2 b 3 tem l o 2 3 b 4 tem hi 2 0 b 5 tem hi 2 1 b 6 tem hi 2 2 b 7 tem hi 2 3 lt lt mid eq eq mid gt gt mid U8 COMPARE PORT MAP a 0 tem lo 1 0 a 1 tem lo 1 1 a 2 tem lo 1 2 a 3 tem l o 1 3 a 4 tem hi 1 0 a 5 tem hi 1 1 a 6 tem hi 1 2 a 7 tem hi 1 3 b 0 tem lo 2 0 b 1 tem lo 2 1 b 2 tem lo 2 2 b 3 tem l o 2 3 b 4 tem hi 2 0 b 5 tem hi 2 1 b 6 tem hi 2 2 b 7 tem hi 2 3 lt COM 0 eq COM 1 gt COM 2 U9 COUNT 10 PORT MAP clk lt mid clr KEY3 COUNT 10 OUT COUNT 10 DATE OUT1 U10 COUNT 10 PORT MA