文献翻译——AT89S52

第1页外文文献资料AT89S52TheAT89S52isalow-power,high-performanceCMOS8-bitmicrocontrollerwith4KbytesofIn-SystemProgrammableFlashmemory.ThedeviceismanufacturedusingAtmelshigh-densitynonvolatilememorytechnologyandiscompatiblewiththeindustry-standard80C51instructionsetandpinout.Theon-chipFlashallowstheprogrammemorytobereprogrammedin-systemorbyaconventionalnonvolatilememoryprogrammer.Bycombiningaversatile8-bitCPUwithIn-SystemProgrammableFlashonamonolithicchip,theAtmelAT89S52isapowerfulmicrocontrollerwhichprovidesahighly-flexibleandcost-effectivesolutiontomanyembeddedcontrolapplications.TheAT89S52providesthefollowingstandardfeatures:4KbytesofFlash,128bytesofRAM,32I/Olines,Watchdogtimer,twodatapointers,two16-bittimer/counters,afive-vectortwo-levelinterruptarchitecture,afullduplexserialport,on-chiposcillator,andclockcircuitry.Inaddition,theAT89S52isdesignedwithstaticlogicforoperationdowntozerofrequencyandsupportstwosoftwareselectablepowersavingmodes.TheIdleModestopstheCPUwhileallowingtheRAM,timer/counters,serialport,andinterruptsystemtocontinuefunctioning.ThePower-downmodesavestheRAMcontentsbutfreezestheoscillator,disablingallotherchipfunctionsuntilthenextexternalinterruptorhardwarereset.1.PinDescription1.1.Port0：Port0isan8-bitopendrainbidirectionalI/Oport.Asanoutputport,eachpincansinkeightTTLinputs.When1sarewrittentoport0pins,thepinscanbeusedashigh-impedanceinputs.Port0canalsobeconfiguredtobethemultiplexedlow-orderaddress/databusduringaccessestoexternalprogramanddatamemory.Inthismode,P0hasinternalpull-ups.Port0alsoreceivesthecodebytesduringFlashprogrammingand第2页outputsthecodebytesdur-ingprogramverification.Externalpull-upsarerequiredduringprogramverification.1.2.Port1：Port1isan8-bitbidirectionalI/Oportwithinternalpull-ups.ThePort1outputbufferscansink/sourcefourTTLinputs.When1sarewrittentoPort1pins,theyarepulledhighbytheinter-nalpull-upsandcanbeusedasinputs.Asinputs,Port1pinsthatareexternallybeingpulledlowwillsourcecurrent(IIL)becauseoftheinternalpull-ups.Inaddition,P1.0andP1.1canbeconfiguredtobethetimer/counter2externalcountinput(P1.0/T2)andthetimer/counter2triggerinput(P1.1/T2EX),respectively,asshowninthefollow-ingtable.Port1alsoreceivesthelow-orderaddressbytesduringFlashprogrammingandverification.Table1PortPinAlternateFunctionsP1.0T2(externalcountinputtoTimer/Counter2),clock-outP1.1T2EX(Timer/Counter2capture/reloadtriggeranddirectioncontrol)P1.5MOSI(usedforIn-SystemProgramming)P1.6MISO(usedforIn-SystemProgramming)P1.7SCK(usedforIn-SystemProgramming)1.3.Port2：Port2isan8-bitbidirectionalI/Oportwithinternalpull-ups.ThePort2outputbufferscansink/sourcefourTTLinputs.When1sarewrittentoPort2pins,theyarepulledhighbytheinter-nalpull-upsandcanbeusedasinputs.Asinputs,Port2pinsthatareexternallybeingpulledlowwillsourcecurrent(IIL)becauseoftheinternalpull-ups.Port2emitsthehigh-orderaddressbyteduringfetchesfromexternalprogrammemoryanddur-ingaccessestoexternaldatamemorythatuse16-bitaddresses(MOVXDPTR).Inthisapplication,Port2usesstronginternalpull-upswhenemitting1s.Duringaccessestoexternaldatamemorythatuse8-bitaddresses第3页(MOVXRI),Port2emitsthecontentsoftheP2SpecialFunctionRegister.Port2alsoreceivesthehigh-orderaddressbitsandsomecontrolsignalsduringFlashprogram-mingandverification.1.4.Port3：Port3isan8-bitbidirectionalI/Oportwithinternalpull-ups.ThePort3outputbufferscansink/sourcefourTTLinputs.When1sarewrittentoPort3pins,theyarepulledhighbytheinter-nalpull-upsandcanbeusedasinputs.Asinputs,Port3pinsthatareexternallybeingpulledlowwillsourcecurrent(IIL)becauseofthepull-ups.Port3receivessomecontrolsignalsforFlashprogrammingandverification.Port3alsoservesthefunctionsofvariousspecialfeaturesoftheAT89S52,asshowninthefol-lowingtable.Table2PortPinAlternateFunctionsP3.0RXD(serialinputport)P3.1TXD(serialoutputport)P3.2(externalinterrupt0)INT0P3.3(externalinterrupt1)1P3.4T0(timer0externalinput)P3.5T1(timer1externalinput)P3.6(externaldatamemorywritestrobe)WRP3.7(externaldatamemoryreadstrobe)D1.5.RST：Resetinput.Ahighonthispinfortwomachinecycleswhiletheoscillatorisrunningresetsthedevice.Thispindriveshighfor98oscillatorperiodsaftertheWatchdogtimesout.TheDISRTObitinSFRAUXR(address8EH)canbeusedtodisablethisfeature.InthedefaultstateofbitDISRTO,theRESETHIGHoutfeatureisenabled.1.6.ALE/：AddressLatchEnable(ALE)isanoutputpulseforPROGlatchingthelowbyteoftheaddressduringaccessestoexternalmemory.This第4页pinisalsotheprogrampulseinput()duringFlashprogramming.InPROGnormaloperation,ALEisemittedataconstantrateof1/6theoscillatorfrequencyandmaybeusedforexternaltimingorclockingpurposes.Note,however,thatoneALEpulseisskippeddur-ingeachaccesstoexternaldatamemory.Ifdesired,ALEoperationcanbedisabledbysettingbit0ofSFRlocation8EH.Withthebitset,ALEisactiveonlyduringaMOVXorMOVCinstruction.Otherwise,thepinisweaklypulledhigh.SettingtheALE-disablebithasnoeffectifthemicrocontrollerisinexternalexecutionmode.1.7.：ProgramStoreEnable()isthereadstrobetoPSENPSENexternalprogrammemory.WhentheAT89S52isexecutingcodefromexternalprogrammemory,isactivatedtwiceeachmachinecycle,exceptthattwoactivationsareskippedduringeachaccesstoexter-naldatamemory.1.8./VPP：ExternalAccessEnable.mustbestrappedtoGNDinEAEAordertoenablethedevicetofetchcodefromexternalprogrammemorylocationsstartingat0000HuptoFFFFH.Note,however,thatiflockbit1isprogrammed,willbeinternallylatchedonreset.shouldbestrappedtoVCCforinternalprogramexecutions.Thispinalsoreceivesthe12-voltprogrammingenablevoltage(VPP)duringFlashprogramming.1.9.XTAL1：Inputtotheinvertingoscillatoramplifierandinputtotheinternalclockoperatingcircuit.1.10.XTAL2：Outputfromtheinvertingoscillatoramplifier.2.MemoryOrganizationMCS-51deviceshaveaseparateaddressspaceforProgramandDataMemory.Upto64KbyteseachofexternalProgramandDataMemorycanbeaddressed.2.1.ProgramMemoryIfthepinisconnectedtoGND,allprogramfetchesaredirectedtoEAexternalmemory.OntheAT89S52,ifisconnectedtoVCC,programfetchesEAtoaddresses0000Hthrough1FFFHaredirectedtointernalmemoryandfetchestoaddresses2000HthroughFFFFHaretoexternalmemory.第5页2.2.DataMemoryTheAT89S52implements256bytesofon-chipRAM.Theupper128bytesoccupyaparalleladdressspacetotheSpecialFunctionRegisters.Thismeansthattheupper128byteshavethesameaddressesastheSFRspacebutarephysicallyseparatefromSFRspace.Whenaninstructionaccessesaninternallocationaboveaddress7FH,theaddressmodeusedintheinstructionspecifieswhethertheCPUaccessestheupper128bytesofRAMortheSFRspace.InstructionswhichusedirectaddressingaccesstheSFRspace.Forexample,thefollowingdirectaddressinginstructionaccessestheSFRatlocation0A0H(whichisP2).3.WatchdogTimer(One-timeEnabledwithReset-out)TheWDTisintendedasarecoverymethodinsituationswheretheCPUmaybesubjectedtosoftwareupsets.TheWDTconsistsofa14-bitcounterandtheWatchdogTimerReset(WDTRST)SFR.TheWDTisdefaultedtodisablefromexitingreset.ToenabletheWDT,ausermustwrite01EHand0E1HinsequencetotheWDTRSTregister(SFRlocation0A6H).WhentheWDTisenabled,itwillincrementeverymachinecyclewhiletheoscillatorisrunning.TheWDTtimeoutperiodisdependentontheexternalclockfrequency.ThereisnowaytodisabletheWDTexceptthroughreset(eitherhardwareresetorWDToverflowreset).WhenWDToverflows,itwilldriveanoutputRESETHIGHpulseattheRSTpin.3.1.UsingtheWDTToenabletheWDT,ausermustwrite01EHand0E1HinsequencetotheWDTRSTregister(SFRlocation0A6H).WhentheWDTisenabled,theuserneedstoserviceitbywriting01EHand0E1HtoWDTRSTtoavoidaWDToverflow.The14-bitcounteroverflowswhenitreaches16383(3FFFH),andthiswillresetthedevice.WhentheWDTisenabled,itwillincrementeverymachinecyclewhiletheoscillatorisrunning.ThismeanstheusermustresettheWDTatleastevery16383machinecycles.ToresettheWDTtheusermustwrite01EHand0E1HtoWDTRST.WDTRSTisawrite-onlyregister.TheWDTcountercannot第6页bereadorwritten.WhenWDToverflows,itwillgenerateanoutputRESETpulseattheRSTpin.TheRESETpulsedurationis98xTOSC,whereTOSC=1/FOSC.TomakethebestuseoftheWDT,itshouldbeservicedinthosesectionsofcodethatwillperiodicallybeexecutedwithinthetimerequiredtopreventaWDTreset.3.2.WDTDURINGPower-downandIdleInPower-downmodetheoscillatorstops,whichmeanstheWDTalsostops.WhileinPower-downmode,theuserdoesnotneedtoservicetheWDT.TherearetwomethodsofexitingPower-downmode:byahardwareresetorviaalevel-activatedexternalinterrupt,whichisenabledpriortoenteringPower-downmode.WhenPower-downisexitedwithhardwarereset,servicingtheWDTshouldoccurasitnormallydoeswhenevertheAT89S51isreset.ExitingPower-downwithaninterruptissignificantlydifferent.Theinterruptisheldlowlongenoughfortheoscillatortostabilize.Whentheinterruptisbroughthigh,theinterruptisserviced.TopreventtheWDTfromresettingthedevicewhiletheinterruptpinisheldlow,theWDTisnotstarteduntiltheinterruptispulledhigh.ItissuggestedthattheWDTberesetduringtheinterruptservicefortheinterruptusedtoexitPower-downmode.ToensurethattheWDTdoesnotoverflowwithinafewstatesofexitingPower-down,itisbesttoresettheWDTjustbeforeenteringPower-downmode.BeforegoingintotheIDLEmode,theWDIDLEbitinSFRAUXRisusedtodeterminewhethertheWDTcontinuestocountifenabled.TheWDTkeepscountingduringIDLE(WDIDLEbit=0)asthedefaultstate.TopreventtheWDTfromresettingtheAT89S51whileinIDLEmode,theusershouldalwayssetupatimerthatwillperiodicallyexitIDLE,servicetheWDT,andreenterIDLEmode.WithWDIDLEbitenabled,theWDTwillstoptocountinIDLEmodeandresumesthecountuponexitfromIDLE.4.Timer0and1Timer0andTimer1intheAT89S52operatethesamewayasTimer0and第7页Timer1intheAT89C51andAT89C52.Forfurtherinformationonthetimersoperation,pleaseclickonthedocumentlinkbelow:/dyn/resources/prod_documents/DOC4316.PDF5.Timer2Timer2isa16-bitTimer/Counterthatcanoperateaseitheratimeroraneventcounter.ThetypeofoperationisselectedbybitC/intheSFRT2T2CON.Timer2hasthreeoperatingmodes:capture,auto-reload(upordowncounting),andbaudrategenerator.ThemodesareselectedbybitsinT2CON,asshowninTable6-1.Timer2consistsoftwo8-bitregisters,TH2andTL2.IntheTimerfunction,theTL2registerisincrementedeverymachinecycle.Sinceamachinecycleconsistsof12oscillatorperiods,thecountrateis1/12oftheoscil-latorfrequency.Table3.Timer2OperatingModesRCLK+TCLKCP/RLTR2MODE00116-bitAuto-reload01116-bitCapture1X1BaudRateGeneratorXX0(Off)IntheCounterfunction,theregisterisincrementedinresponsetoa1-to-0transitionatitscorre-spondingexternalinputpin,T2.Inthisfunction,theexternalinputissampledduringS5P2ofeverymachinecycle.Whenthesamplesshowahighinonecycleandalowinthenextcycle,thecountisincremented.ThenewcountvalueappearsintheregisterduringS3P1ofthecyclefollowingtheoneinwhichthetransitionwasdetected.Sincetwomachinecycles(24oscillatorperiods)arerequiredtorecognizea1-to-0transition,themaximumcountrateis1/24oftheoscillatorfrequency.Toensurethatagivenlevelissampledatleastoncebeforeitchanges,thelevelshouldbeheldforatleastonefullmachinecycle.第8页5.1.CaptureModeInthecapturemode,twooptionsareselectedbybitEXEN2inT2CON.IfEXEN2=0,Timer2isa16-bittimerorcounterwhichuponoverflowsetsbitTF2inT2CON.Thisbitcanthenbeusedtogenerateaninterrupt.IfEXEN2=1,Timer2performsthesameoperation,buta1-to-0transi-tionatexternalinputT2EXalsocausesthecurrentvalueinTH2andTL2tobecapturedintoRCAP2HandRCAP2L,respectively.Inaddition,thetransitionatT2EXcausesbitEXF2inT2CONtobeset.TheEXF2bit,likeTF2,cangenerateaninterrupt.5.2.Auto-reload(UporDownCounter)Timer2canbeprogrammedtocountupordownwhenconfiguredinits16-bitauto-reloadmode.ThisfeatureisinvokedbytheDCEN(DownCounterEnable)bitlocatedintheSFRT2MOD.Uponreset,theDCENbitissetto0sothattimer2willdefaulttocountup.WhenDCENisset,Timer2cancountupordown,dependingonthevalueoftheT2EXpin.Timer2automaticallycountingupwhenDCEN=0.Inthismode,twooptionsareselectedbybitEXEN2inT2CON.IfEXEN2=0,Timer2countsupto0FFFFHandthensetstheTF2bituponoverflow.Theoverflowalsocausesthetimerregisterstobereloadedwiththe16-bitvalueinRCAP2HandRCAP2L.ThevaluesinTimerinCaptureModeRCAP2HandRCAP2Larepresetbysoftware.IfEXEN2=1,a16-bitreloadcanbetriggeredeitherbyanoverfloworbya1-to-0transitionatexternalinputT2EX.ThistransitionalsosetstheEXF2bit.BoththeTF2andEXF2bitscangenerateaninterruptifenabled.SettingtheDCENbitenablesTimer2tocountupordown,asshowninFigure10-2.Inthismode,theT2EXpincontrolsthedirectionofthecount.Alogic1atT2EXmakesTimer2countup.Thetimerwilloverflowat0FFFFHandsettheTF2bit.Thisoverflowalsocausesthe16-bitvalueinRCAP2HandRCAP2Ltobereloadedintothetimerregisters,TH2andTL2,respectively.Alogic0atT2EXmakesTimer2countdown.ThetimerunderflowswhenTH2andTL2equalthevaluesstoredinRCAP2HandRCAP2L.TheunderflowsetstheTF2bitandcauses0FFFFHtobereloadedintothetimerregisters.TheEXF2bittoggleswheneverTimer第9页2overflowsorunderflowsandcanbeusedasa17thbitofresolution.Inthisoperatingmode,EXF2doesnotflaganinterrupt.6.InterruptsTheAT89S52hasatotalofsixinterruptvectors:twoexternalinterrupts(and),threetimerinterrupts(Timers0,1,and2),andtheserialINT0I1portinterrupt.EachoftheseinterruptsourcescanbeindividuallyenabledordisabledbysettingorclearingabitinSpecialFunctionRegisterIE.IEalsocontainsaglobaldisablebit,EA,whichdisablesallinterruptsatonce.NotethatbitpositionIE.6isunimplemented.Usersoftwareshouldnotwritea1tothisbitposition,sinceitmaybeusedinfutureAT89products.Timer2interruptisgeneratedbythelogicalORofbitsTF2andEXF2inregisterT2CON.Nei-theroftheseflagsisclearedbyhardwarewhentheserviceroutineisvectoredto.Infact,theserviceroutinemayhavetodeterminewhetheritwasTF2orEXF2thatgeneratedtheinterrupt,andthatbitwillhavetobeclearedinsoftware.TheTimer0andTimer1flags,TF0andTF1,aresetatS5P2ofthecycleinwhichthetimersoverflow.Thevaluesarethenpolledbythecircuitryinthenextcycle.However,theTimer2flag,TF2,issetatS2P2andispolledinthesamecycleinwhichthetimeroverflows.7.OscillatorCharacteristicsXTAL1andXTAL2aretheinputandoutput,respectively,ofaninvertingamplifierthatcanbeconfiguredforuseasanon-chiposcillator.Eitheraquartzcrystalorceramicresonatormaybeused.Todrivethedevicefromanexternalclocksource,XTAL2shouldbeleftunconnectedwhileXTAL1isdriven,.Therearenorequirementsonthedutycycleoftheexternalclocksignal,sincetheinputtotheinternalclock-ingcircuitryisthroughadivide-by-twoflip-flop,butminimumandmaximumvoltagehighandlowtimespecificationsmustbeobserved.第10页8.IdleModeInidlemode,theCPUputsitselftosleepwhilealltheon-chipperipheralsremainactive.Themodeisinvokedbysoftware.Thecontentoftheon-chipRAMandallthespecialfunctionsregis-tersremainunchangedduringthismode.Theidlemodecanbeterminatedbyanyenabledinterruptorbyahardwarereset.Notethatwhenidlemodeisterminatedbyahardwarereset,thedevicenormallyresumespro-gramexecutionfromwhereitleftoff,uptotwomachinecyclesbeforetheinternalresetalgorithmtakescontrol.On-chiphardwareinhibitsaccesstointernalRAMinthisevent,butaccesstotheportpinsisnotinhibited.Toeliminatethepossibilityofanunexpectedwritetoaportpinwhenidlemodeisterminatedbyareset,theinstructionfollowingtheonethatinvokesidlemodeshouldnotwritetoaportpinortoexternalmemory.9.Power-downModeInthePower-downmode,theoscillatorisstopped,andtheinstructionthatinvokesPower-downisthelastinstructionexecuted.Theon-chipRAMandSpecialFunctionRegistersretaintheirvaluesuntilthePower-downmodeisterminated.ExitfromPower-downmodecanbeinitiatedeitherbyahardwareresetorbyanenabledexternalinterrupt.ResetredefinestheSFRsbutdoesnotchangetheon-chipRAM.TheresetshouldnotbeactivatedbeforeVCCisrestoredtoitsnormaloperatinglevelandmustbeheldactivelongenoughtoallowtheoscillatortorestartandstabilize.第11页中文翻译稿AT89S52该AT89S51是一个低功耗，高性能CMOS8位微控制器,可在4K字节的系统内编程的闪存存储器。该设备是采用Atmel的高密度、非易失性存储器技术和符合工业标准的80C51指令集和引脚。芯片上的Flash程序存储器在系统中可重新编程或常规非易失性内存编程。通过结合通用8位中央处理器的系统内可编程闪存的单芯片，AT89S51是一个功能强大的微控制器提供了高度灵活的和具有成本效益的解决办法，可在许多嵌入式控制中应用。在AT89S51提供以下标准功能：4K字节的Flash闪存，128字节的RAM，32个I/O线，看门狗定时器，两个数据指针，两个16位定时器/计数器，5向量两级中断结构，全双工串行端口，片上振荡器和时钟电路。此外，AT89S51设计了可降至零频率的静态逻辑操作和支持两种软件可选的节电工作模式。在空闲模式下停止CPU的工作，但允许RAM、定时器/计数器、串行接口和中断系统继续运行。掉电模式保存RAM中的内容，停止振荡器工作并禁止其它所有部件工作，直到下一个外部中断或硬件复位。1.引脚功能1.1.P0口：P0口是一个8位漏极开路的双向I/O口。作为输出口，每位能驱动8个TTL逻辑电平。对P0端口写“1”时，引脚用作高阻抗输入。当访问外部程序和数据存储器时，P0口也被作为低8位地址/数据复用。在这种模式下，P0具有内部上拉电阻。在flash编程时，P0口也用来接收指令字节；在程序校验时，输出指令字节。程序校验时，需要外部上拉电阻。1.2.P1口：P1口是一个具有内部上拉电阻的8位双向I/O口，p1输出缓冲器能驱动4个TTL逻辑电平。对P1端口写“1”时，内部上拉电阻把端口拉高，此时可以作为输入口使用。作为输入使用时，被外部拉低的引脚由于内部电阻的原因，将输出电流（IIL）。此外，P1.0和P1.2分别作定时器/计数器2的外部计数输入（P1.0/T2）和时器/计数器2的触发输入（P1.1/T2EX），具体如表1所示。在flash编程和校验时，P1口接收低8位地址字节。第12页表1引脚号第二功能P1.0T2（定时器/计数器T2的外部计数输入），时钟输出P1.1T2EX（定时器/计数器T2的捕捉/重载触发信号和方向控制）P1.5MOSI（在系统编程用）P1.6MISO（在系统编程用）P1.7SCK（在系统编程用）1.3.P2口：P2口是一个具有内部上拉电阻的8位双向I/O口，P2输出缓冲器能驱动4个TTL逻辑电平。对P2端口写“1”时，内部上拉电阻把端口拉高，此时可以作为输入口使用。作为输入使用时，被外部拉低的引脚由于内部电阻的原因，将输出电流（IIL）。在访问外部程序存储器或用16位地址读取外部数据存储器（例如执行MOVXDPTR）时，P2口送出高八位地址。在这种应用中，P2口使用很强的内部上拉发送1。在使用8位地址（如MOVXRI）访问外部数据存储器时，P2口输出P2锁存器的内容。在flash编程和校验时，P2口也接收高8位地址字节和一些控制信号。1.4.P3口：P3口是一个有内部上拉电阻的8位双向I/O口，p2输出缓冲器能驱动4个TTL逻辑电平。对P3端口写“1”时，内部上拉电阻把端口拉高，此时可以作为输入口使用。作为输入使用时，被外部拉低的引脚由于内部电阻的原因，将输出电流（IIL）。P3口亦作为AT89S52特殊功能（第二功能）使用，如表2所示。在flash编程和校验时，P3口也接收一些控制信号。表2引脚号第二功能P3.0RXD（串行输入）P3.1TXD（串行输出）P3.2(外部中断0)INT0P3.3(外部中断1)1P3.4T0（定时器0外部输入）P3.5T1定时器1外部输入）第13页P3.6(外部数据存储器写选通)WRP3.7(外部数据存储器写选通)D1.5.RST：复位输入。晶振工作时，RST脚持续2个机器周期高电平将使单片机复位。看门狗计时完成后，RST脚输出96个晶振周期的高电平。特殊寄存器AUXR(地址8EH)上的DISRTO位可以使此功能无效。DISRTO默认状态下，复位高电平有效。1.6.ALE/：地址锁存控制信号（ALE）是访问外部程序存储器时，锁存低8位PROG地址的输出脉冲。在flash编程时，此引脚()也用作编程输入脉冲。在一般情况PROG下，ALE以晶振六分之一的固定频率输出脉冲，可用来作为外部定时器或时钟使用。然而，特别强调，在每次访问外部数据存储器时，ALE脉冲将会跳过。如果需要，通过将地址为8EH的SFR的第0位置“1”，ALE操作将无效。这一位置“1”，ALE仅在执行MOVX或MOVC指令时有效。否则，ALE将被微弱拉高。这个ALE使能标志位（地址为8EH的SFR的第0位）的设置对微控制器处于外部执行模式下无效。1.7.：外部程序存储器选通信号()是外部程序存储器选通信号。当PSENPSENAT89S52从外部程序存储器执行外部代码时，在每个机器周期被激活两次，而在访问外部数据存储器时，将不被激活。1.8./VPP：访问外部程序存储器控制信号。为使能从0000H到FFFFH的外部程序A存储器读取指令，必须接GND。为了执行内部程序指令，应该接VCC。在flash编EEA程期间，也接收12伏VPP电压。1.9.XTAL1：振荡器反相放大器和内部时钟发生电路的输入端。1.10.XTAL2：振荡器反相放大器的输出端。2.存储器结构MCS-51器件有单独的程序存储器和数据存储器。外部程序存储器和数据存储器都可以64K寻址。2.1.程序存储器:如果引脚接地，程序读取只从外部存储器开始。对于EA89S52，如果接VCC，程序读写先从内部存储器（地址为0000H1FFFH）开始，接着EA从外部寻址，寻址地址为：2000HFFFFH。2.2.数据存储器:AT89S52有256字节片内数据存储器。高128字节与特殊功能寄存器重叠。也就是说高128字节与特殊功能寄存器有相同的地址，而物理上是分开的。当一条指令访问高于7FH的地址时，寻址方式决定CPU访问高128字节RAM还是特殊功能寄存器空间。直接寻址方式访问特殊功能寄存器（SFR）。例如，下面的直接寻址指第14页令访问0A0H（P2口）存储单元3.看门狗定时器（WDT）看门狗定时器（WDT）是为了解决CPU程序运行时可能进入混乱或死循环而设置，它由一个14bit计数器和看门狗定时器复位SFR（WDTRST）构成。外部复位时，看门狗定时器（WDT）默认为关闭状态，要打开WDT，用户必须按顺序将01EH和0E1H写到WDTRST寄存器（SFR地址为0A6H），当启动了WDT，它会随警惕振荡器在每个机器周期计数，除了硬件复位或WDT溢出复位外没有其它方法关闭WDT，当WDT溢出，将使RST引脚输出高电平的复位脉冲。3.1.使用看门狗定时器（WDT）用户在打开WDT时，需要按次