基于VerilogHDL语言的EDA多功能电子钟设计源代码.doc

1：24进制module m24(H,CPH,RD);output 7:0H;input CPH,RD; reg 7:0H;always(negedge RD or posedge CPH) begin if(!RD) H7:0=0; else begin if(H7:4=2)&(H3:0=3) begin H7:0=0; end else begin if(H3:0=9) begin H3:0=0; H7:4=H7:4+1; end else H3:0=H3:0+1; end end endendmodule2：60进制 分钟module m60M(M,CP60M,CPM,RD);output 7:0M;output CP60M;input CPM;input RD;reg7:0M;wire CP60M;always(negedge RD or posedge CPM) begin if(!RD) begin M7:0=0; end else begin if(M7:4=5)&(M3:0=9) begin M7:0=0; end else begin if(M3:0=9) begin M3:0=0; if(M7:4=5) begin M7:4=0; end else M7:4=M7:4+1; end else M3:0=M3:0+1; end end end assign CP60M=(M6&M4&M3&M0);endmodule3：60进制 秒钟module m60S(S,CP60S,CPS,RD);output 7:0S;output CP60S;input CPS;input RD;reg7:0S;wire CP60S;always(negedge RD or posedge CPS) begin if(!RD) begin S7:0=0; end else begin if(S7:4=5)&(S3:0=9) begin S7:0=0; end else begin if(S3:0=9) begin S3:0=0; if(S7:4=5) begin S7:4=0; end else S7:4=S7:4+1; end else S3:0=S3:0+1; end end end assign CP60S=(S6&S4&S3&S0);endmodule4：校时module xiaoshi2(CPM,CPH,CPS,CP60M,CP60S,SWM,SWH);output CPM,CPH;input SWM,SWH;input CPS,CP60S,CP60M;reg CPM,CPH;always(SWM or SWH or CPS or CP60S or CP60M) begin case(SWM,SWH) 2b01: begin CPM=CPS;CPH=CP60M;end 2b10: begin CPM=CP60S;CPH=CPS;end default:begin CPM=CP60S;CPH=CP60M;end endcase endendmodule5报时module baoshi(m6,m4,m3,m0,s6,s4,s3,s0,dy,gy,bshi);input m6,m4,m3,m0,s6,s4,s3,s0,dy,gy;output bshi;wire bm;reg bshi;assign bm=m6&m4&m3&m3&m0&s6&s4&s0;always(bm or s3 or dy or gy) begin if(bm&s3) bshi=gy; else if(bm) bshi=dy; else bshi=0; end endmodule 6时段控制module sdkz(h,sk);