Flash Memory测试简介PPT学习课件

Memory测试原理 1 Unit1 IntroductiontoFlashTechnology 2 OverviewofMemoryDevices Nonvolatile RAM DRAM SRAM EEPROM ROM EPROM PROM Volatile FLASH CourseContents 3 TwoBasicMemoryCategories VolatileMemory易挥发存储器Dataislostwhenpowerisremoved NonvolatileMemory非易挥发存储器Dataremainsevenwhenpowerisremoved 4 VolatileMemory RAM RandomAccessMemorySRAM StaticRAMiscommonlyusedas640Kbcachememoryincomputers DRAM DynamicRAMiscommonlyusedforread writememoryincomputers 5 NonvolatileMemory ROM ReadOnlyMemory ROM areprogrammedinawaferfabandcannotbeerasedorreprogrammedinthefield PROM ProgrammableROMcanbereprogrammedinthefieldbyapplyinglargervoltageswithspecialequipment EPROM ErasablePROMcanbeerasedwithUVlightandreprogrammedwithspecialequipment EEPROM ElectricallyErasablePROMcanbeerasedwithhighervoltagesandreprogrammedinthefield 6 NonvolatileMemory NVRAM NonvolatileRAM Flash issmallerthanPROMs lessexpensive andeasiertoprogramanderase Magnetic Magneticdiskandtapecanbeeasilyprogrammedanderasedbyuser butareslowerthanFlash Optical CDROMcanbeeasilyprogrammedbyuserbutisslowerthanFlash 7 BenefitsofFlashMemoryChips SmallerthanEPROMSandEEPROMSRequiresonlyonetransistorandastoragecapacitorperbitcell Canbequicklyandeasilyerasedandreprogrammedwithouttheneedofspecialequipment Excellentforuseincellphones pagers calculators portabledigitaldevices automotive flightdatarecorders andpersonalcomputers 8 SimpleROMMemoryArray 9 SimpleDRAMMemoryArray Capacitorcharged Nocurrent 0 Capacitoruncharged Currentflow 1 ActivateRowtoreadIfcapacitorwascharged nocurrentflowsonbitlineIfcapacitornotcharged currentflowsonbitlineBufferoncolumnsenseamps 10 SimpleEPROMMemoryArray Asecond floatinggate servesasthestorageelementinanEPROM 11 FloatingGate Source Gate FloatingGate electricallyisolated isthestorageelementcharged programmed neutral erased BasicFlashMemoryCell 12 FlashCellStructure SimilartoEPROM exceptElectrically erasable p Substrate ControlGate FloatingGate 13 FlashCellOperation ProgramModeChannelHot ElectronInjection GND VG 9 3V VD 4 5V Source Drain 14 FlashCellOperation ProgramModeChannelHot electronInjection GND VG 9 3V VD 4 5V Source Drain p Substrate ControlGate FloatingGate e e e e e e e e e e e e e e 15 FlashCellOperation ProgramModeIDSConduction FloatingGateCharge Q p Substrate GND VG 9 3V VD 4 5V ControlGate FloatingGate Source Drain Logicstate 0 16 FlashCellOperation EraseModeNegativeGate F NTunneling p Substrate ControlGate e e e e e e e e e e e e e e e Electrically erasablechargefromgate Source Drain Logicstate 1 17 FlashMemoryBitThresholdVoltages 18 FlashArrayArchitecture schematic Corememory core 19 FlashArrayCellAddressing RowDecoder ColumnDecoder SourceSwitch 20 BasicMemoryDeviceInternalArchitecture 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 A0 A1 A2 A3 A4 A5 A6 A7 Memorycell MemoryCellblock 每个CELL存储data 1 0 AddressDecoderCircuitry 地址译码以 A0 来选择不同的memorycellorblock进行读写操作 Input OutputI O circuitry 是memoryCell和外界的输入输出接口 将data在 D0 与Cell间传输 ControlCircuitry 控制memoryCell工作状态的电路CE OE WE ChipEnable OutputEnable WriteEnable 21 Unit2 DeviceTestingDCparametrictestACparametrictestFunctionalTest 22 DCparametrictest ISVM ForcecurrentmessagevoltageVSIM Forcevoltagemessagecurrent DCParametricTests 测试AddressDecoder和I O回路中Input OutputBuffer的DC特性 在DCTest中一般使用VSIM及ISVM的方法 DCContactCheck开路 短路测试OPEN SHORTInput OutputLeakageCheck输入 输出漏电流测试INLEAK OUTLEAKCMOSAutomaticSleepCMOS自动睡眠模式电流测试CMOSASMStandbyCurrentCheckDevice不工作时待机电流测试ICCSBOutputDriveVoltage CurrentDevice电压及电流驱动能力测试VOH VOL 23 DCParametricTestOPEN SHORTestINLEAK OUTLEAKTestCMOSASMICCSBTestVOH VOLTest 24 OpenTest Purpose 测量devicepins是否correctlytoDUT Testerchannel测量Device内部管脚是否有开路 Groundallpins includingVCC SetVoltageClamp3 0volts UsingPMU forcepositiveornegativecurrent onepinatatime Measureresultantvoltage Failstest open iftheabsolutevoltagemeasuredisgreaterthan1 5V TestMethod 25 ShortTest Purpose 测试thedevicepins是否有短路TestMethod Groundallpins includingVCC SetVoltageClamp3 0volts UsingPMU forcepositiveornegativeVoltage onepinatatime Measureresultantcurrent Failstest short iftheabsolutevoltagemeasuredislessthan0 2V 26 Definition IIL InputleakagelowThecurrentinaninputwhenitisforcedlowvoltage IIH InputleakagehighThecurrentinaninputwhenitisforcedhighvoltage Whytest TheIILtestmeasurestheresistancefromaninputpintoVCC IIHtestmeasurestheresistancefromaninputpintoVSS Thetestinsuresthattheinputbuffersofferahighresistancewhenapply0vandVCC InputLeakageTest INLEAK 27 InputLeakageLowTest IIL TestMethod ApplyVCCmax Preconditioningallinputstologic1withpindrivers InputdisableUsingPMU forceindividualinputstoVSS MeasurethecurrentflowsfromVCCtothepinbeingtested Repeatthesametestoneachpin FailsIILifmeasuredcurrentisoutsideofthespec 0V 28 InputLeakageHighTest IIH TestMethod ApplyVCCmax Preconditioningallinputstologic0withpindrivers InputdisableUsingPMU forceindividualinputstoVCC MeasurethecurrentflowsfromthepinbeingtestedtoVSS Repeatthesametestoneachpin FailsIIHifmeasuredcurrentisoutsideofthespec 3 5V 29 OutputLeakageTest IOL Purpose Tomeasuretheoutputcurrentleakage 1uAspec ApplyVCCmax PreconditioningallOutputstologic1withpindrivers OutputDisableUsingPMU forceindividualinputstoVCC MeasurethecurrentflowsfromthepinbeingtestedtoVSS Repeatthesametestoneachpin FailsIOLifmeasuredcurrentisoutsideofthespec TestMethod 30 OutputLeakageTest IOH Purpose Tomeasuretheoutputcurrentleakage 1uAspec ApplyVCCmax PreconditioningallOutputstologic0withpindrivers OutputDisableUsingPMU forceindividualinputstoVCC MeasurethecurrentflowsfromthepinbeingtestedtoVSS Repeatthesametestoneachpin FailsIOHifmeasuredcurrentisoutsideofthespec TestMethod 31 CMOSASMTest Purpose ThistestcheckstheCMOSAutomaticSleepMode ItisaguardbandedtestsusingaVccwhichis15 30 higherthanMax Vccandtestsagainstalimitof10 guardband Theinputpinsarebiasedattheworstpossibleconditionaswell lowestVIHandhighestVIL ApplyVCCmax chipenabled butatoutputdisablestate AutomaticSleepMode MeasurecurrentflowingintoVCCpinatVIH VILFailureCMOSASMwhencurrentisoutofSPEC TestMethod 32 ICCSBTest Purpose ThistestscheckstheIccStandbyCurrent Icc3intheTTLTable Thistestshouldbedonewithallinputshigh VIH andallinputslow VIL WiththemovetoeliminatetheTTLtable mostcompaniesdoNOTuseTTLlogicanymore thistesthasdecreasingimportance TestMethod ApplyVCCmax chipdisabled butatoutputdisablestate StandbyMode MeasurecurrentflowingintoVCCpinatVIH VILFailureICCSBwhencurrentisoutofSPEC 33 Outputvoltagestesting VOH IOHVOL IOL 34 Outputvoltagestesting VOH IOH Definition VOH representstheminimumvoltage V producedbyanoutput O whentheoutputisinthelogic1 High state IOH representsthecurrentsourcingcapabilities I ofanoutput O whentheoutputisinthelogic1 High state Whytest VOH IOHtestmeasurestheresistanceofanoutputpinwhentheoutputisinthelogic1state ThistestinsuresthattheresistanceoftheoutputmeetsthedesignparametersandguaranteesthattheoutputwillprovidethespecifiedIOHcurrentwhilemaintainingtheproperVOHvoltage 35 TestMethod ApplyVCCmin Preconditionoutputtologic1 outputhigh UsingPMU forceIOHcurrentperspecification Wait1to5msec SetPMUdelay Measureresultantvoltage FailsVOHofmeasuredvoltageislessthanthelimit Outputvoltagestesting VOH IOH 36 Definition VOL representsthemaximumvoltage V producedbyanoutput O whentheoutputisinthelogic0 Low state IOL representsthecurrentsinkingcapabilities I ofanoutput O whentheoutputisinthelogic0 Low state Whytest VOL IOLtestmeasurestheresistanceofanoutputpinwhentheoutputisinthe0state ThistestinsuresthattheresistanceoftheoutputmeetsthedesignparametersandguaranteesthattheoutputwillprovidethespecifiedIOLcurrentwithoutexceedingtheVOLvoltage Outputvoltagestesting VOL IOL 37 TestMethod DUT ApplyVCCmin Preconditionoutputtologic0 outputlow UsingPMU forceIOLcurrentperspecification Wait1to5msec SetPMUdelay Measureresultantvoltage FailsVOLofmeasuredvoltageisgreaterthanthelimit Outputvoltagestesting 38 ACParametricTesting Outputsignal therise falltimes Relationshipbetweeninputsignals thesetup holdtimes Relationshipbetweeninputandoutputsignals thedelaytimesSuccessiverelationshipbetweeninputandoutputsignals thespeedtest 39 ACparametrictest RiseandFallTime RiseandFalltime Toguaranteethatoutputdatariseandfallrate 40 ACparametrictest SetupTimeTSD Setuptime TSDtoguaranteethatinputdatacanbereadwithinaminimumamountoftimebeforeareferencesignaloccurs 41 ACparametrictest HoldTimeTHD Holdtime THDtoguaranteethatinputdatacanbereadwithinaminimumamountoftimeafterareferencesignaloccurs 42 ACparametrictest ProgramDelayTime PropagationDelayMeasurements TAAtoguaranteethatanoutputsignalcanoccurwithinaspecifiedamountoftimeaftertheoccurrenceofareferencesignal 43 FunctionalTest FunctionalTest 是为了保证Device的工作是Match它的TruthTable而进行的测试 由PatternGenerator模拟正常的工作状态 输出Pattern加入Device 将输出值与期望值相比较 Match的为Pass 不Match的为Fail 44 HierarchyinReducedfunctionalFaults Stuck AtFaultTransitionFaultCouplingFaultNPSFNeighborhoodPatternSensitiveFault 45 Stuck AtFault Thelogicvalueofastuck at SA cellorlineisalways0or1 itisalwaysinstate0orinstate1andcannotbechangedtotheoppositestate 46 TransitionFault Acellorlinewhichfailstoundergoa0 1transitionwhenitiswrittenissaidtocontainanuptransitionfault similarly adowntransitionfaultistheimpossibilityofmakinga1 0transition 47 CouplingFault AwriteoperationwhichgeneratesanUoraYtransitioninonecellchangesthecontentsofasecondcell whereUdenotesawrite1operationtoacellcontaininga0andYdenotesawrite0operationtoacellcontaininga1 ThetypesofcouplingfaultsusedforDRAMarebasedonthefollowingassumptionsforread writeoperations Areadoperationwillnotcauseanerror Anon transitionwriteoperationwillnotcauseafault Atransitionwriteoperationmaycauseafault 48 NeighborhoodPatternSensitiveFault APatternSensitiveFault PSF isdefinedasfollows Thecontentsofacell ortheabilitytochangethecontents isinfluencedbythecontentsofallothercellsinthememory ThePSFcanbeconsideredthemostgeneralcaseofthek couplingfault ThePSFmodelallowstheneighborhoodtotakeonanypositioninthememoryarray Whentheneighborhoodisallowedtotakeononlyasingleposition onespeaksaboutaNeighborhoodPatternSensitiveFault NPSF 49 FunctionTestItemExample READ0 READALL EMBERASE BLANKPRGDIAGVERDIAGPRGRVCKRVCKSPPRGSP1 2PRGCKBD 50 READ0 READALL PREERASE BLANK Thesetestblocksworktogethertoinsurethearrayisblankbeforetestingcontinues AportionofthearrayisreadusingREAD0orREADALL dependingontheflow DeviceswhichfailthisinitialblankcheckarePREERASE andthentheeraseisverifiedwithafullBlankCheck Description 51 PRGDIAG PRGDIAGEmbeddedProgramsareverseDIAGpattern Eachbyte wordmustprogramwithinSPECHottemperatureisworst casesincecolumnleakageisatitshighestlevels Onlytheprogrammed0 sareverifiedatthistestblock Description 52 VERDIAG Readsboth1 sand0 softheDIAGpattern TheDIAGpatternisdesignedtorevealmetalshorts M1 M1 M1 M2 andM2 M2 whichcauseblankbitstoprogramadjacenttothetargetprogrammingbit Programmingonlyonebitpercolumnhelpsrevealthistypeofdefect InFigure thearrayontherighthasametalshortbetweencolumns bitlines 2and3 Theshortaccidentallysharestheprogrammingdrainvoltagebetweenthetwocolumns Theprogrammingwordlinevoltageiscommonacrossarow soprogramminganybitincolumn2accidentallyprogramstheadjacentbitincolumn3 Description Thisiscalledbitpickup 53 PRGRVCK ProgrammingReverseCKBD Description RVCKisaworst casepatternforspeedsinceoutputsswitchoneveryaddresstransition 1 0 1 0 54 RVCKSP ReverseCKBDSpeed RVCKSPtestsACspeedbyreadingtheRVCKpatternwithtighttiming Thereareusuallysixspeedgrades Theprogramtestsunitsstartingwiththefastestspeedbin andmovingthroughthesixgradesuntilfindingapassingbin Theactualspeedvaluesofthesixbinsvaryfromprogramtoprogram dependingonthespeeddistributionofthepartandMarketingrequirements Anexampleof3Vspeedgradesisshownbelow Description 55 PRGSP1 2 ProgramSpeed ThePRGSP1 2blockstesttheACwriteparametersItEmbeddedProgramsonerowandonecolumnusingtighttimingparametersandaddress dataformatting Aprogrammingfailureindi