基于FPGA的数字钟设计

1草鱼草鱼基于FPGA的数字钟系统草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼姓名PORK蒋佳霖草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼学号PORK1023000657草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼学院PORK物理与电子学院草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼摘要PORK本文利用FPGA的VERILOG语言设计数字钟系统。草鱼并采用QUARTUSE进行综合，鲤鱼仿真，鲤鱼实验。草鱼经过测试，鲤鱼本文所设计的系统基本可以实现数字的计时和显示，鲤鱼调整时间的功能。草鱼草鱼关键字FPGA，鲤鱼VERILOG语言，鲤鱼数字钟系统草鱼2设计所实现的功能草鱼本文所设计的数字钟系统能进行时，鲤鱼分，鲤鱼秒的显示，鲤鱼和对时间的校正。草鱼能够利用按键进行“调时”，鲤鱼“调分”，鲤鱼“清秒”的功能，鲤鱼随时对数码管进行调整和校正。草鱼数字钟系统是由系统时钟，鲤鱼数码管，鲤鱼FPGA，鲤鱼三个功能键组成。草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼设计所采用的思想草鱼本文所设计的数字钟系统采用VERILOIG自顶而下的设计方法。草鱼在编程中，鲤鱼通过键位的数值的判断来调用例化语句实现控制模块对计时模块和分频模块的控制。草鱼草鱼各模块的代码及测试情况草鱼分频模块的代码PORK草鱼MODULE草鱼草鱼SZZ_FENPINCLK,CLK_1HZPORK草鱼INPUT草鱼CLKPORK草鱼OUTPIT草鱼CLK_1HZPORK草鱼REG310草鱼草鱼COUNTPORK草鱼草鱼ALWAYS草鱼POSEDGE草鱼CLK草鱼草鱼草鱼BEGIN草鱼草鱼IF草鱼草鱼COUNT草鱼草鱼M/21草鱼草鱼草鱼草鱼草鱼BEGIN草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼CLK分频器模块CLK_1HZ计时模块控制模块数码管3COUNT草鱼草鱼COUNT草鱼草鱼1PORK草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼END草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼ELSE草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼BEGIN草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼COUNT草鱼草鱼0PORK草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼CLK_1HZ草鱼草鱼CLK_1HZPORK草鱼草鱼草鱼草鱼草鱼草鱼草鱼草鱼END草鱼END草鱼ENDMODULE草鱼注PORK本文所使用的分频模块只能进行偶数分频。草鱼M为分频的倍数。草鱼草鱼计时模块PORK草鱼MODULE草鱼SZZ_JSCLK_1HZ,NUM1,NUM2,NUM3,NUM4,NUM5,NUM6PORK草鱼INPUT草鱼CLK_1HZPORK草鱼OUTPUT草鱼REG30草鱼NUM1,NUM2,NUM3,NUM4,NUM5,NUM6PORK草鱼ALWAYSPOSEDGE草鱼CLK_1HZ草鱼BEGIN草鱼IFNUM64B10PORK草鱼NUM64B0PORK草鱼END草鱼ELSE草鱼IFNUM54B1001草鱼4BEGIN草鱼NUM6NUM64B1PORK草鱼NUM54B0PORK草鱼END草鱼ELSE草鱼IFNUM44B0110草鱼草鱼BEGIN草鱼NUM5NUM54B1PORK草鱼NUM44B0PORK草鱼END草鱼ELSE草鱼IFNUM34B1001草鱼BEGIN草鱼NUM34B0PORK草鱼NUM4NUM44B1PORK草鱼END草鱼ELSE草鱼IFNUM24B0110草鱼BEGIN草鱼NUM24B0PORK草鱼NUM3NUM34B1PORK草鱼END草鱼ELSE草鱼IFNUM14B1001草鱼BEGIN草鱼NUM14B0PORK草鱼5NUM2NUM24B1PORK草鱼END草鱼ELSE草鱼BEGIN草鱼NUM1NUM14B1PORK草鱼END草鱼END草鱼ENDMODULE草鱼草鱼注本文所使用的计时模块的代码采用状态机，鲤鱼非阻塞语句赋值，鲤鱼所以在判以后不会立即清零，鲤鱼所以判断采用是当其为5的时候才进行下一次状态，鲤鱼并在下一次状态进行清零。草鱼草鱼控制语句PORK草鱼MODULE草鱼草鱼SZZ_KZCLK,RST,TURN1,TURN2,TURN3,N1,N2,N3,N4,N5,N6,RS1,RS2,RS3,RS4,RS5,RS6PORK草鱼INPUT草鱼CLK,TURN1,TURN2,TURN3,RSTPORK草鱼INPUT草鱼30草鱼N1,N2,N3,N4,N5,N6PORK草鱼OUTPUT草鱼REG30草鱼RS1,RS2,RS3,RS4,RS5,RS6PORK草鱼REG30NUM1,NUM2,NUM3,NUM4,NUM5,NUM6PORK草鱼ALWAYSPOSEDGE草鱼CLK草鱼BEGIN草鱼IFRST草鱼BEGIN草鱼RS1N1PORK草鱼RS2N2PORK草鱼RS3N3PORK草鱼RS4N4PORK草鱼RS5N5PORK草鱼RS6N6PORK草鱼END草鱼ELSE草鱼草鱼BEGIN草鱼RS1N1PORK草鱼RS2N2PORK草鱼6RS3N3PORK草鱼RS4N4PORK草鱼RS5N5PORK草鱼RS6N6PORK草鱼RS5RS5NUM5PORK草鱼RS3RS3NUM3PORK草鱼IFTURN1草鱼草鱼BEGIN草鱼草鱼RS5N5PORK草鱼草鱼NUM5NUM54B1PORK草鱼草鱼END草鱼IFTURN2草鱼草鱼BEGIN草鱼草鱼RS3N3PORK草鱼草鱼NUM3NUM34B1PORK草鱼草鱼END草鱼IFTURN3草鱼草鱼草鱼草鱼草鱼草鱼BEGIN草鱼草鱼草鱼草鱼草鱼草鱼RS20PORK草鱼草鱼草鱼草鱼草鱼草鱼RS10PORK草鱼草鱼草鱼草鱼草鱼草鱼END草鱼END草鱼ENDMODULE草鱼注PORK本控制程序是对键位的高电平进行监测，鲤鱼则进行清秒，鲤鱼调分，鲤鱼调时的功能。草鱼草鱼程序的测试图草鱼草鱼图为计数模块的部分的图形。草鱼草鱼7草鱼图为程序调试以后的结果草鱼程序代码草鱼草鱼注PORK因为在FPGA的试验台上有1HZ的CLK信号，鲤鱼所以在实现时可以将CLK信号直接设置为1HZ，鲤鱼故省略例化分频语句。草鱼草鱼MODULE草鱼SZZ_JSCLK_1HZ,NUM1,NUM2,NUM3,NUM4,NUM5,NUM6PORK草鱼INPUT草鱼CLK_1HZPORK草鱼OUTPUT草鱼REG30草鱼NUM1,NUM2,NUM3,NUM4,NUM5,NUM6PORK草鱼ALWAYSPOSEDGE草鱼CLK_1HZ草鱼BEGIN草鱼IFNUM64B10PORK草鱼NUM64B0PORK草鱼END草鱼ELSE草鱼IFNUM54B1001草鱼BEGIN草鱼NUM6NUM64B1PORK草鱼NUM54B0PORK草鱼END草鱼ELSE草鱼IFNUM44B0110草鱼草鱼BEGIN草鱼NUM5NUM54B1PORK草鱼NUM44B0PORK草鱼END草鱼ELSE草鱼IFNUM34B1001草鱼BEGIN草鱼NUM34B0PORK草鱼NUM4NUM44B1PORK草鱼END草鱼ELSE草鱼IFNUM24B0110草鱼BEGIN草鱼NUM24B0PORK草鱼9NUM3NUM34B1PORK草鱼END草鱼ELSE草鱼IFNUM14B1001草鱼BEGIN草鱼NUM14B0PORK草鱼NUM2NUM24B1PORK草鱼END草鱼ELSE草鱼BEGIN草鱼NUM1NUM14B1PORK草鱼END草鱼END草鱼ENDMODULE草鱼草鱼草鱼MODULE草鱼SZZ_KZCLK,RST,TURN1,TURN2,TURN3,N1,N2,N3,N4,N5,N6,RS1,RS2,RS3,草鱼RS4,RS5,RS6PORK草鱼INPUT草鱼CLK,TURN1,TURN2,TURN3,RSTPORK草鱼INPUT草鱼30草鱼N1,N2,N3,N4,N5,N6PORK草鱼OUTPUT草鱼REG30草鱼RS1,RS2,RS3,RS4,RS5,RS6PORK草鱼REG30NUM1,NUM2,NUM3,NUM4,NUM5,NUM6PORK草鱼ALWAYSPOSEDGE草鱼CLK草鱼BEGIN草鱼IFRST草鱼10BEGIN草鱼RS1N1PORK草鱼RS2N2PORK草鱼RS3N3PORK草鱼RS4N4PORK草鱼RS5N5PORK草鱼RS6N6PORK草鱼END草鱼ELSE草鱼草鱼BEGIN草鱼RS1N1PORK草鱼RS2N2PORK草鱼RS3N3PORK草鱼RS4N4PORK草鱼RS5N5PORK草鱼RS6N6PORK草鱼RS5RS5NUM5PORK草鱼RS3RS3NUM3PORK草鱼IFTURN1草鱼草鱼BEGIN草鱼草鱼RS