数字设计课件第七章时序逻辑设计原理

Chapter7sequentiallogicdesignprinciples,state,statevariablelatches,flip-flopsanalysissynthesis,sequentialcircuit,theoutputsdependnotonlyonitscurrentinputs,butalsoonthepastsequenceoftime,possiblyarbitrarilyfarbackintime.,Someimportantconcepts,stateandstatevariablestate:collectionofstatevariable,containalltheinformationaboutthepastnecessarytoaccountforthecircuitsfuturebehavior.statevariable:thesymbolrepresentationofstate.finite-statemachinethestatesofasequentialcircuitisalwaysfinite.,nstatevariables,2npossiblestates,Someimportantconcepts,clockaclocksignalisasignalusedtocoordinatetheactionsoftwoormoresequentialunits.clockedsynchronousstatemachineallmemoryofthesequentialcircuitchangesonlyonaclockedgeorsignallevel.,H,L,7.1BistableElement,Outputvariable：Q，Q_L，且Q_L=QTwostablestate:Q=0、Q_L=1Q=1、Q_L=0,feedback,1,2,Qisthestatevariable,analysiswithtransfercharacteristic,VOUT=T(VIN),VIN,VOUT,7.2LatchesandFlip_Flops,basicbuildingblockbeclassifiedasS-R、D、T、J-Ktypesdefinition:latch：watchesthecircuitsinputscontinuouslyandcanchangestheoutputsatanytime.flip-flops：samplesthecircuitsinputsandchangestheoutputonlywhenaclockingsignalischanging.,1、SRLatches,S-RlatchbuiltwithNORgates,Q=QN=Q_L,hold,reset,set,forbidden,1,2,thestoredbitispresentontheoutputQ.,SandR:activehighsignal,Functiontable,进入亚稳态,(2)minimumpulsewidth,thetimeofactivelevelofSorRmustbekeepinglongerthanminimumpulsewidth,orelsethelatchmaybegointometastable.,propagationdelayisexistwhenatransitiononSorRinputproduceatransitiononanoutputsignal.,S,(3)symbolandcharacteristicequation,S=R=1,restrictedcombination,characteristicequationforS-Rlatch:Q*=S+RQ（SR=0）,currentstate,nextstate,2、S-Rlatch,builtwithNANDgates,S_L、R_L:activelowsignals,hold,reset,set,forbidden,3、S-Rlatchwithenable,metastablestillexist,forbidden,4、Dlatch,保持,R,S,characteristicequationQ*=D（C=1）transferdatatransparently,whenC=0，thedataislatchedonQ.,timingdiagram,datatransfered,datalatched,5、Edge-TriggeredDFlip-Flops,Edge-Triggered：outputofflip-flopchangesontheclocksignalsrisingedgeorfallingedge.,positiveedge（risingedge）,negativeedge（fallingedge）,CLOCK,positive-edge-triggeredDflip-flop,master-slavestructureCLK=0，QM=D，USholdlastQ；Attheclocksrisingedge,USenable，UMholdlastQM，Q=QM；CLK=1，UMholdlastQM，soQholdlastQ。,UM,US,Onlyattherisingedgeofclocksignal,DinputcouldbetransferredtoQoutput.,Others,PR_L:presetCLR:clear,Negative-edge-triggeredDflip-flop,edge-triggeredDflip-flopwithasynchronousinputs,6、edge-triggeredDflop-flopwithenable,characteristicequation：Q*=END+ENQ,frequencydividerwithDf-fs,divide-by-2divider,7、scanflip-flop,TE=1，testoperationmode，f-fstakeTIdata.TE=0，normalDf-f-s，takeDdata.,Normalinput,Testenable,Testinput,8、master/slaveS-R触发器,Q*=S+RQ（SR=0）C=1,masterlatchfollowstheS-Rinput;Cgoesto0,Qoutputthefinallatchedvalueofmasterlatch.Itisnotedge-triggeredf-fs,butpulse-triggered.,C,S,R,QM,QM_L,Q,Q_L,TimingdiagramofS-Rf-fs,9.master/slaveJ-Kflip-flop,stucture,J,K,C,Q,Q_L,feedback,C=1，masterlatchfollowtheinput;Cgoesto0,Qoutput(slavelatch)thefinallatchvalue.,Master,Slave,JKflip-floptimingdiagram,J,K,C,Q,Q_L,C,J,K,QM,QM_L,Q,Q_L,features,reset,set,toggle,hold,Pulse-triggeredf-f-s,Characteristicequations：Q*=JQ+KQ,EliminatethepossiblemetastablewhichexistintheS-Rf-fs(restrictedinput,S=R=1).But,1scatchingand0scatchingareexist.,hold,1scatching,C=1，当上次Q=0，当前JK=0时，若J有1的出现，触发器会捕捉到这一变化，置Q=1。以后，J有1到0的变化，电路不会响应。,0scatching,当上次Q=1，当前JK=0时，若K有1的出现，触发器会捕捉到这一变化，置Q=0。以后，K有1到0的变化，电路不会响应。,10、Edge-triggeredJ-KFlip-Flop,sampletheinputsandchangetheoutputstateattheedgeofclock。characteristicequations：Q*=JQ+KQeliminatethe“1scatching”and“0scatching”.,Timingdiagramofedge-triggeredJ-Kf-fs,11、TFlip-Flop,T:togglefunctionaltable,symbol,characteristicequation：Q*=TQ+TQ,Implementation,ContributebyDorJ-Kf-fs.,TFlip-Flopwithenable,EN=1，normalTflip-flop;EN=0，holdthelastvalue,summary:latchesandflip-flops,labelbystructure：latches：S-R、Dlatchesflip-flops：S-R、D、J-K、Tflip-flopslabelbytriggeringform：pulse-triggered、edge-triggeredonelatchorflip-flopisastorageelements,whichcanstoreonebit(0or1).italsoactasastatevariable,andmorestorageelementscanbecombinedtostoremorebitswhichusedtomemorystatesinsequentialcircuit.,summary:characteristicequation,S-RlatchDlatchDflip-flopDflip-flopwithenableM/SS-Rflip-flopM/SJ-Kflip-flopedge-triggeredJ-Kflip-flopTflip-flop,Q*=S+RQ（SR=0）Q*=DQ*=DQ*=END+ENQQ*=S+RQ（SR=0）Q*=JQ+KQQ*=JQ+KQQ*=TQ+TQ,7.3clockedsynchronousstate-machineanalysis,emphases：BasicstructureMealymachineandMooremachine.understandactionofeachmoduleandtheirequations,tables.analysiswithDf-fs,1、stucture,（1）Mealymachine,Next-statelogicF,statememoryclock,OutputlogicG,inputs,excitation,Currentstate,outputs,Clocksignal,constructbycombinationalcircuit,theoutputsignalistheexcitationinputofstorageelement.nextstate=F(currentstate,input),constructbyflip-flops,canstore2nstateatmost,constructbycombinationalcircuit,output=G(currentstate,input),返回,（2）Mooremachine,Next-statelogicF,statememoryclock,OutputlogicG,PS:output=G(currentstate),inputs,Clocksignal,excitation,Currentstate,outputs,2.analysisexample,statevariable：Q0、Q1,excitation：D0、D1,output：MAX,D0=F（EN，Q1，Q0）=(ENQ0)+(ENQ0)=ENQ0+ENQOD1=F（EN，Q1，Q0）=ENQ1+ENQ1Q0+ENQ1Q0,excitationequation,CharacteristicequationofDf-fs：Q*=D,Transitionequation：Q1*=D1=ENQ1+ENQ1Q0+ENQ1Q0Q0*=D0=ENQ0+ENQO,transitionequation,Transitiontableandstatetable,Transitionequation：Q1*=ENQ1+ENQ1Q0+ENQ1Q0Q0*=ENQ0+ENQO,Transitiontable,Statetable,Assignstatenametoeachstate:Q1Q0S00A01B10C11D,Currentstate,input,Nextstate,MAX=ENQ1Q0,Outputequation,EN,MAX,Transition/outputtable,state/outputtable,Transition/outputtable,state/outputtable,A,D,C,B,Statediagram,Q1Q0,Statevariablecombinationcanbewriteinthecircledirectly.,注意：有限状态机的时序分析必须以时钟周期为单位依序进行。,Timingdiagram,AnalysisofMooremaching,excitationequationandtransitionequationarechangeless,MAXS=Q1Q0,transitiontable,statetable,AMAXS=0,DMAXS=1,CMAXS=0,BMAXS=0,EN=0,EN=1,EN=0,EN=1,EN=0,EN=1,EN=0,EN=1,showoutputvalueinsidethecircle,statediagram,例1、2的时序对比分析,statetransitionfeature,transitionexpressiononarcsleavingaparticularstatemustbemutuallyexclusiveandallinclusive.Notwotransitionexpressionscanequal1forthesameinputcombination;Foreverypossibleinputcombination,sometransitionexpressionmustequal1.,S1,I1,Si,S1,Sn,Ii,In,transitionexpression,3、analysiswithJ-Kflip-flops,(1)excitationequation：J0=K0=1J1=K1=XQ0,(2)transitionequation:Q0*=J0Q0+K0Q0=Q0Q1*=J1Q1+K1Q1=XQ0Q1,(3)outputequation：Z=Q0Q1,(4)transition/outputtableandstate/outputtable,assignstatename：Q1Q0S00A01B10C11D,AZ=0,DZ=1,CZ=0,BZ=0,X=1,X=0,X,X,X,X,X,X,statediagram,CP,timingdiagram,X,Q1,Q0,Z,Exp3：analyzethefollowingcircuit,X,CLK,Z,(1)excitationequation：T1=XT2=XQ1,T1,T2,Q1,Q2,(2)transitionequation：Q1*=T1Q1+T1Q1=XQ1+XQ1Q2*=T2Q2+T2Q2=XQ1Q1+（XQ1）Q1,(3)outputequation：Z=XQ1Q2,7.4clockedsynchronousstate-machinedesign,Constructstate/outputtable,Stateminimization（可选）,Stateassignment,Constructtransition/outputtable,Chooseflip-flops,Constructexcitationtable,Derivingexcitationequation,Derivingoutputequation,Drawinglogiccircuitdiagram,Exp1:sequence-detectordesign,Designa“110”sequence-detector.iftheserialinputbinarynumberincludecontinuous“110”sequence,thecircuitoutput1.synthesisbyDflip-flops.thatisinputP：outputC：solution1：Mooremachine（1）inputandoutputvariableinput：P（每次给电路送一个二进制数码）output：C（表明检测的结果，1位）,firstinput,stateanalysisofexp.1,P：,C：,目标：检测110,Input0,Input1,Exp1:sequence-detectordesign,Definingstate：S0receivedasingle0S1receivedasingle1S2receivedacontinuous“11”S3receivedacontinuous“110”,state/outputtable,（2）stateminimization（3）stateassignment（状态的分配、赋值）nstatevariables2nstates。Then,Sstatesneed(?)statevariables(flip-flops)torepresent.Thenumberoff-fs：m=2，namedQ0、Q1Assignstatevariablecombinationstoeachsymbolstate：S：S0S1S2S3Q1Q0：00011011,Usestatecombinationstosubstitutethesymbolstate.,(4)constructtransition/outputtable,S0,S1,S2,S3,(5)Constructexcitationtable,Chooseflip-flopsanduseapplicationequationtoconstructexcitationtable.,FunctiontableofDf-f-s,Applicationtable,Excitationtable,Applicationequation：D=Q*,D1=Q1Q0+Q1Q0PD0=Q1Q0P+Q1Q0P+Q1Q0P,(6)Derivetheexcitationequations,C=Q1Q0,(7)Derivetheoutputequation,思考：若状态赋值时，采用gray码顺序给各状态赋值，则电路是怎样的？,（1）definingstatesS0receiveasingle0，C=0S1receiveasingle1，C=0S2receivecontinuous“11”，C=0S3receivecontinuous“110”，C=1,Solution2:usemealymachine,(2)Constructstate/outputtable,S0andS3areequivalentstates，soeliminateS3,andgettheminimizedstate/outputtable.,S0,(3)Stateminimization,Numberoff-fs：namedQ1、Q0Q1Q0=00，01，10，11choose3toassigntothe3knownstates。like，S000，S101，S211Q1Q0=10，unusedstate.,Transition/outputtable,(4)Stateassignment,minimalrisk,minimalcost,Dispositionofunusedstates,(5)Constructexcitationtable,UseDf-fsandinminimalcostdisposition.,Excitationtable,Applicationequation：D=Q*,(6)Derivetheexcitationequationsandoutputequation,D1=Q0PD0=PC=Q1P,anotherway:synthesisusingJ-Kf-fs,ApplicationtableofJ-Kf-fs,Excitationtable,Minimalcostdisposition,ExcitationequationsJ1=PQ0K1=PJ0=PK0=PoutputequationC=Q1P,Excitationequationsandoutputequation,课堂练习,试写出如下电路的激励方程和转移方程。,D1=XQ0Q1D0=XQ0+Q1Q1*=D1Q0*=D0Y=X+Q1Q0,Designexamplesinbook,Exp1:DesignamachineinputsAandBwithoutputZthatis1if:AhadthesamevalueatthetwopreviousticksBhasbeen1sincethelasttimetheabovewastrue）,CLK,A,B,Z,Atthebeginning,setstateINIT，Z=0状态A0，A收到一个0，Z=0状态A1，A收到一个1，Z=0状态OK0，A收到连续的两个0，Z=1状态OK1，A收到连续的两个1，Z=1状态A001，A收到连续的两个0后，收到1，同时B=1，Z=1状态A110，A收到连续的两个1后，收到0，同时B=1，Z=1状态AE10，A已经收到过连续的00或11，收到连续的10，同时B=1，Z=1状态AE01，A已经收到过连续的00或11，收到连续的01，同时B=1，Z=1,1.Findstates,电路开始工作，设置INIT状态，Z=0状态A0，A收到第一个0，Z=0状态A1，A收到第一个1，Z=0状态OK0，A收到连续的两个0，Z=1状态OK1，A收到连续的两个1，Z=1状态A001，A收到连续的两个0后，收到1，同时B=1，Z=1状态A110，A收到连续的两个1后，收到0，同时B=1，Z=1状态AE10，A已经收到过连续的00或11，收到连续的10，同时B=1，Z=1状态AE01，A已经收到过连续的00或11，收到连续的01，同时B=1，Z=1,Equivalentstates,eliminatestateAE10,Equivalentstates，eliminatestateAE01,Stateminimization,Equivalentstates,eliminatestateA001,Equivalentstates，eliminatestateA110,Stateminimization,最小化状态个数的状态表,Minimalstatetable,Stateassignment,Possiblestateassignments,Q1=0,intheINITstateQ1=1,inthenon-INITstate,Inthenon-INITstate,Q3givethepreviousvalueofA;Q2indicatesthattheconditionsfora1outputaresatisfiedinthecurrentstate.,Transitiontableandexcitationtable,？,Completedexcitationtable,Twoapproaches:MinimalcostMinimalrisk,Dispositionofunusedstates,D1,Minimalrisk,D1=Q1+Q2Q3D2,D3,Z=Q1Q2,D1,Minimalcost,D1=1D2,D3,Z=Q2,LogicdiagraminminimalcostforExp1,LogicdiagraminminimalriskforExp1,Exp2:1s-countingmachine,designaclockedsynchronousstate-machinewithtwoinputsXandY,andoneoutputZ,theoutputshouldbe1ifthenumberof1inputsonXandYsinceresetisamultipleof4,and0otherwise.,reset,Eachstaterecordthenumberof1inputonXandY：Multipleof4implythatthenumberof1inputcanbedividedby4.(MOD4=0)NMOD4=0，Z=1S0NMOD4=1，Z=0S1NMOD4=2，Z=0S2NMOD4=3，Z=0S3,Namingstate,Synthesissteps,1、state/outputtable,2、stateassignment:S000、S101、S211、S310,3、transition/outputtable,4、applicationtable,Exp3:acombinationlock,requirement:UNLK=1ifandonlyifXis0andthesequenceofinputsreceivedonXattheprecedingsevenclockticksofXwas0110111.HINT=1ifandonlyifthecurrentvalueofXisthecorrectonetomovethemachineclosertobeinginthe“unlocked”state(withUNLK=1).Itisasequence-detectormachine,7.5designingstatemachinesusingstatediagram,Differencebetweenstatetable