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Available online at ScienceDirectIFAC-PapersOnLine 48-4 (2015) 354361On PLCs Control Program Hardware Implementation Selected Problems of Mapping and SchedulingAdam Milik*Institute of Electronics, Silesian University of Technology of Gliwice, Poland (e-mail: ik polsl.pl).Abstract: The paper shows the FPGA dedicated method of mapping a PLC program written according to the IEC61131-3 standard. There is described complete synthesis process from the program description to hardware implementation through mapping and scheduling procedures. PLCs programming languages are translated into common intermediate graph form. It enables massive parallel implementation. There is presented an originally developed graph structure with attribute edges. Finally the graph mapping methodologies are discussed. A general hardware mapping concept and algorithms for utilizing specific FPGA components are presented. An efficient mapping of the DSP48 block is shown. It attempts to utilize all features of the block in pipelined calculation model. The consideration are summarized with implementation result comparison for general hardware mapping and with use of DSP48 units. 2015, IFAC (International Federation of Automatic Control) Hosting by Elsevier Ltd. All rights reserved.Keywords: PLC, FPGA, DSP48, LD, IL, SFC, DFG, high level synthesis, logic synthesis, reconfigurable hardware1. INTRODUCTIONProgrammable logic controllers (PLCs) are present from early 70s of XX century. They successfully replaced the mechanical and electro mechanical control systems offering better performance and reliability. Today PLCs become a standard in automation. The performance improvement of logic controllers is a main concern for automation system designers. Is it possible to improve the performance of a PLC? An attempt to answer this question is made by different researchers like in (Chmiel and Hrynkiewicz, 2010). One of the ideas that can significantly increase performance is fully custom hardware implementation of controller structure (Du et al. 2010, Economakos and Economakos 2012, Ichikawa et al. 2011, Mocha and Kania 2012, Milik 2013) It was even shown that controllers with advanced fuzzy algorithms are efficiently implemented in hardware (Wyrwo and Hrynkiewicz, 2013). They are opposite to microprocessor based implementation that are based on serial processing of instructions. The serial processing concept is a source of significant performance limitation. It can be overcome by dedicated implementation of a hardware structure for a particular control task execution. In opposite to serial processing a massively parallel processing is possible with use of SRAM configured FPGAs. The application specific logic controller (ASLC) assures reprogramability through the static reconfiguration. It is worth to mention an interesting proposal of a dedicated PLC FPGA described in (Welch and Carletta, 2000).The great success of PLCs is connected with easiness of programming. The method of program design has been standardized by the IEC61131-3 document and its subsequent revisions (Cenelec, 2013, John and Tiegelkamp, 2010). Thereis described a wide range of programming languages from the simple textual instruction list (IL) to the high level structured text (ST). The ladder diagram (LD) graphical language is still very popular among automation designers. It has been inherited from design methodology based on electrical schematics of relay control systems. The SFC language is derived from GRAFCET (David, 1995). It offers ability of describing concurrent processes. All languages allow to express a control algorithm independently from a target hardware platform. Automation designers do not have to go into implementation details and concentrate on solving the control problem.The ASLC (application specific logic controller) is implemented from a standard program with use of the high level synthesis covering: translation, scheduling and mapping. Each of those steps requires knowledge and skills from areas like: compilation, digital synthesis, operation schedule, hardware mapping. To make the application specific logic controller competitive to standard PLCs the set of EDA tools must be created. This paper is a continuation of research program over the ASLC implementation (Milik and Hrynkiewicz 2012 and 2014, Milik 2013). It briefly recalls basic definitions and recently presented methods of intermediate program representation. Than it moves to stages devoted to technology mapping. There are discussed an early mapping stages, scheduling problems and different mapping strategies targeted to specific components of contemporary FPGAs represented by the Xilinx Spartan 6 family.2. THE PLC PROGRAM INTERMEDIATEREPRESENTATIONThe control program must be translated into a form that is suitable for further handling accommodated to hardware2405-8963 2015, IFAC (International Federation of Automatic Control) Hosting by Elsevier Ltd. All rights reserved. Peer review under responsibility of International Federation of Automatic Control.10.1016/j.ifacol.2015.07.060Adam Milik et al. / IFAC-PapersOnLine 48-4 (2015) 354361361synthesis. It is expected that intermediate representation allows not only revealing the program semantics but also operation dependencies. It is important to reveal allindependent operations for possible parallel execution in hardware. An enhanced data flow graph (EDFG) has beenQ is the set of variables associated with outputs and internal nodes. The above sequential processing is transformed to parallel processing by introducing an auxiliary variables set D as follows:proposed. The flow graphs are commonly used by compilers (Hopcroft and Ullman 1979, Wirth, 1976) and in hardwared i = f i (I , d 1,., d i-1, qi,., qn);i = 1KnQ = D(2)synthesis (Gajski et al., 1994).The EDFG is a directed acyclic graph. It is given by G=V, E where: V is a set of nodes and E is a set of directed edges. The directed edge e is an ordered triple e = vSRC, vDST, a where: vSRC is a predeceasing node and vDST is a successor node of the directed edge. The a is an attribute of the edge chosen from the set A. The set A consist of unary operations applicable for a particular node type. Exemplary EDFGs are shown in the figure (Fig. 1). The attributed edge combines an assignment operation with a logic or an arithmetic complement. This modification significantly simplifies algorithms for graph creation, optimization and hardware mapping. There are shown the raw form of the logic graph(1) and the arithmetic graph (3) obtained during compilation process. Next to them are shown graphs after merge operations (2) and (4) respectively. A conditional execution is implemented with use of selection node shown in (5).The compilation process is aimed for obtaining the high performance processing model. It is based on single processing cycle by propagating input variables through the nodes of an EDFG until assignment nodes. It has been described in details in (Milik, 2013). The compilation process assures the sequential processing according to proper variable accessing. This can be put down as ordered sequence of functions represented by rungs of the LD:The D set represents already evaluated values. The processing cycle is completed by the items value assignment form D to Q.Ladder diagramabq1 q1cq1q2 Sequential Functional Chartc1 c2Fig. 2. The compilation outline process for LD and SFC to EDFGThe figure (Fig. 2) shows an essence of a compilationqi = f i ( I ,Q),i = 1.r(1)concept. The input languages are translated into commonWhere: I denotes the set of variables associated with inputs,3.4.abcde5.yrepresentation of the EDFG. The first case shows the LD compilation process to raw EDFG form that is further processed (optimized). The second case depicts translation of the SFC step into an equivalent EDFG structure. The control program written with use of different languages is brought to the common representation that retain processing capabilities. Directed edges determine operation dependencies that enables extracting independent operations and tasks.3. PREPARATION FOR GENERAL HARDWAREMAPPINGAfter generation and optimization stages the EDFG graph is transformed in order to meet target hardware platform requirements. The general hardware mapping procedure assumes that there are present basic arithmetic blocks corresponding to graph operations nodes (addition, multiplication and division). Attributed edges allows for easyGraph Items DescriptionANDORADDSUBConditional selectionoptimization of arithmetic expressions. The node merge reduces the tree height and respective paths length from variable or constant read nodes to assignment nodes. The node merge also simplifies constant handling. An arithmeticSimple edgeNOT edge Complement edgeFig. 1. The EDFG conceptoperation node argument set after optimization (propagation) contains maximally one constant node. It is important to balance the graph while the compilation process creates thegrapevine form from consecutive assignments. There are two fundamental transformations described further that are applied to the EDFG before scheduling and mapping process can take place.3.1. Complement edges transformationThe EDFG complement edges are convenient for transforming arithmetic operations. When all transformations (optimizations) on the arithmetic level are completed the complement edges are translated into equivalent hardware representation. It consists of adder, logic inversion and constant value:complementary edge by reducing it (Fig. 3.3) or propagating to the constant (Fig. 3.4). Finally the single complement edge is propagated before or after node. The decision depends on successive node. If successive node performs addition the complementary edge is forward propagated. When the forward propagation is not possible the complement operation is expanded and back propagated to the argument with shorter calculation time.3.2. Multiple arguments node expansionThe node with multiple arguments (2) does not correspond to elementary hardware components. It cannot be directlymapped and requires expansion to satisfy real component-a = a +1(3)constraints. The expansion process creates two argumentThe respective expansion procedure is applied to arithmetic nodes with complemented arguments only. It is aimed for reducing the number of additional operations but does not constraint successive processes. The complement arc transformation process connected to addition node is shown in figures (Fig. 3.1 and Fig. 3.2). The process changes each complement arc into a bitwise inversion arc and adds a constant 1. Referring to the property of a single constant argument per operation node, the constant values are merged. The transformation process is applied iteratively to all complementary arcs. Finally operation is implemented with use of the adder and typical logic components available innodes that are directly mapped. A special handling is used for additive nodes with a constant. The developed expansion process iteratively expands arithmetic nodes with more than two arguments. The expanded arguments calculation time is taken into consideration during the process. The procedure balances a total calculation time of the subtree during node expansion. Considering execution time allows for better balancing the tree and improve obtained scheduling result. Let variable t is associated with the EDFG node and describes the operation completion time. The operation completion time (in as soon as possible approach) for particular node is calculated as:FPGAs. An adder is implemented with use of LUT andt = MAX (t ) + tp(4)arithmetic support components next to it creating carry chain. The multiplicative operation nodes allow reduction of1.jijiWhere: tj is a j node calculation completion time, ti is ith argument node completion time of node j and tpj is j nodey=a+b-c-d+3y=a+b+c+5operation completion time according to the operation typeand implementation target. The tj value can be determined2. y=a+b-c-dy=a+b+c+2provided all ti are knownThe expansion algorithm starts from initializing the variable t for each operation node. The variable t in the figure (Fig. 4.1) is shown as a subscript of each node. The t variable of operation node is set to uninitialized value (t = -1) except of reading variable nodes. Those nodes are initialized with t = 0 as the value is immediately available. Following procedure is1.2.3.y=(-a)*(-b)y=a*b4. y=(-a)*7y=a*(-7)0 05. (a*(-b)4.(a*b)+1a*(b+1) 00 1 2 3 4 5 6 7 8Fig. 3. The complement edge transformationsFig. 4. The arithmetic node expansion algorithm exampleapplied for all variable assignment nodes. Starting from variable assignment node the procedure traces back to argument nodes. If the t variable of current node is not assigned than it is a subject of the t value calculation according to (4). If there is an argument node that t = -1 the procedure is called recursively for this node. If the graph adjacency matrix row contains more than two nonzero items than the node is subject of the expansion process. The node arguments count is used in practical EDFG implementation instead of adjacency matrix. Arguments pair with the smallest t value is selected for expansion. Selected arguments are reconnected to the newly created node. The new node is assigned t value according to (4) and becomes the argument of the node j (the expanded node). The expanded nodes are marked with grey colour in figures (Fig. 4.1 and Fig. 4.2). The node j expansion process is continued until number of arguments is equal to 2. There is a special case of expansion for addition nodes with a constant. An adder is able to perform addition of 2 bit vector arguments (a, b) and a single bit item (ci) applied to the carry in input. When the constant value c meet a requirement:y = a + b + ci : ci 0,1Where: e is a variable associated with input signal, d a variable associated with an output signal, p a read-write variable associated with internal signal, and read only variables (parameters of function).01234tFig. 5. The direct hardware mapping procedure: (1) An input EDFG, (2) The mapped circuit structure.The simplest method utilize a direct correspondence between hardware arithmetic primitives and respective nodes of an EDFG. The EDFG is directly mapped to respective arithmetic components that are separated with registers (shown as hatched rectangles). The direct mapping process bounds permanently each node with unique hardware resource. It has been shown schematically in the figure (Fig. 5.2). Thec 1(8)into single DSP48 unit. The next level of clustering merges operations with accumulative addition of result. The clustering operation improve the performance enabling0n = 11.COUTWhere: vs is the vector size, the LUT is the number of LUT generators. The LUT factor exhibits low sensitivity to changes during resource allocation procedure and hinders changes tracking. There was introduced a general multiplexing factor for variables and constants. It counts the number of inputs required for particular hardware resource and assigns value of 2 for variables and 1 for constant value. Finally the variable nodes are exchanged in order to minimize overall multiplexing costs in scheduled operations set.C 47:0D 17:0B 17:0A 17:0PCIND Q0D:A:BCED QCEFunction selectionZX CIND QP 17:0CEIn order to reduce argument multiplexing costs the use of distributed RAM (Fig. 6) is attempted. The problem of use a memory modules are also addressed in work (Coussy et al. 2008). Currently the ability of utilizing the distribute RAM is reduced to variables that implement processing parameters. The processing parameters are marked in the gray rectangles2. EDFG mapping patternFig. 7. The DSP48A simplified block diagram (1) and EDFG mapping pattern (2).1. DSP48 Cluster2. DSP48 Cluster3. DSP48 Clustercalculation for one cycle in order to propagate the arguments. Finally the (Fig. 8.3) shows the mixed addition and multiplication nodes mapping result. There are shown the successive unit reuse with pipelined processing utilization. The procedure attempts to fully utilize the unit without cycle stalls. FPGA TailADABAAOPFig. 8. The EDFG expansion procedure for DSP48A mapping.pipelined calculations. The mapping procedure requires declaring two constant values of 0 and 1 that enable bypassing adder and multiplier stages respectively.Lets consider the general expansion and mapping for addition and multiplication nodes. The expansion procedure starts from the assignment node and traces back to the argument nodes. The general properties of merged arithmetic node should be recalled. The node arguments set contains nodes with different operations. The identical operation precedes current node only if it is an argument of multiple nodes (cannot be merged). The mapping procedure recursively visits unassigned argument nodes. The set of nodes is ordered according to the calculation time with ASAP approach. If the node cycle identifier is not assigned than it is a subject of recursive evaluation. The DSP48 pattern is created with clustered nodes to which nodes are reconnected. The addition node with multiple arguments selects the pair of arguments with smaller cycle identifiers (possibly variable read nodes). They are reconnected to the DSP48 pattern as B and D arguments. If there are still unmapped arguments a new instance of DSP48 is created connected to the previous on in accumulative fashion. The B and D argument selection of the DSP48 unit is repeated. The operation is continued until all arguments of the addition node are assigned. The last mapping procedure holds the created DSP48 instance while tracing back to the map requesting node enables use of multiplier node.The multiplication node with multiple arguments mapping pattern is shown in (Fig. 8.2). It is a rear case in signal processing but general approach requires addressing this situation. The nodes with smallest ASAP time factor are selected. The operation is repeated iteratively by creating DSP48 clusters until all arguments are assigned to DSP48 clusters. It should be noticed that DSP48 defer the nextFig. 9. The DSP48A simplified block diagram (1) and EDFG mapping pattern (2).The Spartan6 device offers two block RAM cores next to each DSP48 unit. When memories are configured to the 18 bit data bus that matches width of the DSP48 block data path they are able to store 512 words. The memories content is initialized by configuration process that eliminates the implementation of this process reducing overall hardware overhead. The schematic diagram of calculation unit based on a DSP48 and respective block RAMs is shown in the figure (Fig. 9). Block RAMs operate in parallel creating a 3 arguments addressable register set for A, B and D inputs of the DSP48. The control unit is implemented with use of general purpose logic components. Its concept is based on a counter based control units with LUT based argument readdressing. The utilization of dedicated hardware resources and minimization of general purpose logic resources usage (LUTs and Flip-Flops) are fundamental advantages of the architecture. It can be noticed that even the smallest devices from the Spartan6 family (e.g. XC6SLX4) enables implementation of 8 arithmetic blocks with performance of 250 300MHz that results with a pick performance of 2.0 2.4 GMAC/s.4.4. Hardware mapping summaryThe Spartan 6 FPGAs offers a reach set of resources that are able to implement arithmetic calculations. In order to explain the differences the exemplary design of a PID controller has been implemented with presented strategies (Tab.1). It was obtained through generation of mapped design in Verilog HDL utilizing a specific components according to guidelines of XST synthesis tool (Xilinx, 2013). There are distinguished LUT generators operating as logic or memory components. DSP48 units utilization distinguish between a multiplier only usage and full unit utilization. In order to emphasize the differences in mapping there are considered one (1CH) and two independent instances (2CH) of the PID controller.The direct mapping strategy (DIR) is the simplest one. Usage of registers is dominant for storing all variables andTab. 1.Mapping strategies implementation result comparisonTypeMapalg.FFLUTDSP48fMAXMHztCTHMc/sLOGMEMMULALL1CHDIR297115-4-197.2728.1SHR189136-1-130.6718.6SDR11250181-180.3725.7D48D242872-1260.5832.5D48B2220-1302.91030.22CHDIR594230-8-185.3726.4SHR351175-1-128.41012.8SDR20486181-178.11017.8D48D283272-1239.81023.9D48B2223-1302.91421.6coefficients. The LUT utilization is acceptable. The next algorithm (SHR - shared) implements the resource sharing but revels the problem of additional cost of resource sharing. It introduces the calculation resources reduction but overall LUT resource utilization is higher than in the direct approach. Utilizing distributed RAMs (SDR shared with distributed RAM) allows for reduction of registers and multiplexing resources. Mentioned already mapping strategies are based on elementary arithmetic components. The DSP48 core is used as a multiplier only part. The DSP48 core mapping strategy enables full utilization of the core and further reduction of resource requirements. There are two methods of implementation differing with variables storage implementation. The D48D utilize DSP48 with distributed RAMs while D48B utilize the RAMB8 block memories. In both cases utilization of general purpose logic is significantly reduced. All arithmetic computation are implemented in DSP48 block. Finally the throughput (TH) expressed as number of fully processed samples per second should be analyzed. There can be observed a good performance of D48D method that gives the best trade-off between resource requirements and performance.5. SUMMARYThe paper presents entire synthesis process of a hardware implemented controller from an abstract description to hardware mapping. The paper recalls presented translation methods of PLC languages to the original intermediate form of the EDFG. The obtained structure represents entire control process that is subject of a hardware mapping. Finally the hardware mapping stages are presented. The mapping procedure starts with EDFG accommodation to hardware components. There are discussed a multiple argument node expansion problem that maximize parallel execution of the algorithm. The other problem that has been addressed is an adder optimization with use of the attributed edges. The hardware prepared EDFG is scheduled with two different approaches. The direct approach allows simple transformation into hardware structure. The hardware component reuse has been introduced in the second method that increase the hardware components utilization. Finally the DSP48 component mapping procedure is shown. The mapping procedure introduces mapping strategy that expands operation nodes into DSP48 patterns. The method takes benefits from the pipelined architecture and accumulative adder of the DSP48 unit.Presented algorithms belong to originally developed synthesis tool for a hardware implementation of LD, IL and SFC control programs. The compilation and synthesis tool is a subject of ongoing research and development. It is planned to extend arithmetic support to floating point numbers and further improvement of scheduling and mapping processes.REFERENCESCenelec (2013). EN 61131-3, Programmable Controller Part 3: Programming Languages, Intern. Standard, Management Centre, Avenue Marnix 17, Brussels.Chmiel M., Hrynkiewicz E. (2010) Concurrent operation of processors in the bit-byte CPU of a PLC. Control and Cybernetics. 2010 vol. 39 iss. 2, pp. 559-579Canis A., Choi J., Aldham M., Zhang V., Kammoona A., Anderson J.H., Brown S., Czajkowski T. LegUp: High- level synthesis for FPGA-based processor/accelerator systems, ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA), pp. 33-36, Monterey, CA, February 2011.Coussy P., Chavet C., Bomel P., Heller D., Senn E., Martin E.: GAUT: A High-Level Synthesis Tool for DSP Applications. From C Algorithm to RTL Architecture, Coussy P., Morawiec A. (eds.) High-Level Synthesis. From Algorithm to Digital Circuit, Springer Science + Busines Media 2008Czerwiski R., Kania D., (2013) Finite state machine logic synthesis for complex programmable logic devices. Springer, Berlin, 2013Du D., Xu X., Yamazaki K.(2010) A study on the generation of silicon-based hardware PLC by means of the direct conversion of the ladder diagram to circuit design language, The International Journal of Advanced Manufacturing Technology, Springer London, 2010, vol. 49, issue 5, pp.615-626David R. (1995) Grafcet: A powerful tool for specification of logic controllers, IEEE Transactions on Control Systems Technology, vol. 3(3), 1995, pp. 253-268.Deschamps J.P., Bioul G.J.A., Sutter G.D.: Synthesis of Arithmetic Circuits: FPGA, ASIC and Embedded Systems, John Wiley & Sons, 2006Economakos C.; Economakos G. (2008). FPGA implementation of PLC programs using automated high- level synthesis tools; IEEE International Symposium on Industrial Electronics, pp 1908 1913Economakos C.; Economakos G. (2012). C-based PLC to FPGA translation and implementation: The effects of coding styles, 16th International Conference on System Theory, Control and Computing, pp.1-6, 12-14 Oct. 2012 Gajski D., N Dutt., Wu A., Lin S., (1994) High-Le