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Intelligent traffic lightWith economic development, increased the number of vehicles, road congestion is becoming increasingly serious, intelligent traffic lights on the emerged. At present, the worlds Intelligent Transportation System will be: a huge structure, management difficulties, such as the maintenance of large inputs. In order to improve the existing traffic conditions, and to overcome the existing shortcomings of intelligent transportation system I designed analog control traffic lights in urban and rural areas of small-scale smart traffic lights. It has small size, intelligence, maintenance into small, easy to install and so on. And other intelligent transportation system compared to the system to adapt to economic and social development, in line with the current status of scientific and technological development.Intelligent traffic lights are a comprehensive use of computer network communication technology, sensor technology to manage the automatic control system of traffic lights. Urban traffic control system is used for urban traffic data monitoring, traffic signal control and traffic management computer system; it is the modern urban traffic control system command and the most important component. In short, how to use the appropriate control method to maximize the use of costly cities to build high-speed roads, trunk road and the ramp to alleviate urban areas with the neighboring state of traffic congestion has become more and more traffic management and urban planning departments need to address the main problem. To this end, this article on the urban traffic light control system analog circuit theory, design calculation and experimental testing and other issues to discuss specific analysis.The General Situation of AT89C51Microcontrollers are used in a multitude of commercial applications such as modems, motor-control systems, air conditioner control systems, automotive engine and among others. The high processing speed and enhanced peripheral set of these microcontrollers make them suitable for such high-speed. However, these critical application domains also require that these microcontrollers are highly reliable. The high reliability and low market risks can be ensured by a robust testing process and a proper tools environment for the validation of these microcontrollers both at the component and at the system level. Intel Platform Engineering department developed an object-oriented multi-threaded test environment for the validation of its AT89C51 automotive microcontrollers. The goals of this environment was not only to provide a robust testing environment for the AT89C51 automotive microcontrollers, but to develop an environment which can be easily extended and reused for the validation of several other future microcontrollers. The environment was developed in conjunction with Microsoft Foundation Classes (AT89C51). The paper describes the design and mechanism of this test environment, its interactions with various hardware/software environmental components, and how to use AT89C51.1.1 IntroductionThe 8-bit AT89C51 CHMOS microcontrollers are designed to handle high-speed calculations and fast input/output operations. MCS 51 microcontrollers are typically used for high-speed event control systems. Commercial applications include modems, motor-control systems, printers, photocopiers, air conditioner control systems, disk drives, and medical instruments. The automotive industry use MCS 51 microcontrollers in engine-control systems, airbags, suspension systems, and antilock braking systems (ABS). The AT89C51 is especially well suited to applications that benefit from its processing speed and enhanced on-chip peripheral functions set, such as automotive power-train control, vehicle dynamic suspension, antilock braking, and stability control applications. Because of these critical applications, the market requires a reliable cost-effective controller with a low interrupt latency needed in real time applications, and a CPU with above average processing power in a single package. The financial and legal risk of having devices that operate unpredictably is very high. Once in the market, particularly in mission critical applications such as an autopilot or anti-lock braking system, mistakes are financially prohibitive. Redesign costs can run as high as a $500K, much more if the fix means 2 back annotating it across a product family that share the same core and/or peripheral design flaw. In addition, field replacements of components are extremely expensive, as the devices are typically sealed in modules with a total value several times that of the component. To mitigate these problems, it is essential that comprehensive testing of the controllers be carried out at both the component level and system level under worst case environmental and voltage conditions. This complete and thorough validation necessitates not only a well-defined process but also a proper environment and tools to facilitate and execute the mission successfully. Intel Chandler Platform Engineering group provides post silicon system validation (SV) of various micro-controllers and processors. The system validation process can be broken into three major parts. The type of the device and its application requirements determine which types of testing are performed on the device.1.2 The AT89C51 provides the following standard features:4Kbytes of flash, 128 bytes of RAM, 32 I/O lines, two 16-bittimer/counters, a five vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator and clock circuitry. In addition, the AT89C51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt sys -tem to continue functioning. The Power-down Mode saves the RAM contents but freezes the oscillator disabling all other chip functions until the next hardware reset.1.3Pin DescriptionGND Ground.Port 0：Port 0 is an 8-bit open-drain bi-directional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high impedance inputs .Port 0 may also be configured to be the multiplexed low order address/data bus during accesses to external program and data memory. In this mode P0 has internal pull-ups. Port 0 also receives the code bytes during Flash programming, and outputs the code bytes during program verification. External pull-ups are required during program verification.Port 1：Port 1 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pull-ups. Port 1 also receives the low-order address bytes during Flash programming and verification.Port 2：Port 2 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pull-ups. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pull-ups. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that uses 16-bit addresses . In this application, it uses strong internal pull-ups when emitting 1s. During accesses to external data memory that uses 8-bit addresses, Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits and some control signals during Flash programming and verification. Output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the pull-ups. Port 3 also serves the functions of various special feature soft the AT89C51 as listed below:RST：Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device.ALE/PROG：Address Latch Enable output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming. In normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency, and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external Data Memory. If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.PSEN：Program Store Enable is the read strobe to external program memory. When the AT89C51 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory.EA/VPP：External Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped to VCC for internal program executions. This pin all receives the 12-volt programming enable voltage (VPP) during Flash programming, for parts that require 12-volt VPP. Chip erase The power to erase the entire Flash array, through the appropriate combination of control signals and by holding ALE / 10 ms compiled low. 1 written in code array chip erase operation must be performed before the code memory can be reprogrammed. Byte of each code in the flash memory array can be written, and the entire array can be erased through the appropriate combination of control signals. Write cycle is self-timed, and once started, will be automatically done. Information between the computer interface into a computer electronic system to process the information outside the two forms. There is a physical signal, it represents the value of the plan. Any interface functions can be divided into the number of operations that modify data in some way, the conversion process between the internal and external form of a number of steps. Analog digital converter for continuously variable signals into digital form, may be taken by a fixed binary value. If the discontinuous change in the output of the sensor, there is no ADC is necessary. In this case, the signal conditioning section must input signals into a direct connection to the part of the form next to the interface, input / output section of the output interface of the computer itself, takes a similar form, the obvious difference is that the information the flow in the opposite direction, it is through to the outside world, in this case, the program may call an output routine supervision and operator interface, and implementation ratio can be used for digital - analog converter digital . This subroutine in turn pass the information generated, it can be converted into a corresponding electrical signal output device using the DAC analog form. In the form of operating conditions of the last signal for the implementing agency. Almost always used in the microcomputer circuit signal is too small to connect directly to the outside world, you must use some kind of interface translation . they are a more appropriate form of interface circuit part of the design we have seen computer engineers who wish to apply for one of the most important task facing the form of this figure is only the most useful computer connected to the device can be turned on or off, in a discrete bit mode of the micro-computer, where each bit represents a switch or regulator in order to resolve the status of real-world problems, the microcontroller must be more than just a CPU, a program and data memory. in addition, it must include the hardware to allow the CPU to access information from the outside world. Once the CPU to gather information and processing data must be able to change on the outside of some parts of these hardware devices, peripherals, CPU outside the window.The peripheral micro-controller provides the most basic form is a general-purpose I70ports, each I /O pins can be used as input or output. The function of each pin is set or clear the corresponding bit data direction register in the appropriate decisions in the initialization phase of the program, each output pin to drive the CPU instructions used by the pin can be considered to use the program instructions the CPU (or read). Some type of logic 1 or logic 0. Communication function of the serial unit includes a Microcontroller , CPU and external devices to communicate serial format, instead of using bit parallel format and require less I / O pins, which makes it cheaper, but slower The serial transmission synchronous or asynchronous 黄河科技学院毕业设计（文献翻译） 第 5 页 智能交通灯简述随着经济的发展，车辆的数目不断增加，道路堵车现象日益严重，智能交通灯就应运而生了。目前世界上的智能交通系统存在的问题是：系统结构庞大、管理困难、维护投入大等。为了改善现有的交通状况，并克服现有智能交通系统的缺点我设计了城乡交通灯模拟控制小型化的智能交通灯。它具有小型化、智能化、维修投入小、易于安装等特点。与其他的智能交通系统相比该系统更适应经济和社会的发展，符合目前科技发展的现状。 智能交通灯是一项综合运用网络通讯计算机技术、感应技术来管理交通灯具的自动控制系统。城市交通控制系统是用于城市交通数据监测、交通信号灯控制与交通疏导的计算机综合管理系统，它是现代城市交通监控指挥系统中最重要的组成部分。总之，如何采用合适的控制方法，最大限度利用好耗费巨资修建的城市高速道路，缓解主干道与坡道、城区同周边地区的交通拥堵状况，越来越成为交通运输管理和城市规划部门亟待解决的主要问题。为此，本文就城乡交通灯模拟控制系统的电路原理、设计计算和实验调试等问题来进行具体分析讨论。 AT89C51 AT89C51概况 单片机控制器被用来在众多的商业应用，如调制解调器，电机控制系统，空调控制系统，汽车发动机和其他领域。高处理速度和增强型微控制器的外设集，使它们适合这样高速的基于事件的应用程序。然而，这些关键的应用领域也需要这些单片机控制器性能是高度可靠的。可确保高可靠性和低市场风险由一个强大的测试过程和一个适当的工具，为这些微控制器在组件和系统级验证环境。 Intel平台工程部门开发验证它的AT89C51的汽车微控制器面向对象多线程的测试环境。这种环境下的不仅为AT89C51的汽车微控制器提供一个宽广的测试环境，而且发展的环境可以很容易地扩展和其他几个未来的微控制器的验证重用。环境与Microsoft基础类（AT89C51）为共同发展。本文介绍了本次测试环境的设计和机制，与各种软/硬件环境组成部分的相互作用，以及如何使用AT89C51的。MCS - 51简介8位单片机AT89C51CHMOS微控制器的设计用于处理高速计算和快速输入/输出的操作。MCS - 51单片机通常用于高速事件控制系统。商业应用包括调制解调器，电机控制系统，打印机，复印机，空调控制系统，磁盘驱动器，医疗器械。汽车行业使用MCS 51单片机在发动机控制系统，安全气囊，悬架系统，防抱死制动系统（ABS）。 AT89C51从效益上特别适合于应用程序，其处理速度和增强型外设功能，如在汽车动力传动控制，车辆动态悬架，防抱死制动，稳定控制系统的应用。因为这些关键的应用，市场需要一个可靠的成本低的中断延迟响应，服务能力大的需要驱动时间和事件在实时应用中的集成外设，以及一个高于平均处理能力水平的CPU控制器的软件包。设备操作的财务和法律风险是很难预测的。一旦在市场上，尤其是在关键任务应用，如自动驾驶仪或防抱死制动系统的失误将使财政望而却步。为50万美元的设计成本可以运行高得多，如果修复意味着2回注释整个产品系列共享相同的核心和/或外围设备的设计缺陷。此外，更换零部件领域是极其昂贵的，因为这些设备通常是密封模块组件的几次，总价值。为了减轻这些问题，单片机控制器是必不可少的，同时在最坏情况下的环境和电压条件下的组件级和系统级进行全面的测试控制器。这种全面，彻底的验证，不仅需要一个定义良好的过程，也需要一个适当的环境和工具，以方便和成功地执行任务。英特尔钱德勒平台工程组提供各种微控制器和处理器后硅系统验证（SV）。系统验证过程可分为三个主要部分。设备的类型及其应用的要求，确定在哪些类型的测试设备上进行。窗体顶端AT89C51提供以下标准功能：4KB的闪存，128字节RAM，32 条I / O线，两个16位的定时器/计数器，一个两级五向量中断结构，一个完整的全双工串行口，片上振荡器和时钟电路。此外，AT89C51的静态逻辑运行可下降到零频率，并支持两种软件可选的节电模式。空闲模式时CPU停止工作，同时允许的RAM，定时器/计数器，串口和中断系统继续运行。掉电模式保存RAM的内容，但冻结振荡器，禁用所有其他芯片功能，直到下一次硬件复位。 1-3引脚描述 VCC电源电压。 GND接地。 端口0：端口0是一个8位漏极开路双向I / O端口。作为一个输出端口，每个引脚可以驱动8个TTL输入。当1写入端口0引脚，引脚可以用作高阻抗输入，为了在访问外部程序和数据存储器的地址/数据总线，这种模式下P0具有内部上拉电阻，端口0也可以被配置为低8位地址使用。端口0接收FLASH编程的代码字节期间，方案论证过程中输出代码字节。外部上拉的过程中需要核查程序。 端口1：端口1是一个8位双向内部上拉I / O端口。端口1的输出缓冲器可以吸收来自四个TTL的输入。当1写入端口1他们会被内部上拉拉高，并可以用作输入引脚。端口1，被外部拉低，因为低将会使电流源（IIL）引脚内部上拉。端口1还可以接收低地址字节的flash编程和校验。 端口2：端口2是一个8位双向内部上拉I / O的端口。端口2输出缓冲器可以吸收来自四个TTL的输入。当1写入端口2他们会被内部上拉拉高，并可以用作输入引脚。作为输入，端口2引脚在外部被拉低将源电流（IIL）由于内部上拉。端口2发出的高阶地址字节在从外部程序存储器获取和访问端口2引脚被外部拉低时，低源电流（IIL）由于内部上拉。在从外部程序存储器获取和访问外部数据存储器时，端口2排放高阶地址字节，使用16位地址（MOVX DPTR）