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1926 基于 单片机 抢答 设计

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1926_基于单片机的抢答器设计,1926,基于,单片机,抢答,设计

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黄河科技学院毕业设计（文献综述） 第 4 页基于单片机抢答器的设计一、前言为什么说信息技术时代，随着人们生活水平不断越高，对精神生活的要求也越来越高。在现代社会里。无论是学校、工厂、军队还是益智性电视节目,都会举办各种各样的智力竞赛。特别是在很多公开竞争场合要求有公正的竞争裁决，诸如证券、股票交易等，因此，单片机智能抢答器给人们提供了一个很好的选择，它是基于单片计算机设计和开发的一个实用性产品，根究该电路的特点，利用单片机芯片作为基础 ，与外部各种电路组合实现构成系统，利用单片机的定时器/计数器定时和记数的原理，将软、硬件有机地结合起来，使得系统能够正确地进行计时，同时使数码管能够正确地显示时间。，用4x4键盘来输入是选手需要加减进行分数的加减输入。主板上的6个数码显示，加几分的数，按确定键后分数值从I/O口P2传到计分器显示模块上再通过数码管驱动模块显示。近年来随着科技的飞速发展，单片机的应用正在不断深入，同时带动传统控制检测技术日益更新。在实时检测和自动控制的单片机应用系统中，单片机往往作为一个核心部件来使用，作为嵌入式控制系统的主体与核心，代替了传统的控制系统的常规电子线路。但仅单片机方面知识是不够的，还应根据具体硬件结构软硬件结合，加以完善。单片机智能抢答器是基于单片计算机设计和开发的一个实用性产品，随着当今社会的不断发展，促使人们学科学、学技术、学知识的手段多种多样。抢答器作为一种工具，已广泛应用于各种智力和知识竞赛场合。但抢答器的使用频率较低，且有的要么制作复杂，要么可靠性低，减少兴致。做为一个单位若专购一台抢答器虽然在经济上可以承受，但每年使用的次数极少，往往因长期存放使（电子器件的）抢答器损坏，再购置的麻烦和及时性就会影响活动的开展,因此设计了本抢答器。具体技术与显示原理将会在下面的论文中进行详细的论述。同时超大规模集成电路的开发运用，电子技术领域里出现了一系列崭新的器件、系统和技术手段，各种各样新型的电子器件纷纷问世。单片机的应用正在不断走向成熟，带动传统控制检测日新月异，这也在软件方面得到了体现。温州网创科技有限公司集抢答器，计分器，数显倒计时器全面整合，开发出了带分数显示型智力抢答器，被全国各地众多电视台选用。二、主题1、早期的抢答器在百度，Google等各种搜索工具里的搜索，或者查“抢答器”都能搜到大量的设计文档和有关的研究资料，以及在万方数据库，中国知网等各种数据库的检索，均能找到各种方式制作的简易抢答器。通过在井冈山师范学院学报（自然科学版）2000年11月第21卷第5期的查阅，介绍了一种比较早期的八路抢答器，基本使用数字电路的方法制作的。文中有“笔者根据这一要求，并根据74LS373八路锁存器的功能特点，用74LS373和其它几块常用的74LS系列数字集成电路设计出了一数码显示八路抢答器电路”。此外，在电子电路网（/soft/67270）中有“本八路抢答器设计使用方法非常简单，从上述工作原理可知，抢答前只需先将开关K置于2，然后再置于1，即可进行抢答 . 顺便提一下，由于当按钮开关AN0先按下时，数码管显示0，这与我们平时的编号习惯有点不同。本八路抢答器论文中关于原理的分析内容均为单片机教程网， 工作人员得出如有错误请指正。本设计元件选择:锁存器选用74LS373 八路锁存器，编码器用74LS148 三线编码器，数码显示驱动器用bcd码七段译码器74LS247与共阳极七段数码管搭配，控制电路由八输入与非门 74LS30和一个或门、一个非门构成，或门用74LS32二输入四或门，非门 74LS04六反相器”以及“用555芯片组成电路作信号发生器”。以上所述的都是早期的抢答器。以模拟电路、数字电路或者模拟电路与数字电路相结，功能比较简单，且成本也比较高，发生故障的可能性也比较高主要存在以下缺陷：传统的抢答器都是导线布线，受现场环境影响很大。显示方式简单，无法判断提前抢按按键的行为且不便于电路升级换代2、现代控制主体的核心基础单片机近年来随着科技的飞速发展，超大规模集成电路的开发运用，电子技术领域里出现了一系列崭新的器件、系统和技术手段，各种各样新型的电子器件纷纷问世。同时自从单片机出现后，它的应用正在不断走向成熟。抢答器的设计也因此越来越容易。在何立民.单片机应用技术大全.北京:北京航空航天大学出版社,1994中有“自从1971年出现了微处理器后不久，就出现单片机，但只是一位的单片机。1976年Inter公司推出了8位的MCS-48系列的单片机，为单片机的发展奠定了坚实的基础。到80年代末，世界各地已相继研制出大约50个系列300多个品种的单片机产品。继8位单片机之后，又出现了16位的单片机，随着INTEL i960系列特别是后来的ARM系列的广泛应用，32位单片机迅速取代16位单片机的高端地位，并且进入主流市场。而传统的8位单片机的性能也得到了飞速提高，处理能力比起80年代提高了数百倍。目前，高端的32位单片机主频已经超过300MHz，性能直追90年代中期的专用处理器，而普通的型号出厂价格跌落至1美元，最高端的型号也只有10美元。当代单片机系统已经不再只在裸机环境下开发和使用，大量专用的嵌入式操作系统被广泛应用在全系列的单片机上。而在作为掌上电脑和手机核心处理的高端单片机甚至可以直接使用专用的Windows和Linux操作系统。”由于计算机的普及和电子信息技术的迅猛发展,对智能抢答器有了更高的要求，如何有效的保证许多公开竞争场合裁决的公平，公正。单片机智能抢答器为之提供了条件和发展空间。建立一个价格适宜、智能化、自动化、数字化等特点的智能抢答器具有重要意义。 在刘瑞宁单片机通信技术与工程实践中阐述：应用于控制系统的单片机主要有8位与16位、32位三种。对于工业自动化控制中的单片机应用系统对单片机的要求侧重于中断系统，I/O口的数量与功能，内部存储器和寄存器A/D,D/A转换器件等。对于一般性控制系统来说，选择8位机基本可以满足要求。 本设计是以六路抢答为基本理念。考虑到依需设定限时回答的功能，故采用常用的8位51系列芯片AT89C51单片机，用于其主控部分与外围接口实现抢答系统，利用单片机的定时器/计数器定时和记数的原理，将软、硬件有机地结合起来，使得系统能够正确地进行计时，同时使数码管能够正确地显示时间。用开关做键盘输出，扬声器发生提示。同时系统能够实现：在抢答中，只有开始后抢答才有效，如果在开始抢答前抢答为无效；抢答限定时间和回答问题的时间可在1-99s设定；可以显示是哪位选手有效抢答和无效抢答，正确按键后有音乐提示；抢答时间和回答问题时间倒记时显示，满时后系统计时自动复位及主控强制复位；按键锁定，在有效状态下，按键无效非法。 在刘瑞宁单片机通信技术与工程实践中介绍如何有效编写串口通信程序。串口通信程序一般分查询与中断两种。查询简单可靠，但占用处理器资源，处理器利用率低。中断方式下，在发送接收数据的时候处理器可做其它工作，效率更高。因此本设计用锁存显示组号。三、总结展望2009年，抢答器作为一种电子产品，早已广泛应用于各种智力和知识竞赛场合，但目前所使用的抢答器有的电路较复杂不便于制作,可靠性低，实现起来很困难；有的则用一些专用的集成块 ,而专用集成块的购买又很困难。为适应高校等多代表队单位活动的需要而设计一个多功能抢答器，这种抢答器具有电路简单，元件普通 ,易于购买等优点,很好地解决了制作者制作困难和难于购买的问题。在国内外已经开始了普遍的应用。四、参考文献1 沈红卫.基于单片机的智能系统设计与实现M.北京：电子工业出版社,2005.1. 2 徐建军.MCS-51系列单片机应用及接口技术M.北京：人民邮电出版社,2003.63 何立民.单片机应用技术大全.北京:北京航空航天大学出版社,19944 何立民.MCS-51单片机应用系统设计系统配置与接口技术M.北京：航空航天大学5 楼然苗，李光飞51系列单片机设计实例北京：北京航空航天大学出版社，2004：24-35 6 张培仁基于C语言编程MCS-51单片机原理与应用北京：清华大学出版社，2003：159-163 7 Analog Device Corp.Data-Acquisition Databook,1991 8 Joseph D.Greenfield:Practical Digital Design Using ICs9 杨西明，朱骐.单片机编程与应用入门北京：机械工业出版社，2004：59-66 10 Protel电路设计实用指南 西安电子科技大学出版社 刘宏 赵杰忠等编11 张友德，赵志英，涂时亮单片微型机原理，应用与实践（第四版）上海：复旦大学出版社，2003：110-125 12 张延琪常用电子电路280例解析北京：中国电力出版社，2005：54-55 13 胡钢微机原理及应用北京：机械工业出版社，2001：50-5214 杨振江，杜铁军，李群流行单片机应用子程序及应用实例西安：西安电子科技大学出版社，2002：88-89 15 高吉祥，易凡电子技术基础实验与课程设计北京：电子工业出版社，2005：45-49黄河科技学院毕业设计(论文)文献翻译 第 11 页The General Situation of AT89C51 1 The application of AT89C51Microcontrollers are used in a multitude of commercial applications such as modems, motor-control systems, air conditioner control systems, automotive engine and among others. The high processing speed and enhanced peripheral set of these microcontrollers make them suitable for such high-speed event-based applications. However, these critical application domains also require that these microcontrollers are highly reliable. The high reliability and low market risks can be ensured by a robust testing process and a proper tools environment for the validation of these microcontrollers both at the component and at the system level. Intel Plaform Engineering department developed an object-oriented multi-threaded test environment for the validation of its AT89C51 automotive microcontrollers. The goals of thisenvironment was not only to provide a robust testing environment for the AT89C51 automotive microcontrollers, but to develop an environment which can be easily extended and reused for the validation of several other future microcontrollers. The environment was developed in conjunction with Microsoft Foundation Classes (AT89C51). The paper describes the design and mechanism of this test environment, its interactions with various hardware/software environmental components, and how to use AT89C51.1.1 IntroductionThe 8-bit AT89C51 CHMOS microcontrollers are designed to handle high-speedcalculations and fast input/output operations. MCS 51 microcontrollers are typically used for high-speed event control systems. Commercial applications include modems,motor-control systems, printers, photocopiers, air conditioner control systems, disk drives,and medical instruments. The automotive industry use MCS 51 microcontrollers in engine-control systems, airbags, suspension systems, and antilock braking systems (ABS). The AT89C51 is especially well suited to applications that benefit from its processing speed and enhanced on-chip peripheral functions set, such as automotive power-train control, vehicle dynamic suspension, antilock braking, and stability control applications. Because of these critical applications, the market requires a reliable cost-effective controller with a low interrupt latency response, ability to service the high number of time and event driven integrated peripherals needed in real time applications, and a CPU with above average processing power in a single package. The financial and legal risk of having devices that operate unpredictably is very high. Once in the market, particularly in mission criticalapplications such as an autopilot or anti-lock braking system, mistakes are financiallyprohibitive. Redesign costs can run as high as a $500K, much more if the fix means 2 back annotating it across a product family that share the same core and/or peripheral design flaw. In addition, field replacements of components is extremely expensive, as the devices are typically sealed in modules with a total value several times that of the component. To mitigate these problems, it is essential that comprehensive testing of the controllers be carried out at both the component level and system level under worst case environmental and voltage conditions.This complete and thorough validation necessitates not only a well-defined process but also a proper environment and tools to facilitate and execute the mission successfully.Intel Chandler Platform Engineering group provides post silicon system validation (SV) of various micro-controllers and processors. The system validation process can be broken into three major parts.The type of the device and its application requirements determine which types of testing are performed on the device.1.2 The AT89C51 provides the following standard features: 4Kbytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bittimer/counters, a five vector two-level interrupt architecture,a full duple ser -ial port, on-chip oscillator and clock circuitry.In addition, the AT89C51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters,serial port and interrupt sys -tem to continue functioning. The Power-down Mode saves the RAM contents but freezes the oscil lator disabling all other chip functions until the next hardware reset.Figure 1-2-1Block Diagram1-3Pin DescriptionThe 8-bit AT89C51 CHMOS microcontrollers are designed to handle high-speed calculations and fast input/output operations. MCS 51 microcontrollers are typically used for high-speed event control systems. Commercial applications include modems, motor-control systems, printers, photocopiers, air conditioner control systems, disk drives, and medical instruments. The automotive industry use MCS 51 microcontrollers in engine-control systems, airbags, suspension systems, and antilock braking systems (ABS). The AT89C51 is especially well suited to applications that benefit from its processing speed and enhanced on-chip peripheral functions set, such as automotive power-train control, vehicle dynamic suspension, antilock braking, and stability control applications. Because of these criticalapplications, the market requires a reliable cost-effective controller with a low interrupt latency response, ability to service the high number of time and event driven integrated peripherals needed in real time applications, and a CPU with above average processing power in a single package. The financial and legal risk of having devices that operate unpredictably is very high. Once in the market, particularly in mission critical applications such as an autopilot or anti-lock braking system, mistakes are financiallyprohibitive. Redesign costs can run as high as a $500K, much more if the fix means back annotating it across a product family that share the same core and/or peripheral design flaw. In addition, field replacements of components is extremely expensive, as the devices are typically sealed in modules with a total value several times that of the component. To mitigate these problems, it is essential that comprehensive testing of the controllers be carried out at both the component level and system level under worst case environmental and voltage conditions.This complete and thorough validation necessitates not only a well-defined process but also a proper environment and tools to facilitate and execute the mission successfully.Intel Chandler Platform Engineering group provides postsilicon system validation (SV) of various micro-controllers and processors. The system validation process can be broken into three major parts.The type of the device and its application requirements determine which types of testing are performed on the device.The AT89C51 provides the following standard features: 4Kbytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bittimer/counters, a five vector two-level interrupt architecture,a full duple ser -ial port, on-chip oscillator and clock circuitry.In addition, the AT89C51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters,serial port and interrupt sys -tem to continue functioning. The Power-down Mode saves the RAM contents but freezes the oscil -lator disabling all other chip functions until the next hardware reset.VCC Supply voltage.GND Ground.Port 0：Port 0 is an 8-bit open-drain bi-directional I/O port. As an output port, each pin cansink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as highimpedance inputs.Port 0 may also be configured to be the multiplexed loworder address/data busduring accesses to external program and data memory. In this mode P0 has internalpullups.Port 0 also receives the code bytes during Flash programming,and outputs the codebytes during program verification. External pullups are required during programverification.Port 1：Port 1 is an 8-bit bi-directional I/O port with internal pullups.The Port 1 output buffers can sink/so -urce four TTL inputs.When 1s are written to Port 1 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pullups.Port 1 also receives the low-order address bytes during Flash programming and verification.Port 2：Port 2 is an 8-bit bi-directional I/O port with internal pullups.The Port 2 outputbuffers can sink/source four TTL inputs.When 1s are written to Port 2 pins they arepulled high by the internal pullups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pullups. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pullups.Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVXDPTR). In this application, it uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX RI), Port 2 emits the contents of the P2 Special Function Register.Port 2 also receives the high-order address bits and some control signals durin Flash programming and verification.Port 3：Port 3 is an 8-bit bi-directional I/O port with internal pullups.The Port 3 outputbuffers can sink/sou -rce four TTL inputs.When 1s are written to Port 3 pins they are pulled high by the internal pullups and can be used as inputs. As inputs,Port 3 pins that are externally being pulled low will source current (IIL) because of the pullups.Port 3 also serves the functions of various special featuresof the AT89C51 as listed below:RST：Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device.ALE/PROG：Address Latch Enable output pulse for latching the low byte of the address duringaccesses to external memory.This pin is also the program pulse input (PROG) during Flash programming.In normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency,and may be used for external timing or clocking purposes. Note, however, that one ALEpulse is skipped duri -ng each access to external DataMemory.If desired, ALE operationcan be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active onlyduring a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Settingthe ALE-disable bit has no effect if the microcontroller is in external execution mode.PSEN：Program Store Enable is the read strobe to external program memory. When theAT89C51 is executing code from external program memory, PSEN is activated twiceeach machine cycle, except that two PSEN activations are skipped during each access toexternal data memory.EA/VPP：External Access Enable. EA must be strapped to GND in order to enable the deviceto fetch code from external program memory locations starting at 0000H up to FFFFH.Note, however, that if lock bit 1 is programmed, EA will be internally latched onreset.EA should be strapped to VCC for internal program executions. This pin alsreceives the 12-volt programming enable voltage (VPP) during Flash programming, forparts that require 12-volt VPP.XTAL1：Input to the inverting oscillator amplifier and input to the internal clock operatingcircuit.XTAL2 ：Output from the inverting oscillator amplifier.Oscillator CharacteristicsXTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifierwhich can be configured for use as an on-chip oscillator, as shown in Figure 1. Either aquartz crystal or ceramic resonator may be used. To drive the device from an externalclock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 2.There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time specifications must be observed. Idle Mode In idle mode, the CPU puts itself to sleep while all the onchip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset. It should be noted that when idle is terminated by a hard ware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory. Power-down ModeIn the power-down mode, the oscillator is stopped, and the instruction that invokes power-down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the power-down mode is terminated. The only exit from power-down is a hardware reset. Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize.The AT89C51 code memory array is programmed byte-bybyte in either programming mode. To program any nonblank byte in the on-chip Flash Memory, the entire memory must be erased using the Chip Erase Mode.2 Programming AlgorithmBefore programming the AT89C51, the address, data and control signals should be set up according to the Flash programming mode table and Figure 3 and Figure 4. To program the AT89C51, take the following steps.1. Input the desired memory location on the address lines.2. Input the appropriate data byte on the data lines. 3. Activate the correct combination of control signals. 4. Raise EA/VPP to 12V for the high-voltage programming mode. 5. Pulse ALE/PROG once to program a byte in the Flash array or the lock bits. The byte-write cycle is self-timed and typically takes no more than 1.5 ms. Repeat steps 1 through 5, changing the address and data for the entire array or until the end of the object file is reached. Data Polling: The AT89C51 features Data Polling to indicate the end of a write cycle. During a write cycle, an attempted read of the last byte written will result in the complement of the written datum on PO.7. Once the write cycle has been completed, true data are valid on all outputs, and the next cycle may begin. Data Polling may begin any time after a write cycle has been initiated. 2.1 Ready/Busy: The progress of byte programming can also be monitored by the RDY/BSY output signal. P3.4 is pulled low after ALE goes high during programming to indicate BUSY. P3.4 is pulled high again when programming is done to indicate READY.Program Verify: If lock bits LB1 and LB2 have not been programmed, the programmed code data can be read back via the address and data lines for verification. The lock bits cannot be verified directly. Verification of the lock bits is achieved by observing that their features are enabled. Figure 2-1-1 Programming the Flash Figure 2-2-2 Verifying the Flash2.2 Chip Erase: The entire Flash array is erased electrically by using the proper combination of control signals and by holding ALE/PROG low for 10 ms. The code array is written with all “1”s. The chip erase operation must be executed before the code memory can be re-programmed.2.3 Reading the Signature Bytes: The signature bytes are read by the same procedure as a normal verification of locations 030H, 031H, and 032H, except that P3.6 and P3.7 must be pulled to a logic low. The values returned areas follows.(030H) = 1EH indicates manufactured by Atmel(031H) = 51H indicates 89C51(032H) = FFH indicates 12V programming(032H) = 05H indicates 5V programming2.4 Programming InterfaceEvery code byte in the Flash array can be written and the entire array can be erased by using the appropriate combination of control signals. The write operation cycle is selftimed and once initiated, will automatically time itself to completion. A microcomputer interface converts information between two forms. Outside the microcomputer the information handled by an electronic system exists as a physical signal, but within the program, it is represented numerically. The function of any interface can be broken down into a number of operations which modify the data in some way, so that the process of conversion between the external and internal forms is carried out in a number of steps. An analog-to-digital converter(ADC) is used to convert a continuously variable signal to a corresponding digital form which can take any one of a fixed number of possible binary values. If the output of the transducer does not vary continuously, no ADC is necessary. In this case the signal conditioning section must convert the incoming signal to a form which can be connected directly to the next part of the interface, the input/output section of the microcomputer itself. Output interfaces take a similar form, the obvious difference being that here the flow of information is in the opposite direction; it is passed from the program to the ou