数字电压表的Verilog程序

/*/* TLC549控制程序/*module TLC549(clk,reset,sdata,cs,adc_clk,data_out);input clk,reset,sdata;output cs,adc_clk;output 7:0data_out;reg cs;reg 7:0data_out;reg 7:0data_out_r;reg 7:0count_clk;reg adc_clk_r;reg clk_r;reg mark; /标识八位数据reg flag ; /标识八位数据接收完 reg 3:0cnt;/标识八位数的个数parameter s0=0,s1=1,s2=2;reg 2:0c_st;reg5:0 temp; /1.4us 的计数assign adc_clk=adc_clk_r;/assign adc_clk_r=clk_r;always(posedge clk)begin if (count_clk119) count_clk=count_clk+1; else begin count_clk=0;clk_r=clk_r;end endalways(posedge clk)begin adc_clk_r=clk_r;endalways(posedge clk_r or negedge reset)begin if (!reset) c_st=s0; else case (c_st)s0:begin cs=1;mark=0; if (temp=3) begin c_st=s1;temp=0;end else begin temp=temp+1;c_st=s0;end ends1:begin cs=0;mark=1; c_st=s2; ends2:begin cs=0;mark=1; if(flag=1)c_st=s0;else c_st=s2; end default:c_st=s0;endcaseendalways(posedge adc_clk_r)begin if(mark=1) begin if(flag=1) data_out=data_out_r; else begin data_out_r=data_out_r6:0,sdata;end endendalways(posedge adc_clk_r)begin if(mark=1) begin if(cnt=8) begin cnt=0;flag=1;end else begin cnt=cnt+1;flag9)|(V13:0=8)&(V23:0=8)|(V13:0=9)&(V23:0=7)|(V13:0=7)&(V23:0=9) a=1; else a=0; if(V13:0+V23:0=9) b=1; else b=0; endalways(V1,V2,c_in,a) begin if(a=1&c_in=1&b=0) q3:0=V13:0+V23:0+7; else if(a=1&c_in=0&b=0) q3:0=V13:0+V23:0+6; else if(a=0&c_in=1&b=0) q3:0=V13:0+V23:0+1; else if(a=0&c_in=1&b=1)q3:0=V13:0+V23:0+7; else q3:0=V13:0+V23:0; endalways(a,V1,V2,c_in)begin if(a=1|(V13:0+V23:0=9&c_in=1) c_out=1; else c_out=0;endendmodule/*/* 数字转换查找表/*module lookup(V,q);input 7:0V;output 11:0q; reg 11:0q;reg 11:0HB,LB;wire d1,d2,d3;always(V)begin case(V7:4) /-A/D值的高4位转换成3位BCD码 4b1111: HB=12b001001000000; /-2.40 4b1110: HB=12b001000100100;/-2.24 4b1101: HB=12b001000001000;/-2.08 4b1100: HB=12b000110010010;/-1.92 4b1011: HB=12b000101110110;/-1.76 4b1010: HB=12b000101100000;/-1.60 4b1001: HB=12b000101000100;/-1.44 4b1000: HB=12b000100101000; /-1.28 4b0111: HB=12b000100010010;/-1.12 4b0110: HB=12b000010010110; / -0.96 4b0101: HB=12b000010000000; / -0.80 4b0100: HB=12b000001100100;/-0.64 4b0011: HB=12b000001001000;/-0.48 4b0010: HB=12b000000110010;/-0.32 4b0001: HB=12b000000010110;/-0.16 4b0000: HB=12b000000000000; / -0.00 default: HB=12b111111111111;endcase case(V3:0) /-A/D值低4位变为3位BCD码 4b1111: LB=12b000000010101; / -0.15 4b1110: LB=12b000000010100; /-0.14 4b1101: LB=12b000000010011; /-0.13 4b1100: LB=12b000000010010; /-0.12 4b1011: LB=12b000000010001; /-0.11 4b1010: LB=12b000000010000; /-0.10 4b1001: LB=12b000000001001; /-0.09 4b1000: LB=12b000000001000; /-0.08 4b0111: LB=12b000000000111; /-0.07 4b0110: LB=12b000000000110; /-0.06 4b0101: LB=12b000000000101; /-0.05 4b0100: LB=12b000000000100; /-0.04 4b0011: LB=12b000000000011; /-0.03 4b0010: LB=12b000000000010; /-0.02 4b0001: LB=12b000000000001; /-0.01 4b0000: LB=12b000000000000; / -0.00default: LB=12b111111111111;endcaseendcnt10 u1(.V1(LB3:0),.V2(HB3:0),.q(q3:0),.c_in(1b0),.c_out(d1);cnt10 u2(.V1(LB7:4),.V2(HB7:4),.q(q7:4),.c_in(d1),.c_out(d2);cnt10 u3(.V1(LB11:8),.V2(HB11:8),.q(q11:8),.c_in(d2),.c_out(d3);endmodule/*/* 译码显示电路/*module scan_led(clk_1k,d,dig,seg);/模块名scan_ledinput clk_1k;/输入时钟input11:0 d;/输入要显示的数据output7:0dig;/数码管选择输出引脚output7:0 seg;/数码管段输出引脚reg7:0 seg_r;/定义数码管输出寄存器reg7:0 dig_r;/定义数码管选择输出寄存器reg3:0 disp_dat;/定义显示数据寄存器reg2:0count;/定义计数寄存器assign dig = dig_r;/输出数码管选择assign seg = seg_r;/输出数码管译码结果always (posedge clk_1k) /定义上升沿触发进程begin if(count2)count = count + 1b1; else count=0;endalways (posedge clk_1k) begincase(count)/选择扫描显示数据3d0:disp_dat = d11:8; /第一个数码管3d1:disp_dat = d7:4;/第二个数码管3d2:disp_dat = d3:0;/第三个数码管endcasecase(count)/选择数码管显示位3d0:dig_r = 8b01111111;/选择第一个数码管显示3d1:dig_r = 8b10111111;/选择第二个数码管显示3d2:dig_r = 8b11011111;/选择第三个数码管显示endcase case(count) 3d0:seg_r7=0; 3d1:seg_r7=1; 3d2:seg_r7=1; endcaseendalways (disp_dat)begincase(disp_dat)/七段译码4h0:seg_r6:0 = 7b1000000;/显示04h1:seg_r6:0 = 7b1111001;/显示14h2:seg_r6:0 = 7b0100100;/显示24h3:seg_r6:0 = 7b0110000;/显示34h4:seg_r6:0 = 7b0011001;/显示44h5