计算机设计与实践——32位先行进位加法器PPT课件

.,32位先行进位加法器,VerilogHDL语言,.,32位超前进位加法器的进位是并行同时产生的，能够极大的减少加法器由进位引起的延时。增加了逻辑器件，但有效的减少的延迟。进位是由cla部件超前算出，本位是由不含进位的加法器算出。,.,VerilogHDL代码如下：modulealu_32(c2,f32,x32,y32,ciii);/32位加法器先行进位加法器input32:1x32;input32:1y32;inputciii;output32:1f32;outputc2;wirec1;wire2:1p;wire2:1g;alu_16alu_16_1(g1,p1,f3216:1,x3216:1,y3216:1,ciii);alu_16alu_16_2(g2,p2,f3232:17,x3232:17,y3232:17,c1);assignc1=g1|p1endmodule,.,modulealu_16(gmm,pmm,f16,x16,y16,cii);/16位加法器先行进位加法器input16:1x16;input16:1y16;inputcii;output16:1f16;outputgmm,pmm;wire4:1c;wire4:1p;wire4:1g;jiafaqi_4alu_4_1(g1,p1,f164:1,x164:1,y164:1,cii);jiafaqi_4alu_4_2(g2,p2,f168:5,x168:5,y168:5,c1);jiafaqi_4alu_4_3(g3,p3,f1612:9,x1612:9,y1612:9,c2);jiafaqi_4alu_4_4(g4,p4,f1616:13,x1616:13,y1616:13,c3);cla_4cl_4_1(c,p,g,cii);assignpmm=p4endmodule,.,modulejiafaqi_4(gm,pm,f,x,y,c0);/四位超前进位加法器input4:1x;/四位x值input4:1y;/四位y值output4:1f;/四位加和foutputgm,pm;inputc0;/上一的级进位wire3:1c;/超前进位wire4:1p;wire4:1g;assignp=x|y;assigng=xendmodule,.,modulejiafaqi_1(x,y,c0,f);/一位加法器模块inputx;inputy;inputc0;outputf;assignf=(xy)c0;endmodulemodulecla_4(c,p,g,c0);/4位CLA部件input4:1p;input4:1g;inputc0;output4:1c;assignc1=g1|p1endmodule,.,测试代码：moduletest;reg32:1x32;reg32:1y32;regciii;wirec2;wire32:1f32;alu_32uut(.c2(c2),.f32(f32),.x32(x32),.y32(y32),.ciii(ciii);,.,initialbeginx32=0;y32=0;ciii=0;#100;x32=32haaaaaaaa;y32=32h55555555;ciii=0;#100;x32=32haaaaaaaa;y32=32h55555555;ciii=1;#100;x32=32h00000011;y32=32