基于51单片机的电子数字钟设计的外文翻译

AT89C51 Family Users Guide1. Features Compatible with MCS-51 Products 4K Bytes of In-System Reprogrammable Flash Memory Endurance: 1,000 Write/Erase Cycles Fully Static Operation: 0 Hz to 24 MHz Three-level Program Memory Lock 128 x 8-bit Internal RAM 32 Programmable I/O Lines Two 16-bit Timer/Counters Six Interrupt Sources Programmable Serial Channel Low-power Idle and Power-down Modes2. DescriptionThe AT89C51 is a low-power, high-performance CMOS 8-bit microcomputer with 4K bytes of Flash programmable and erasable read only memory (PEROM). The device is manufactured using Atmels high-density nonvolatile memory technology and is compatible with the industry-standard MCS-51 instruction set and pin-out. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89C51 is a powerful microcomputer which provides a highly-flexible and cost-effective solution to many embedded control applications.3. Pin Configurations4. Lock DiagramThe AT89C51 provides the following standard features: 4K bytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bit timer/counters, a five vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator and clock circuitry. In addition, the AT89C51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt system to continue functioning. The Power-down Mode saves the RAM contents but freezes the oscillator disabling all other chip functions until the next hardware reset.5. Pin DescriptionVCC: Supply voltage.GND: Ground.Port 0:Port 0 is an 8-bit open-drain bi-directional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high-impedance inputs.Port 0 may also be configured to be the multiplexed low-order address/data bus during accesses to external program and data memory. In this mode P0 has internal pull-ups.Port 0 also receives the code bytes during Flash programming, and outputs the code bytes during program verification. External pull-ups are required during program verification.Port 1:Port 1 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pull-ups. Port 1 also receives the low-order address bytes during Flash programming and verification.Port 2:Port 2 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pull-ups. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that uses 16-bit addresses (MOVX DPTR). In this application, it uses strong internal pull-ups when emitting 1s. During accesses to external data memory that uses 8-bit addresses (MOVX RI), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits and some control signals during Flash programming and verification.Port 3:Port 3 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the pull-ups. Port 3 also serves the functions of various special features of the AT89C51 as listed below:Port PinAlternate FunctionsP3.0RXD(serial input port)P3.1TXD(serial output port)P3.2INT0(external interrupt 0)P3.3INT1(external interrupt 1)P3.4T0(timer 0 external input)P3.5T1(timer 1 external input)P3.6WR(external data memory write strobe)P3.7RD(external data memory read strobe)Port 3 also receives some control signals for Flash programming and verification.RST:Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device.ALE/:Address Latch Enable output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming. In normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency, and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external Data Memory. If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.:Program Store Enable is the read strobe to external program memory. When the AT89C51 is executing code from external program memory, is activated twice each machine cycle, except that two activations are skipped during each access to external data memory./VPP:External Access Enable. must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, will be internally latched on reset. should be strapped to VC C for internal program executions. This pin also receives the 12-volt programming enable voltage (VPP) during Flash programming, for parts that require 12-volt VPP.XTAL1:Input to the inverting oscillator amplifier and input to the internal clock operating circuit.XTAL2:Output from the inverting oscillator amplifier.6. Oscillator CharacteristicsXTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in Figure 1. Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 2. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time specifications must be observed.Oscillator ConnectionsNote: C1, C2 = 30 pF10 pF for Crystals= 40 pF10 pF for Ceramic ResonatorsExternal Clock Drive Configuration7. Idle ModeIn idle mode, the CPU puts itself to sleep while all the on-chip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset. It should be noted that when idle is terminated by a hard ware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory.8. Power-down ModeIn the power-down mode, the oscillator is stopped, and the instruction that invokes power-down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the power-down mode is terminated. The only exit from power-down is a hardware reset. Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize.9. Programming the FlashThe AT89C51 is normally shipped with the on-chip Flash memory array in the erased state (that is, contents = FFH) and ready to be programmed. The programming interface accepts either a high-voltage (12-volt) or a low-voltage (VCC) program enable signal. The low-voltage programming mode provides a convenient way to program the AT89C51 inside the users system, while the high-voltage programming mode is compatible with conventional third party Flash or EPROM programmers. The AT89C51 is shipped with either the high-voltage or low-voltage programming mode enabled. The respective top-side marking and device signature codes are listed in the following table.The AT89C51 code memory array is programmed byte-by-byte in either programming mode. To program any nonblank byte in the on-chip Flash Memory, the entire memory must be erased using the Chip Erase Mode.10. Flash Programming and Verification CharacteristicsTA = 0C to 70C, VCC = 5.010%Note: 1. Only used in 12-volt programming mode.11. DC CharacteristicsTA = -40C to 85C, VCC = 5.0V20% (unless otherwise noted)Notes: 1. under steady state (non-transient) conditions, IOL must be externally limited as follows:Maximum IOL per port pin: 10 mAMaximum IOL per 8-bit port: Port 0: 26 mAPorts 1, 2, 3: 15 mAMaximum total IOL for all output pins: 71 mAIf IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions.2.Minimum VCC for Power-down is 2V.12. External Program and Data Memory Characteristics13. External Program Memory Read Cycle14. External Data Memory Read Cycle15. External Data Memory Write Cycle16. External Clock Drive Waveforms17. External Clock Drive18. Serial Port Timing: Shift Register Mode Test Conditions(VCC = 5.0 V 20%; Load Capacitance = 80 pF)19. Shift Register Mode Timing Waveforms20. Ring Information21. Packaging InformationAT89C51系列用户指南1 主要性能参数MCS-51 产品指令系统完全兼容4k 字节可重擦写 Flash 闪速存储器-周期：1000次擦/写全静态操作：0Hz24MHz三级加密程序存储器1288 字节内部 RAM32个可编程 IO 口线2个 16 位定时计数器6个中断源可程串行UART 通道低功耗空闲和掉电模式2 功能特性概述AT89C51 是美国 ATMEL 公司生产的低电压，高性能 CMOS8 位单片机，片内含 4k bytes 的可反复擦写的只读程序存储器（PEROM）和 128 bytes 的随机存取数据存储器（RAM），器件采用 ATMEL 公司的高密度、非易失性存储技术生产，兼容标准 MCS-51 指令系统，片内置通用 8 位中央处理器（CPU）和 Flash 存储单元，功能强大 AT89C51 单片机可为您提供许多高性价比的应用场合，可灵活应用于各种控制领域。3 引脚配置4 方框图AT89C51 提供以下标准功能：4k 字节 Flash 闪速存储器，128 字节内部 RAM，32个 IO 口线，两个 16 位定时计数器，一个 5 向量两级中断结构，一个全双工串行通信口，片内振荡器及时钟电路。同时，AT89C51 可降至 0Hz 的静态逻辑操作，并支持两种软件可选的节电工作模式。空闲方式停止 CPU 的工作，但允许 RAM，定时计数器，串行通信口及中断系统继续工作。掉电方式保存 RAM 中的内容，但振荡器停止工作并禁止其它所有部件工作直到下一个硬件复位。5 引脚功能说明Vcc：电源电压GND：地P0 口：P0 口是一组 8 位漏极开路型双向 IO 口，也即地址数据总线复用口。作为输出口用时，每位能吸收电流的方式驱动 8个 TTL 逻辑门电路，对端口写“1”可作为高阻抗输入端用。在访问外部数据存储器或程序存储器时，这组口线分时转换地址（低 8 位）和数据总线复用，在访问期间激活内部上拉电阻。在Flash编程时，P0 口接收指令字节，而在程序校验时，输出指令字节，校验时，要求外接上拉电阻。P1 口：P1 是一个带内部上拉电阻的 8 位双向 IO 口，P1 的输出缓冲级可驱动（吸收或输出电流）4个 TTL 逻辑门电路。对端口写“1”，通过内部的上拉电阻把端口拉到高电平，此时可作输入口。作输入口使用时，因为内部存在上拉电阻，某个引脚被外部信号拉低时会输出一个电流（IIL）。Flash编程和程序校验期间，P1 接收低 8 位地址。P2 口：P2 是一个带有内部上拉电阻的 8 位双向 IO 口，P2 的输出缓冲级可驱动（吸收或输出电流）4个TTL 逻辑门电路。对端口写“1”，通过内部的上拉电阻把端口拉到高电平，此时可作输入口，作输入口使用时，因为内部存在上拉电阻，某个引脚被外部信号拉低时会输出一个电流（IIL）。在访问外部程序存储器或 16 位地址的外部数据存储器（例如执行 MOVXDPTR 指令）时，P2 口送出高 8 位地址数据。在访问 8 位地址的外部数据存储器（如执行 MOVXRI 指令）时，P2 口线上的内容（也即特殊功能寄存器（SFR）区中 R2 寄存器的内容），在整个访问期间不改变。Flash 编程或校验时，P2 亦接收高位地址和其它控制信号。P3 口：P3 口是一组带有内部上拉电阻的 8 位双向 IO 口。P3 口输出缓冲级可驱动（吸收或输出电流）4个TTL逻辑门电路。对 P3 口写入“1”时，它们被内部上拉电阻拉高并可作为输入端口。作输入端时，被外部拉低的 P3 口将用上拉电阻输出电流（IIL）。P3 口除了作为一般的 IO 口线外，更重要的用途是它的第二功能，如下表所示：端口引脚第二功能P3.0RXD（串行输入口）P3.1TXD（串行输出口）P3.2（外中断 0）P3.3（外中断 1）P3.4T0（定时计数器 0 外部输入）P3.5T1（定时计数器 1 外部输入）P3.6（外部数据存储器写选通）P3.7（外部数据存储器读选通）P3 口还接收一些用于 Flash 闪速存储器编程和程序校验的控制信号。RST：复位输入。当振荡器工作时，RST 引脚出现两个机器周期以上高电平将使单片机复位。ALE： 当访问外部程序存储器或数据存储器时，ALE（地址锁存允许）输出脉冲用于锁存地址的低8位字节。即使不访问外部存储器，ALE 仍以时钟振荡频率的 l6 输出固定的正脉冲信号，因此它可对外输出时钟或用于定时目的。要注意的是：每当访问外部数据存储器时将跳过一个 ALE 脉冲。对 Flash 存储器编程期间，该引脚还用于输入编程脉冲（PROG）。如有必要，可通过对特殊功能寄存器（SFR）区中的 8EH 单元的 DO 位置位，可禁止 ALE 操作。该位置位后，只有一条 MOVX 和 MOVC 指令 ALE 才会被激活。此外，该引脚会被微弱拉高，单片机执行外部程序时，应设置 ALE 无效。：程序储存允许（PSEN）输出是外部程序存储器的读选通信号，当 AT89C51 由外部程序存储器取指令（或数据）时，每个机器周期两次有效，即输出两个脉冲。在此期间，当访问外部数据存储器，这两次有效的信号不出现。VPP：外部访问允许。欲使 CPU 仅访问外部程序存储器（地址为 0000HFFFFH）， 端必须保持低电平（接地）。需注意的是：如果加密位 LB1 被编程，复位时内部会锁存 端状态。如 端为高电平（接 VCC 端），CPU 则执行内部程序存储器中的指令。Flash 存储器编程时，该引脚加上+12V 的编程允许电源 Vpp，当然这必须是该器件是使用 12V 编程电压 Vpp。XTAL1：振荡器反相放大器的及内部时钟发生器的输入端。XTAL2：振荡器反相放大器的输出端。6 时钟振荡器AT89C5l 中有一个用于构成内部振荡器的高增益反相放大器，引脚 XTAL1 和 XTAL2 分别是该放大器的输入端和输出端。这个放大器与作为反馈元件的片外石英晶体或陶瓷谐振器一起构成自激振荡器。接石英晶体（或陶瓷谐振器）及电容 C1、C2 接在放大器的反馈回路中构成并联振荡电路。对外接电容 C1、C2 虽然没有十分严格的要求，但电容容量的大小会轻微影响振荡频率的高低、振荡器工作的稳定性、起振的难易程序及温度稳定性，如果使用石英晶体，我们推荐电容使用 30pF10pF，而如使用陶瓷谐振器建议选择 40pF10F。用户也可以采用外部时钟。采用外部时钟的电路如图 5 右图所示。这种情况下，外部时钟脉冲接到 XTAL1 端，即内部时钟发生器的输入端，XTAL2 则悬空。内部振荡电路石英晶体时：C1，C230pF10pF陶瓷滤波器：C1，C240pF10pF外部时钟驱动电路7 空闲节电模式AT89C51有两种可用软件编程的省电模式，它们是空闲模式和掉电工作模式。这两种方式是控制专用寄存器PCON（即电源控制寄存器）中的 PD（PCON.1）和 IDL（PCON.0）位来实现的。PD 是掉电模式，当 PD=1 时，激活掉电工作模式，单片机进入掉电工作状态。IDL 是空闲等待方式，当 IDL=1，激活空闲工作模式，单片机进入睡眠状态。如需同时