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笔记本图纸点位广达图纸quanta da0ql4mb8e0 hasee a550-i3_W 笔记本 图纸 点位广达 quanta a550 i3

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1 2 3 4 5 6 7 8 01 QL4 (15.6W) BLOCK DIAGRAM 27MHz PCB STACK UP 8L Dis. & UMA HDMI CON PAGE 22 CPU A A DDRIII-SODIMM1 PAGE 12 DDRIII 800/1066 MT/s nVIDIA (40nm) Auburndale 35W Clarksfield 45W PCI-Express 16X 1333MT/s CFD only CRT PAGE 22 Switchable IC N10M-GE N10P-GE 128 Bit 969p DDRIII-SODIMM2 PAGE 13 DDRIII 800/1066 MT/s PAGE 32~33 1333MT/s CFD only PAGE 3~6 PAGE 41~42 LCD CONN PAGE 21 DMI LINK 32.768KHz 25MHz SATA0 150MB HDMI SATA - HDD CRT PAGE 31 LVDS SATA1 150MB B B SATA - CD-ROM PAGE 31 CLOCK GEN 9LRS3197 Mini PCI-E Card x2 Express Card x1 PCH PAGE 2 USB2.0 7,10,11 Ibex-M SATA5 150MB 8 9 6 0,1,2 E-SATA Webcam PAGE 21 USB2.0 Ports BlueTooth PAGE 24 RTS5159 PAGE 23 PAGE 30 PAGE 7~11 PAGE 24 X3 PCI-E X1 X1 X1 32.768KHz Mini PCI-E Card WWAN/TV PAGE 30 LAN Atheros PCIE-LAN AR8131(M) GagaLAN PAGE 26 Express Card C C PAGE 28 27 PAGE 27 Keyboard ENE KBC KB3926 C0 LPC Touch Pad PAGE Azalia 25MHz PAGE 29 Analog ALC272 RJ45 PAGE 26 ONFI PAGE 24 GMT G9931P1U SPI Braidwood PAGE 31 SPI PAGE 7 MDC CONN PAGE 26 FAN PAGE 28 PAGE 29 AUDIO Amplifier TPA6017A2 PAGE 25 D D Jack to Speaker PAGE 25 microphone Audio Jacks (Phone/ MIC) PAGE 24 PROJECT : QL4 Quanta Computer Inc. Document Number PAGE 24 Siiize Custom Rev E NB5 Block Diagram Date: Friiiday, October 09, 2009 Sheet 1 of 44 1 2 3 4 5 6 7 8 14.318MHz SYSTEM CHARGER(ISL6251AHAZ-T) PAGE 39 DDR III SMDDR_VTERM 1.5V/1.5VSUS(RT8207) PAGE 37 VGACORE(1.025V) RT8208A PAGE 36 CPU CORE ISL6288 PAGE 35 VCCP +1.1VTT(RT8208A) AND PCH 1.05V(RT8204) PAGE 34 SYSTEM POWER RT8206B PAGE 33 UMA GPU CORE (RT8152A) PAGE 32 LAYER 1 : TOP LAYER 2 : SGND LAYER 3 : IN1 LAYER 4 : VCC LAYER 5 : IN2 LAYER 6 : IN3 LAYER 7 : SGND2 LAYER 8 : BOT 1 2 3 4 5 6 7 8 02 CLOCK GENERATOR +3V R303 *10K/F_4 A A U19 +3V C451 4.7U/6.3V_6 4.7U/6.3V_6 CPU_SEL 1 23 CLK_BUF_BCLK_P [8] VDD_USB VDD_LCD VDD_SRC VDD_CPU VDD_REF CPU-0 CPU-0# 133 or 100 Mhz output to PCH 5 17 24 29 22 CLK_BUF_BCLK_N [8] C452 C454 C470 .1U/10V_4 .1U/10V_4 RTM875N- CPU-1 R306 10K/F_4 20 19 .1U/10V_4 .1U/10V_4 CPU-1# C469 C464 632-GRT .1U/10V_4 +VDDIO_CLK 96Mhz output for generate 48Mhz 3 CLK_BUF_DREFCLK [8] DOT96T_LPR 18 4 ( USB ) and 24 Mhz ( HDA )clk CLK_BUF_DREFCLK# [8] VDD_CPU_IO VDD_SRC_IO SDATA SCLK DOT96C_LPR 15 31 13 [8,12,13,27,30] CGDAT_SMB [8,12,13,27,30] CGCLK_SMB CLK_BUF_PCIE_3GPLL [8] SRC-1 SRC-1# 100Mhz output for DMI reference clk 32 14 CLK_BUF_PCIE_3GPLL# [8] R296 R300 10K/F_4 33_4 CPU_SEL 16 10 +3V CLK_BUF_DREFSSCLK [8] CPU_STOP# SATA CLK_ICH_14M C465 10P/50V_4 100Mhz output for SATA reference clk 30 11 [8] CLK_ICH_14M CLK_BUF_DREFSSCLK# [8] REF_0/CPU_SEL SATA# CK_PWRGD_R CLK_VGA_27M_NOSS R308 33_4 33_4 25 6 CLK_27M_NONSS [16] CK_PWRGD/PD#_3.3 27MHz_nonSS 27MHz_SS CLK_VGA_27M_SS R309 7 CLK_27M_SS [16] Place the 33 ohm resistors close to the CK 505 XTAL_OUT XTAL_IN 27 XOUT XIN VSS_SATA VSS_USB VSS_LCD QFN32 Discrete and Hybrid 28 33 GND VSS_REF VSS_CPU VSS_SRC 9 2 8 26 21 12 +3V RTM875N-632-GRT B B R295 1K/F_4 CK_PWRGD_R Y3 XTAL_IN 2XTAL_OUT 1 Q10 2N7002E 14.3 R297 100K/F_4 C461 33P/50V_4 C457 33P/50V_4 2 [37] VR_PWRGD_CLKEN# PAD and HOLE MINI CARD Hole. MDC Hole. CPU bracket Hole. C C EMI solution. B-stage change B-stage change VGA bracket Hole. PAD2 1 PAD1 1 PAD3 PAD4 PAD5 D D 1 1 1 MDC_SPRING MDC_SPRING *EMI_PAD *EMI_PAD *EMI_PAD PROJECT : QL4 Quanta Computer Inc. Document Number PAD6 PAD7 PAD8 1 1 1 B-stage change *EMI_PAD *EMI_PAD *EMI_PAD Siiize Custom Rev E NB5 CLOCK & Screw Holes [7,8,9,11,29,34,36,42] +1.05V [3,7,8,9,10,11,12,13,21,22,23,24,25,26,27,28,29,30,31,32,33,37,40,42] +3V Date: Friiiday, October 09, 2009 Sheet 2 of 44 1 2 3 4 5 6 7 8 H19 h-tc146bc256d146p2 H21 h-tc146bc256d146p2 H29 h-tc67bc276d67p2 H33 *emiipad236x591b H27 H-TC161BC276D161P2 H20 *H-TC161BC276D161P2 H30 H-TC161BC276D161P2 H32 *emiipade472x1220 H26 h-tc67bc276d67p2 H28 *h-tc67bc276d67p2 H31 *EMIPAD236X591B H14 *O-O236X669D236X669N H18 *H-tC130bc197d130pb H24 *H-TC130BC197D130PB H16 *h-c315d106p2 H15 *h-c315d106p2 H3 *H-C315D130P2 H25 *H-C315D106P2 H22 *h-qll4-3 H9 *h-qll4-2 H2 *h-c315d106p2 H4 *H-C315D106P2 H7 *h-c315d106p2 H23 *h-c315d106p2 H1 *h-qll4-1 H17 *h-tc421x335bc315d106p2 H11 *h-tc295bc220d161p2 H13 *h-tc295bc220d161p2 H10 *h-tc295bc220d161p2 H12 *h-tc295bc220d161p2 H6 *h-tc295bc220d161p2 H5 *h-tc295bc220d161p2 H8 *h-tc295bc220d161p2 1 1 1 1 1 1 1 1 3 1 1 1 1 1 1 2 1 1 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 C773 .1U/25V_4 +VIN 1 2 C966 .1U/25V_4 +VIN 1 2 LAN_AGND1 R796 0_4 18MHZ 0 1 CPU_SEL CPU0/1=133MHz (default) CPU0/1=100MHz C471 +1.05V +VDDIO_CLK L23 1 2 HCB1608KF-181T15_6 C459 .1U/10V_4 C453 C450 C458 Place each 0.1uF cap as close as possible to each VDD IO pin. Place the 10uF caps on the VDD_IO plane. .1U/10V_4 10U/6.3V_6S 10U/6.3V_6S 1 2 3 4 5 6 7 8 DIS NA UMA 0 ohm 03 C297 470P/50V_4 C298 Ra CPU_PLTRST# Rb 0 ohm NA 470P/50V_4 HWPG Rc 0 ohm NA U29A B26 PEG_COMP R385 49.9/F_4 PEG_ICOMPI PEG_ICOMPO PEG_RCOMPO PEG_RBIAS PEG_RX#[0] PEG_RX#[1] PEG_RX#[2] PEG_RX#[3] PEG_RX#[4] PEG_RX#[5] PEG_RX#[6] PEG_RX#[7] PEG_RX#[8] PEG_RX#[9] PEG_RX#[10] PEG_RX#[11] PEG_RX#[12] PEG_RX#[13] PEG_RX#[14] PEG_RX#[15] A26 A24 B27 PEG_RBIAS R384 U29B For ITP CLk [9] DMI_TXN0 [9] DMI_TXN1 [9] DMI_TXN2 [9] DMI_TXN3 [9] DMI_TXP0 [9] DMI_TXP1 [9] DMI_TXP2 [9] DMI_TXP3 DMI_RX#[0] DMI_RX#[1] DMI_RX#[2] DMI_RX#[3] DMI_RX[0] DMI_RX[1] DMI_RX[2] DMI_RX[3] C23 A25 750/F_4 R125 R124 20/F_4 H_COMP3 AT23 A16 B16 COMP3 COMP2 COMP1 BCLK BCLK# CLK_CPU_BCLK [10] CLK_CPU_BCLK# [10] B22 20/F_4 H_COMP2 AT24 PV 0616 DEL debug Con. PEG_RX#[0..15] [14] PEG_RX#0 A21 K35 R29 49.9/F_4 H_COMP1 G16 MISC A A J34 PEG_RX#1 3 49.9/F_4 H_COMP0 AT26 AR30 AT30 COMP0 SKTOCC# BCLK_ITP BCLK_ITP# PEG_RX#2 B24 J33 AH24 CLK_PCIE_3GPLL [8] PEG_RX#3 D23 G35 CLK_PCIE_3GPLL# [8] PEG_RX#4 B23 G32 CLOCKS PEG_CLK E16 Rc PEG_RX#5 H_CATERR# AK14 AT15 R386 0_4 A22 F34 D16 CATERR# PECI PEG_CLK# F31 PEG_RX#6 Ra [10] H_PECI PEG_RX#7 THERMAL R383 3 *0_4P2R D24 DMI D35 AN26 A18 4 [9] DMI_RXN0 [9] DMI_RXN1 [9] DMI_RXN2 [9] DMI_RXN3 [37] H_PROCHOT# DREFSSCLK [8] DMI_TX#[0] DMI_TX#[1] DMI_TX#[2] DMI_TX#[3] PROCHOT# DPLL_REF_SSCLK E33 PEG_RX#8 C33 PEG_RX#9 G24 AK15 A17 1 2 [10,29] PM_THRMTRIP# DREFSSCLK# [8] THERMTRIP# DPLL_REF_SSCLK# F23 Rb D32 PEG_RX#10 PV 0616 DEL debug Con. R381 0_4 H23 B32 PEG_RX#11 C31 PEG_RX#12 B28 PEG_RX#13 B30 PEG_RX#14 A31 PEG_RX#15 AP26 F6 DDR3_DRAMRST# [12] 100/F_4 24.9/F_4 130/F_4 RESET_OBS# PM_SYNC VCCPWRGOOD_1 VCCPWRGOOD_0 SM_DRAMPWROK SM_DRAMRST# DDR3 SM_RCOMP[0] D25 AL15 [9] DMI_RXP0 [9] DMI_RXP1 [9] DMI_RXP2 [9] DMI_RXP3 [9] PM_SYNC DMI_TX[0] DMI_TX[1] DMI_TX[2] DMI_TX[3] AL1 SM_RCOMP_0 R87 AM1 SM_RCOMP_1 R92 F24 AN14 E23 AN27 [10] H_PWRGOOD MISC SM_RCOMP[1] SM_RCOMP[2] AN1 SM_RCOMP_2 R88 R121 AN15 PM_EXT_TS#0 R120 G23 AK13 [9] PM_DRAM_PWRGD 10K/F_4 0_4 PEG_RX[0..15] [14] +1.1V_VTT PEG_RX0 J35 AM26 PM_EXTTS#0 [12,13] PEG_RX[0] PEG_RX[1] PEG_RX[2] PEG_RX[3] PEG_RX[4] PEG_RX[5] PEG_RX[6] PEG_RX[7] PEG_RX[8] PEG_RX[9] PEG_RX[10] PEG_RX[11] PEG_RX[12] PEG_RX[13] PEG_RX[14] TAPPWRGOOD PM_EXT_TS#[0] H34 PEG_RX1 AP15 PM_EXT_TS#1 R114 R119 2.7GT/s data rate 0_4 10K/F_4 PM_EXTTS#1 [13] PM_EXT_TS#[1] H33 PEG_RX2 F35 PEG_RX3 G33 PEG_RX4 E34 PEG_RX5 H_VTTPWRGD AM15 CPU_PLTRST# AL14 [9] FDI_TXN[7:0] +1.1V_VTT VTTPWRGOOD RSTIN# FDI_TXN0 E22 [8,14,26,27,29,30,32] PLTRST# FDI_TX#[0] FDI_TX#[1] FDI_TX#[2] FDI_TX#[3] FDI_TX#[4] FDI_TX#[5] FDI_TX#[6] FDI_TX#[7] FDI_TXN1 D21 R110 AT28 PRDY# FDI_TXN2 D19 XDP_PREQ# XDP_TCLK PV 0616 DEL debug Con. AP27 PREQ# TCK FDI_TXN3 D18 FDI_TXN4 G21 F32 PEG_RX6 D34 PEG_RX7 F33 PEG_RX8 B33 PEG_RX9 D31 PEG_RX10 R109 750/F_4 PWR MANAGEMENT AN28 T1 FDI_TXN5 E19 AP28 XDP_TMS T2 TMS FDI_TXN6 F21 FDI_TXN7 G18 JTAG & BPM AT27 XDP_TRST# T3 TRST# A32 PEG_RX11 AJ22 BPM#[0] C30 PEG_RX12 A28 PEG_RX13 B29 PEG_RX14 A30 PEG_RX15 PV 0616 DEL debug Con. AK22 AT29 XDP_TDI_R B [9] FDI_TXP[7:0] T21 B BPM#[1] TDI FDI_TXP0 D22 XDP_TDO_R AK24 AR27 FDI_TX[0] FDI_TX[1] BPM#[2] TDO T18 FDI_TXP1 XDP_TDI_M XDP_TDO_M C21 AJ24 AR29 BPM#[3] TDI_M T20 FDI_TXP2 D20 AJ25 AP29 T19 FDI_TX[2] FDI_TX[3] PEG_RX[15] BPM#[4] TDO_M FDI_TXP3 C18 AH22 PEG_TX#[0..15] [14] BPM#[5] FDI_TXP4 G22 C_PEG_TX#0 C587 .1U/10V_4 PEG_TX#0 .1U/10V_4 PEG_TX#1 L33 AK23 FDI_TX[4] PEG_TX#[0] BPM#[6] FDI_TXP5 E20 M35 C_PEG_TX#1 C585 AH23 AN25 XDP_DBRESET# [9] FDI_TX[5] PEG_TX#[1] BPM#[7] DBR# FDI_TXP6 C_PEG_TX#2 .1U/10V_4 PEG_TX#2 .1U/10V_4 PEG_TX#3 F20 M33 C578 FDI_TX[6] PEG_TX#[2] FDI_TXP7 G19 IC,AUB_CFD_rPGA,R1P0 M30 C_PEG_TX#3 C572 FDI_TX[7] PEG_TX#[3] .1U/10V_4 PEG_TX#4 .1U/10V_4 PEG_TX#5 L31 C_PEG_TX#4 C571 PEG_TX#[4] PEG_TX#[5] PEG_TX#[6] PEG_TX#[7] PEG_TX#[8] PEG_TX#[9] PEG_TX#[10] F17 K32 C_PEG_TX#5 C569 [9] FDI_FSYNC0 [9] FDI_FSYNC1 [9] FDI_INT FDI_FSYNC[0] FDI_FSYNC[1] M29 C_PEG_TX#6 C568 .1U/10V_4 PEG_TX#6 .1U/10V_4 PEG_TX#7 .1U/10V_4 PEG_TX#8 E17 C_PEG_TX#7 C565 C_PEG_TX#8 C561 J31 C17 K29 FDI_INT C_PEG_TX#9 .1U/10V_4 PEG_TX#9 .1U/10V_4 PEG_TX#10 H30 C560 H29 C_PEG_TX#10 C559 F18 [9] FDI_LSYNC0 FDI_LSYNC[0] F29 C_PEG_TX#11 C557 E28 C_PEG_TX#12 C555 D29 C_PEG_TX#13 C552 .1U/10V_4 PEG_TX#11 .1U/10V_4 PEG_TX#12 .1U/10V_4 PEG_TX#13 .1U/10V_4 PEG_TX#14 .1U/10V_4 PEG_TX#15 D17 [9] FDI_LSYNC1 FDI_LSYNC[1] PEG_TX#[11] PEG_TX#[12] PEG_TX#[13] PEG_TX#[14] PEG_TX#[15] D27 C_PEG_TX#14 C550 C26 C_PEG_TX#15 C549 +1.1V_VTT JTAG MAPPING PEG_TX[0..15] [14] L34 C_PEG_TX0 C588 .1U/10V_4 PEG_TX0 .1U/10V_4 PEG_TX1 XDP_TDO_R R201 H_CATERR# R77 51_4 49.9/F_4 PEG_TX[0] PEG_TX[1] PEG_TX[2] PEG_TX[3] PEG_TX[4] PEG_TX[5] PEG_TX[6] PEG_TX[7] PEG_TX[8] PEG_TX[9] PEG_TX[10] PEG_TX[11] PEG_TX[12] PEG_TX[13] PEG_TX[14] PEG_TX[15] C_PEG_TX1 C583 M34 M32 C_PEG_TX2 C577 .1U/10V_4 PEG_TX2 .1U/10V_4 PEG_TX3 H_PROCHOT# R76 CPU_PLTRST# R111 68_4 *68 L30 C_PEG_TX3 C570 PV 0616 DEL debug Con. *51 *51 *51 C_PEG_TX4 C_PEG_TX5 .1U/10V_4 PEG_TX4 .1U/10V_4 PEG_TX5 .1U/10V_4 PEG_TX6 .1U/10V_4 PEG_TX7 XDP_TMS R116 XDP_TDI_R R451 M31 C573 C567 K31 XDP_PREQ# R136 M28 C_PEG_TX6 C566 H31 C_PEG_TX7 C564 C C .1U/10V_4 PEG_TX8 .1U/10V_4 PEG_TX9 .1U/10V_4 PEG_TX10 .1U/10V_4 PEG_TX11 XDP_TCLK R112 *51 K28 C_PEG_TX8 C563 G30 C_PEG_TX9 C562 G29 C_PEG_TX10 C558 F28 C_PEG_TX11 C556 E27 C_PEG_TX12 C553 .1U/10V_4 PEG_TX12 .1U/10V_4 PEG_TX13 .1U/10V_4 PEG_TX14 .1U/10V_4 PEG_TX15 D28 C_PEG_TX13 C554 +3V C27 C_PEG_TX14 C551 C25 C_PEG_TX15 C548 51_4 XDP_TRST# R129 U14 IC,AUB_CFD_rPGA,R1P0 R162 MC74VHC1G08DFT2G 2 H_VTTPWRGD 4 1 [21,29,34,35,36,38,39] HWPG 2K/F_4 R163 1K/F_4 +3VPCU R148 3K/F_4 DRAM_PWG3 R185 1K/F_4 DRAM_PWG1 Q76 MMBT3904-7-F 2 +1.5VSUS_CPU +1.5VSUS_CPU 1.5K/F_4 DRAM_PWG4 R80 976/F_4 D D R250 1K/F_4 1.1V DRAM_PWG2 2 Q78 MMBT3904-7-F 1 3 PM_DRAM_PWRGD +1.1V_VTT Q77 DTC144EUA R79 3K/F_4 Use a voltage divider with VDDQ (1.5V) rail (ON in S3) and resistor combination of 4.75K (to VDDQ)/12K(to GND) to generate the required voltage. Note: CRB uses a 3.3V (always ON) rail with 2K and 1K combination. PROJECT : QL4 Quanta Computer Inc. Document Number R63 3K/F_4 Siiize Custom Rev E [5,10,11,34,38] +1.1V_VTT [5,12,13,39,40,42] +1.5VSUS [2,7,8,9,10,11,12,13,21,22,23,24,25,26,27,28,29,30,31,32,33,37,40,42] +3V NB5 PROCESSER 1/4(HOST&PEX) Date: Friiiday, October 09, 2009 Sheet 3 of 44 1 2 3 4 5 6 7 8 Intel(R) FDI PCI EXPRESS -- GRAPHICS 1 3 1 3 2 3 5 R252 Scan Chain (Default) STUFF -> R97, R89, R90 NO STUFF -> R84, R512 CPU Only STUFF -> R97, R84 NO STUFF -> R89, R512, R90 GMCH Only STUFF -> R512, R90 NO STUFF -> R97, R84, R89 1.5K/F_4 PV 0616 DEL debug Con. R12 1 2 3 4 5 6 7 8 04 AUBURNDALE/CLARKSFIELDPROCESSOR (DDR3) [13] M_B_DQ[63:0] A A U29C U29D [12] M_A_DQ[63:0] M_A_DQ0 M_A_DQ1 M_B_DQ0 M_B_DQ1 A10 AA6 B5 W8 M_A_CLK0 [12] M_A_CLK0# [12] M_A_CKE0 [12] M_B_CLK0 [13] M_B_CLK0# [13] M_B_CKE0 [13] SA_DQ[0] SA_DQ[1] SA_DQ[2] SA_DQ[3] SA_DQ[4] SA_DQ[5] SA_DQ[6] SA_DQ[7] SA_DQ[8] SA_DQ[9] SA_DQ[10] SA_DQ[11] SA_DQ[12] SA_DQ[13] SA_DQ[14] SA_DQ[15] SA_DQ[16] SA_DQ[17] SA_DQ[18] SA_DQ[19] SA_DQ[20] SA_DQ[21] SA_DQ[22] SA_DQ[23] SA_DQ[24] SA_DQ[25] SA_DQ[26] SA_DQ[27] SA_DQ[28] SA_DQ[29] SA_DQ[30] SA_DQ[31] SA_DQ[32] SA_DQ[33] SA_DQ[34] SA_DQ[35] SA_DQ[36] SA_DQ[37] SA_DQ[38] SA_DQ[39] SA_DQ[40] SA_DQ[41] SA_DQ[42] SA_DQ[43] SA_DQ[44] SA_DQ[45] SA_DQ[46] SA_DQ[47] SA_DQ[48] SA_DQ[49] SA_DQ[50] SA_DQ[51] SA_DQ[52] SA_DQ[53] SA_DQ[54] SA_DQ[55] SA_DQ[56] SA_DQ[57] SA_DQ[58] SA_DQ[59] SA_DQ[60] SA_DQ[61] SA_DQ[62] SA_DQ[63] SA_CK[0] SA_CK#[0] SA_CKE[0] SB_DQ[0] SB_DQ[1] SB_DQ[2] SB_DQ[3] SB_DQ[4] SB_DQ[5] SB_DQ[6] SB_DQ[7] SB_DQ[8] SB_DQ[9] SB_DQ[10] SB_DQ[11] SB_DQ[12] SB_DQ[13] SB_DQ[14] SB_DQ[15] SB_DQ[16] SB_DQ[17] SB_DQ[18] SB_DQ[19] SB_DQ[20] SB_DQ[21] SB_DQ[22] SB_DQ[23] SB_DQ[24] SB_DQ[25] SB_DQ[26] SB_DQ[27] SB_DQ[28] SB_DQ[29] SB_DQ[30] SB_DQ[31] SB_DQ[32] SB_CK[0] SB_CK#[0] SB_CKE[0] C10 AA7 A5 W9 M_A_DQ2 M_A_DQ3 M_B_DQ2 M_B_DQ3 C7 P7 C3 M3 A7 B3 M_A_DQ4 M_A_DQ5 M_B_DQ4 M_B_DQ5 B10 Y6 E4 V7 M_A_CLK1 [12] M_A_CLK1# [12] M_A_CKE1 [12] M_B_CLK1 [13] M_B_CLK1# [13] M_B_CKE1 [13] SA_CK[1] SA_CK#[1] SA_CKE[1] SB_CK[1] SB_CK#[1] SB_CKE[1] D10 Y5 A6 V6 M_A_DQ6 M_A_DQ7 M_B_DQ6 M_B_DQ7 E10 P6 A4 M2 A8 C4 M_A_DQ8 M_A_DQ9 M_B_DQ8 M_B_DQ9 D8 AE2 D1 AB8 M_A_CS#0 [12] M_A_CS#1 [12] M_B_CS#0 [13] M_B_CS#1 [13] SA_CS#[0] SA_CS#[1] SB_CS#[0] SB_CS#[1] F10 AE8 D2 AD6 M_A_DQ10 M_A_DQ11 M_B_DQ10 M_B_DQ11 E6 F2 F7 AD8 F1 AC7 M_A_ODT0 [12] M_A_ODT1 [12] M_A_DM[7:0] [12] M_B_ODT0 [13] M_B_ODT1 [13] M_B_DM[7:0] [13] SA_ODT[0] SA_ODT[1] SB_ODT[0] SB_ODT[1] M_A_DQ12 M_A_DQ13 M_B_DQ12 M_B_DQ13 E9 AF9 C2 AD1 B7 F5 M_A_DQ14 M_A_DQ15 M_A_DM0 M_A_DM1 M_B_DQ14 M_B_DQ15 M_B_DM0 M_B_DM1 E7 B9 F3 D4 SA_DM[0] SA_DM[1] SA_DM[2] SA_DM[3] SA_DM[4] SA_DM[5] SA_DM[6] SA_DM[7] SB_DM[0] SB_DM[1] SB_DM[2] SB_DM[3] SB_DM[4] SB_DM[5] SB_DM[6] SB_DM[7] C6 D7 G4 E1 M_A_DQ16 H10 M_A_DM2 M_A_DM3 M_B_DQ16 M_B_DQ17 M_B_DM2 H7 H6 H3 M_A_DQ17 M_A_DQ18 M_B_DM3 G8 M7 G2 K1 AH1 M_B_DM4 AG6 M_A_DM4 M_B_DQ18 M_B_DQ19 K7 J6 AM7 M_A_DM5 AL2 M_B_DM5 M_A_DQ19 J8 J3 AN10 M_A_DM6 AN13 M_A_DM7 AR4 M_B_DM6 AT8 M_B_DM7 M_A_DQ20 M_B_DQ20 M_B_DQ21 G7 G1 M_A_DQ21 G10 G5 M_A_DQ22 M_A_DQ23 M_B_DQ22 M_B_DQ23 J7 J2 M_A_DQS#[7:0] [12] M_B_DQS#[7:0] [13] M_A_DQS#0 M_A_DQS#1 M_B_DQS#0 M_B_DQS#1 J10 C9 J1 D5 SA_DQS#[0] SA_DQS#[1] SA_DQS#[2] SA_DQS#[3] SA_DQS#[4] SA_DQS#[5] SA_DQS#[6] SA_DQS#[7] SB_DQS#[0] SB_DQS#[1] SB_DQS#[2] SB_DQS#[3] SB_DQS#[4] SB_DQS#[5] SB_DQS#[6] SB_DQS#[7] M_A_DQ24 L7 F8 M_B_DQ24 J5 F4 M_A_DQS#2 M_A_DQS#3 M_A_DQ25 M_A_DQ26 M6 J9 M_B_DQ25 M_B_DQ26 K2 M_B_DQS#2 M_B_DQS#3 J4 M8 N9 L3 L4 AH7 M_A_DQS#4 M_A_DQ27 L9 M_B_DQ27 M1 AH2 M_B_DQS#4 B B M_A_DQ28 AK9 M_A_DQS#5 M_B_DQ28 L6 K5 M_B_DQS#5 AL4 M_A_DQ29 M_A_DQ30 AP11 M_A_DQS#6 AT13 M_A_DQS#7 M_B_DQ29 M_B_DQ30 K8 K4 AR5 M_B_DQS#6 AR8 M_B_DQS#7 N8 M4 M_A_DQ31 M_B_DQ31 P9 N5 M_A_DQS[7:0] [12] M_B_DQS[7:0] [13] M_A_DQ32 AH5 M_A_DQS0 M_A_DQS1 M_B_DQ32 AF3 M_B_DQS0 M_B_DQS1 C8 C5 SA_DQS[0] SA_DQS[1] SA_DQS[2] SA_DQS[3] SA_DQS[4] SA_DQS[5] SA_DQS[6] SA_DQS[7] SB_DQS[0] M_A_DQ33 AF5 M_B_DQ33 AG1 F9 E3 SB_DQ[33] SB_DQS[1] M_A_DQ34 AK6 M_A_DQS2 M_B_DQ34 AJ3 M_B_DQS2 H9 H4 SB_DQ[34] SB_DQS[2] M_A_DQ35 AK7 M_A_DQS3 M_B_DQ35 AK1 M_B_DQS3 M9 M5 SB_DQ[35] SB_DQS[3] AH8 M_A_DQS4 M_A_DQ36 AF6 M_B_DQ36 AG4 AG2 M_B_DQS4 SB_DQ[36] SB_DQS[4] AK10 M_A_DQS5 M_A_DQ37 AG5 M_B_DQ37 AG3 AL5 M_B_DQS5 SB_DQ[37] SB_DQS[5] AN11 M_A_DQS6 AR13 M_A_DQS7 M_A_DQ38 M_B_DQ38 AJ4 AP5 M_B_DQS6 AJ7 SB_DQ[38] SB_DQS[6] M_A_DQ39 M_B_DQ39 AH4 M_B_DQ40 AK3 AR7 M_B_DQS7 AJ6 SB_DQ[39] SB_DQS[7] M_A_DQ40 AJ10 M_A_A[15:0] [12] M_B_A[15:0] [13] SB_DQ[40] M_A_DQ41 M_A_A0 M_B_DQ41 AK4 M_B_A0 M_B_A1 AJ9 Y3 U5 SA_MA[0] SA_MA[1] SA_MA[2] SA_MA[3] SA_MA[4] SA_MA[5] SA_MA[6] SA_MA[7] SA_MA[8] SA_MA[9] SA_MA[10] SA_MA[11] SA_MA[12] SA_MA[13] SA_MA[14] SA_MA[15] SB_DQ[41] SB_MA[0] M_A_DQ42 AL10 M_A_A1 M_B_DQ42 AM6 M_B_DQ43 AN2 W1 V2 SB_DQ[42] SB_MA[1] AA8 M_A_A2 AA3 M_A_A3 M_A_DQ43 AK12 M_B_A2 M_B_A3 T5 SB_DQ[43] SB_MA[2] M_A_DQ44 AK8 M_B_DQ44 AK5 M_B_DQ45 AK2 V3 SB_DQ[44] SB_MA[3] M_A_DQ45 AL7 M_A_DQ46 AK11 M_A_A4 M_B_A4 M_B_A5 V1 R1 SB_DQ[45] SB_MA[4] AA9 M_A_A5 M_B_DQ46 AM4 M_B_DQ47 AM3 T8 SB_DQ[46] SB_MA[5] M_A_DQ47 AL8 M_A_DQ48 AN8 M_A_A6 M_A_A7 M_B_A6 M_B_A7 V8 R2 SB_DQ[47] SB_MA[6] M_B_DQ48 AP3 T1 R6 SB_DQ[48] SB_MA[7] M_A_DQ49AM10 M_A_DQ50 AR11 M_A_A8 M_B_DQ49 AN5 M_B_A8 M_B_A9 Y9 R4 SB_DQ[49] SB_MA[8] M_B_DQ50 AT4 M_B_DQ51 AN6 M_B_DQ52 AN4 M_A_A9 U6 R5 SB_DQ[50] SB_DQ[51] SB_MA[9] SB_MA[10] M_A_DQ51 AL11 M_A_DQ52 AM9 AD4 M_A_A10 AB5 M_B_A10 M_A_A11 M_B_A11 T2 P3 SB_DQ[52] SB_DQ[53] SB_MA[11] SB_MA[12] M_B_DQ53 AN3 M_A_DQ53 AN9 M_A_DQ54 AT11 M_A_A12 M_B_A12 U3 R3 AG8 M_A_A13 M_B_DQ54 AT5 M_B_DQ55

内容简介：

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