电子专业音响音响ic dac非传统dac pcm1732

1、PCM1732For most current data sheet and other product information, visit 24-Bit, 96kHz, Stereo AudioMDIGITAL-TO-ANALOG CONVERTERWith HDCD DecoderFEATURES ENHANCED MULTI-LEVEL DS DAC INPUT AUDIO DATA WORD: 16-, 20-,DESCRIPTIONThe PCM1732 is designed for mid- to high-grade digital aud

2、io applications which achieve 96kHz sam- pling rates with 24-bit audio data, such as High Defi- nition Compatible Digital (HDCD) CD players, DVD players, mini-disc players and AV receivers.PCM1732 uses a newly-developed “enhanced, multi- level delta-sigma modulator” architecture that im- proves audi

3、o dynamic performance and reduces jitter sensitivity.The internal digital filter operates at 8x oversampling24-Bit SAMPLING FREQUENCY (fs): 16kHz - 96kHz SYSTEM CLOCK: 256, 384, 512, 768fS HIGH PERFORMANCE: THD+N: 96dB Dynamic Range: 104dB SNR: 104dB AUDIO OUTPUT LEVEL: 0.57 x VCC (Vp-p) 8x OVERSAMP

4、LING DIGITAL FILTER WITH HDCD DECODER:Stopband Attenuation: 120dB Passband Ripple: 0.00001dBHDCD Filter Optimized for 44.1kHz to 48kHz and 88.2kHz to 96kHz MULTI-FUNCTIONS:at a 96kHz attenuation.samplingrate,with120dB stopbandDigital De-emphasis Soft MuteDigital Attenuation Zero DetectPCM1732BCKINHD

5、CDAmplitude DecodingSerial Input I/FLRCINHDCDHidden CodeRecoveryDINDigital GacalingReversible Output Phase +5V SINGLE-SUPPLY OPERATION SMALL SO-28 PACKAGEVOUTLEXTLLow-Pass FilterDACHDCD8xEnhanced Multi-LevelDSModulatorOversampling Digital FilterML/I2S MC/DEMMD/FSSV RLow-Pass FilterOUTDACEXTRMode Con

6、trol I/FCS/IWOMODEZERONOTE An HDCD license from Pacific Microsonics, Inc. is required to purchase the PCM1732.BPZ ControlMUTERSTSCKPower-On ResetOpen DrainHDCD is a registered trademark of Pacific Microsonics, Inc.Crystal/OSCPower SupplyHDCD technology is provided under license from Pacific Microson

7、ics Inc. The PCM1732s design is covered by the following patents:In the USA: 45,479,168, 5,638,074, 5,640,161, 5,808,574, 5,838,2745,854,600, 5,864,311, 5,872,531.In Australia: 669,114. Other patents pending.XTIXTOCLKOVCC1 AGND1DGNDVDDInternational Airport Industrial Park Mailing Address: PO Box 114

8、00, Tucson, AZ 85734 Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 Tel: (520) 746-1111 Twx: 910-952-1111 Internet: / Cable: BBRCORP Telex: 066-6491 FAX: (520) 889-1510 Immediate Product Info: (800) 548-6132 1999 Burr-Brown CorporationPDS-1522BPrinted in U S A August,

9、 1999VCC2L AGND2LVCC2R AGND2RSPECIFICATIONS24-Bit Data PerformanceAll specifica ions at +25C, +VCC = +VDD = +5V, fS = 44.1kHz, and SYSCLK = 384fS, unless otherwise noted.NOTES: (1) Refer to the System Clock section of this data sheet. (2) An external buffer is recommended. (3) Dynamic performance sp

10、ecifications are tested with 20kHz low-pass filter and THD+N specifications are tested with 30kHz LPF, 400Hz HPF, Average Mode. (4) Dynamic performance specifications are tested with HDCD ga caling set to analog ga caling. (5) SNR is tested with infinite zero detection off. (6) Output level is for s

11、ine wave. DAC outputs 0 64 VCC (peak-to-peak) due to filter response as transient.PCM17322PARAMETERCONDITIONSPCM1732UNITSMINTYPMAXRESOLUTION24BitsDATA FORMATAudio Data Interface Format Data Bit LengthAudio Data Format Sampling Frequency (fS) System Clock Frequency(1) System Clock Duty Cycle1MSB-Fir

12、1640Standard/I2S/20/24 Selectable t, Binary Twos C6/384/512/768fSmplement 9660kHz%DIGITAL INPUT/OUTPUT LOGIC LEVELInput Logic Level (except XTI): VIHVILOutput Logic Level (CLKO):VOHVOLIOH = 2mA IOL = 4mA2.0V V V VCLKO PERFORMANCE(2)Output Rise Time Output Fall Time Output Duty Cycle20 80% V

13、DD, 10pF80 20% VDD, 10pF10pF Load5.5430ns ns%DYNAMIC PERFORMANCE(3, 4)THD+NVO = 0dBVO = 60dBDynamic RangeSignal-to-Noise Ratio(5) Channel SeparationfS = 44.1kHz fS = 96kHz fS = 44.1kHzfS = 44.1kHz, EIAJ A-weighted fS = 96kHz, A-weightedfS = 44.1kHz, EIAJ A-weighted fS = 96kHz, A-weightedfS = 44.1kHz

14、 fS = 96kHz98989696944210410310410310410190dB dB dBdB dB dB dB dB dBDC ACCURACYGain ErrorGain Mismatch Channel-to-Channel Bipolar Zero ErrorVO = 0.5VCC at Bipolar Zero1.01.0303.03.060% of FSR% of FSR mVANALOG OUTPUTOutput Voltage(6) Center Voltage Load ImpedanceFull Scale (0dB) AC Load50.57 VCC0.5 V

15、CCVp-p VkWDIGITAL FILTER PERFORMANCEFilter Characteristics 1(fS = 44.1kHz/48kHz optimal) PassbandStopband Passband RippleStopband AttenuationDelay TimeFilter Characteristics 2(fS = 88.2kHz/96kHz optimal) PassbandStopband Passband RippleStopband Attenuation Delay TimeDe-Emphasis Error0.002dB3dB 0.453

16、fSStopband = 0.515fS Stopband = 0.520fS0.005dB3dB 2.2V (typical). During internal reset = LOW, the output of the DAC is invalid and the analog outputs are forced to VCC /2. Figure 5 illustrates the timing of the internal power-on reset.PCM1732 accepts an external forced reset when RST = LOW. When RS

17、T = LOW, the output of the DAC is invalid and the analog outputs are forced to VCC /2 after internal initialization (1024 system clocks count after RST = HIGH.) Figure 6 illustrates the timing of the RST pin.Zero Out (pin 21)Zero is an open drain output. If the input data is continuously zero for 65

18、,536 cycles of BCKIN, an internal FET is switched to “ON” and the drain of the internal FET is switched to ground. The zero detect function is available in both software mode and hardware mode.DC level at bipolar zero. The synchronization occurs in less than 1 cycle of LRCIN.typicallyFIGURE 1. System Clock Connection.NOTE: (1) The internal crystal oscillator