基于verilog的循环计数器

1、电子与信息工程系Verilog数字系统设计实 验 名 称专业、年级学 号姓 名循环计数器以下内容由实验指导教师填写（实验内容请以批注的形式批阅）实验项目完成情况实验项目成绩指导教师时 间年 月 日实验五 循环计数器一、实验目的1、熟悉Quartus和 Modelsim 软件2、学习分配管脚和下载测试3、乘法运算显示电路设计验证二、循环计数器的源代码module xunhuan(clk,hex0,hex1);input clk;output 7:0hex0,hex1;reg7:0hex0,hex1;reg4:0count;reg25:0fenpin;reg clk_fp;always(posed

2、ge clk)beginif(fenpin26d50000000) fenpin=fenpin+1b1;elsefenpin=26d0;endalways(posedge clk)beginif(fenpin=26d24999999) clk_fp=1b1;elseclk_fp5d0) count=count-1d1;else count=5d29; case(count) 5d29: begin hex0=8h90; hex1=8ha4;end 5d28: begin hex0=8h80; hex1=8ha4;end 5d27: begin hex0=8hf8; hex1=8ha4;end

3、5d26: begin hex0=8h82; hex1=8ha4;end 5d25: begin hex0=8h92; hex1=8ha4;end 5d24: begin hex0=8h99; hex1=8ha4;end 5d23: begin hex0=8hb0; hex1=8ha4;end 5d22: begin hex0=8ha4; hex1=8ha4;end 5d21: begin hex0=8hf9; hex1=8ha4;end 5d20: begin hex0=8hc0; hex1=8ha4;end 5d19: begin hex0=8h90; hex1=8hf9;end 5d18

4、: begin hex0=8h80; hex1=8hf9;end 5d17: begin hex0=8hf8; hex1=8hf9;end 5d16: begin hex0=8h82; hex1=8hf9;end 5d15: begin hex0=8h92; hex1=8hf9;end 5d14: begin hex0=8h99; hex1=8hf9;end 5d13: begin hex0=8hb0; hex1=8hf9;end 5d12: begin hex0=8ha4; hex1=8hf9;end 5d11: begin hex0=8hf9; hex1=8hf9;end 5d10: be

5、gin hex0=8hc0; hex1=8hf9;end 5d9: begin hex0=8h90; hex1=8hc0;end 5d8: begin hex0=8h80; hex1=8hc0;end 5d7: begin hex0=8hf8; hex1=8hc0;end 5d6: begin hex0=8h82; hex1=8hc0;end 5d5: begin hex0=8h92; hex1=8hc0;end 5d4: begin hex0=8h99; hex1=8hc0;end 5d3: begin hex0=8hb0; hex1=8hc0;end 5d2: begin hex0=8ha

6、4; hex1=8hc0;end 5d1: begin hex0=8hf9; hex1=8hc0;end 5d0: begin hex0=8hc0; hex1=8hc0;end endcase endEndmodule三：Transcript显示结果：Loading work.xuanhuan_vlg_tst# Loading work.xuanhuan# * Warning: (vsim-3009) TSCALE - Module xuanhuan does not have a timescale directive in effect, but previous modules do.# Region: /xuanhuan_vlg_tst/i1# # add wave *# view structure# .main_erior.cs.body.struct# view signals# .main_erior.cs.body# run -all# 0 xxxxxxxx xxxxxxx