大规模数字逻辑课程设计流水灯设计

1、大规模数字逻辑课程设计题目:流水灯设计学 号： xxx 姓 名： xxx 班 级： xxx 目录1.流水灯控制的实验要求与思路31.1实验要求31.2实验思路32.系统逻辑设计：43.源程序代码4(1)分频器部分4(2)控制模块54.实验步骤:75. 实验原理图：76.分配管脚87.运行界面：88.总结与体会109.参考文献101. 流水灯控制的实验要求与思路1.1实验要求在流水灯控制系统中,要求开发板上的8个led灯依次以0.5s的时间间隔从上到下再下到上的顺序点亮，然后分别以1s、1.5s、2s的时间间隔和相同顺序点亮8个led灯，以此为一个循环，重复以上四个步骤就可以实现流水灯系统的自动

2、循环运作。1.2实验思路根据时钟信号的脉冲输入，我们以改变每个led点亮状态的保持的时间来改变led的变换间隔时间，根据led的循环点亮和时间间隔的改变设计成为一个直观的led流水灯自动循环系统，由此思路我们就可以很容易的着手流水灯控制程序的设计。2. 系统逻辑设计： 根据以上的设计要求，运用模块化的设计思路，我们在quartus ii8.0 软件系统中设计了led流水灯控制模块、分频器模块，并通过各个模块程序之间的端口合理连接和协调，成功设计出led流水灯灯控制电路，得到逻辑结构原理图，即为整个流水灯控制电路的逻辑结构。使用veriloghdl语言设计相应的模块。3.源程序代码(1)/ 分频

3、器部分 ，获得便于试验观察的时钟信号module clk_div(clk_out,clk_in); input clk_in; output clk_out; reg clk_out; integer counter; parameter cnt=25_000_000; always (posedge clk_in) begincounter=counter+1; if(counter=cnt/2-1)begin clk_out=!clk_out; counter=0;end endendmodule（2）/控制模块：module lsd(clk,led);input clk;output 7

4、:0led;/ 输出端口定义为寄存器型reg 7:0 count;reg 7:0 count1;reg 7:0 count2;reg 7:0 led;reg 3:0 state; always (posedge clk)/ always语句，表示每当clk的上升沿到来时，完成begin-end之间语句的操作 begin count=count+1; if(count17) begin state = state + 4b0001; / one clk,one state case(state) 4b0000: led = 8b00000001; /the 1st state 4b0001: l

5、ed = 8b00000010; 4b0010: led = 8b00000100; 4b0011: led = 8b00001000; 4b0100: led = 8b00010000; 4b0101: led = 8b00100000; 4b0110: led = 8b01000000; 4b0111: led = 8b10000000; 4b1000: led = 8b10000000; 4b1001: led = 8b01000000; 4b1010: led = 8b00100000; 4b1011: led = 8b00010000; 4b1100: led = 8b0000100

6、0; 4b1101: led = 8b00000100; 4b1110: led = 8b00000010; 4b1111: led = 8b00000001; default: state = 4b0000; / default,8b00000001 endcase end else if(count49) begin if(count%2=0) begin state = state + 4b0001; / one clk,one state case(state) 4b0000: led = 8b00000001; /the 2st state 4b0001: led = 8b00000

7、010; 4b0010: led = 8b00000100; 4b0011: led = 8b00001000; 4b0100: led = 8b00010000; 4b0101: led = 8b00100000; 4b0110: led = 8b01000000; 4b0111: led = 8b10000000; 4b1000: led = 8b10000000; 4b1001: led = 8b01000000; 4b1010: led = 8b00100000; 4b1011: led = 8b00010000; 4b1100: led = 8b00001000; 4b1101: l

8、ed = 8b00000100; 4b1110: led = 8b00000010; 4b1111: led = 8b00000001; default: state = 4b0000; / default,8b00000001 endcase end end else if(count97) begin count1=count1+1; if(count1%3=0) begin state = state + 4b0001; / one clk,one state case(state) 4b0000: led = 8b00000001; /the 3st state 4b0001: led

9、 = 8b00000010; 4b0010: led = 8b00000100; 4b0011: led = 8b00001000; 4b0100: led = 8b00010000; 4b0101: led = 8b00100000; 4b0110: led = 8b01000000; 4b0111: led = 8b10000000; 4b1000: led = 8b10000000; 4b1001: led = 8b01000000; 4b1010: led = 8b00100000; 4b1011: led = 8b00010000; 4b1100: led = 8b00001000;

10、 4b1101: led = 8b00000100; 4b1110: led = 8b00000010; 4b1111: led = 8b00000001; default: state = 4b0000; / default,8b00000001 endcase end end else if(count161) begin count2=count2+1; if(count2%4=0) begin state = state + 4b0001; / one clk,one state case(state) 4b0000: led = 8b00000001; /the 4st state

11、4b0001: led = 8b00000010; 4b0010: led = 8b00000100; 4b0011: led = 8b00001000; 4b0100: led = 8b00010000; 4b0101: led = 8b00100000; 4b0110: led = 8b01000000; 4b0111: led = 8b10000000; 4b1000: led = 8b10000000; 4b1001: led = 8b01000000; 4b1010: led = 8b00100000; 4b1011: led = 8b00010000; 4b1100: led =

12、8b00001000; 4b1101: led = 8b00000100; 4b1110: led = 8b00000010; 4b1111: led = 8b00000001; default: state = 4b0000; / default,8b00000001 endcase end end else count=0; endendmodule4.实验步骤:将modul_sel拨码开关组合为1,2,8拨上3,4,5,6,7拨下,是数码管显示为c1.1 建立工程,对建立的工程命名、文件命名，选择相应的芯片及配置，然后在打开的工程下建立veriloghdl语言编写的文件：文件名分别是ls

13、d.v、clk_div.v，将这两个文件同时加入此工程内。2 将相应的文件转换为符号文件，并创建一个block，生成电路原理图，然后将此文件保存到当前工程下，并将文件名命名为lsdblock,然后将其设置为顶层实体。3 将步骤2中生成的block文件先进行综合，待综合无误之后进行管脚分配，之后进行全编译生成我们需要下载到开发板上的lsd.sof文件，然后加入下载界面，选择相应的设置，且在jtag模式下，然后下载该sof文件来观察开发板上led的变化现象。5. 实验原理图：6.分配管脚7. 运行界面：（1）根据lsd.v文件代码创建符号文件：（2）根据clk_div.v文件代码创建符号文件：（3）综合时显示框（4）全编译时显示框（5）下载文件的界面：8.总结与体会 此次课程设计，学到了很多课内学不到的东西，比如独立思考解决问题，出现差错的随机应变，和与人合作共同提高，都受益非浅，通过这次的课程设计，使我对基础知识加深了理解，熟练了软件qutars ii8.0的基本操作，并且对一个设计中的流程有所了解，知道了每个操作步骤的具体作用，这样可以使自己更加明白的去操作每