Freescale公司的QorIQ系列处理器P1010学习

1、Freescale公司的QorIQ系列处 理器P1010学习P1010学习笔记P1010是Freescale公司QorIQ系列通信处理器的一款入门级两核处理器芯片，具有高性能、低功耗、性价比高的特点。QorIQ P1010eS00v2 Core32 KBi-Cache32 KBD-cacbeCoherent ModufeSQMVK?System SusimerfaoeAowterationP1010内部为e500V2内核，最高主频可达800MHz, 45nm制程工艺，支持 800Mbps数据率的DDR3 SDRAM或者DDR3L SDRAM接口，核心电源电压为1. 0V, 工作温度为0105C

2、,芯片外形尺寸为19mm*19mm, 425-pin, 0. 8mm的引脚间距。1. e500v2 内核： 32KB L1指令和数据缓存，256KB L2缓存，双精度浮点运算单元(FPU)； 双SATA I/II控制器，1.5/3Gbps,集成PHY,支持热插拔； 双PCIe 1.0, xl, 2. 5G/T (理论上单向峰值带宽为2.OGbps/lane,因 为接收和发送是相互独立的，故双向带宽为4Gbps/lane),集成SerDes PHY；既可以作为RC又可以作为EP;可配置成2个xl的port,支持单独的INT中断传输。 三个10/100/1000Mbps三态以太网控制器,集成MAC

3、,只能配置成RGMII、 SGMII 接口； 一个 DDR3/DDR3L 控制器，支持 16bit> 32bit 数据接口，16bit 为带 ECC 接口，32bit 不带 ECC,支持 600800Mbps,即 300400MHz 时钟频率；DDR3 SDRAM为1.5V电压供电，DDR3L为1.35V电源供电；两个bank,共 支持8GB容量DDR3颗粒，从64Mbits8Gbits的x8或者xl6位宽。 专用的保密引擎和boot； TDM 接口：接收数据、时钟和帧同步信号，发送数据、时钟和帧同步信号，收、发相 互独立，发送同步、时钟和接收时钟可以配置成输入或者输出。与E1/T1帧无

4、 缝对接，最高128时隙，8/16bits位宽，帧同步、数据可以设置在时钟的上升 沿或者下降沿采样，同步信号可以正向也可设置成负向有效。 双CAN Bus控制器； 集成SD/MMC/SDIO支持从外部Flash卡中启动； 一个USB2.0控制器，集成USBPHY； 可编程中断控制器PIC；可提供多处理器中断管理，负责接收内部和外部中断源，将它们分级并上 报给cpuo 集成Flash控制器IFC；支持 NOR FLASH 和 NAND FLASH, 8/16bit, 电源管理控制器PMC； 四通道通用DMA控制器； 两条12c控制器； SPI接口控制器，只支持P1010作为SPI主设备； 16个

5、GPI或者GPO管脚或者open-drain,可以独立配置； 系统定时器，包含周期性中断定时器、RTC、软件watchdog定时器和4 个通用定时器： 双 UART； 标准JTAG；2.高速接口的配置X6 SerDes可以配置成PCIe、SATA、SGMH接口，在上电复位时就确定。Table 1-1. Supported high-speed interface combinations4-lane SerDes2-lane SerDes012301PCI Express 1 x1(2.5)PCI Express 2 x1(2.5)SGMII 2 (1.25)SGMII 3 (1.25)SAT

6、A 1 (3.0)SATA 2 (3.0)PCI Express 1 x1(2.5)SGMII 1 (1.2S)SGMII 2 (1.25)SGMII 3 (1.25)SATA 1 (3.0)SATA 2 (3.0)OftSGMII 1 (1.25)SGMII 2 (1.25)SGMII 3 (1.25)PCI Express 1 xl 5)PCI Express 2 xl(2.5)eTSECl支持RGMII和SGMII,由cfg_io）ort 0:1来决定，同时决定 的还有PCIe和SATA；eTSEC2/3 只支持 SGMIIoI able 4-2U. berues i/u port an

7、a protocol selectionFunctional signalReset configurati on nameValue(Binary)4-Lane SerDes2-Lane SerDes012301IFC_AD(13: 14Default (11)cfg_io_port s0:100offOffoffottottoff01PCI Express 1 xl5)PCI Express2x1(2.5)©TSEC2 asSGMII(1.25)gTSEC 3 asSGMII(125)SATA1(3.0)SATA2(3.0)10PCI Express 1 x1(2.5)eTSEC

8、l asSGMII(125)eTSEC2 as SGMII(1-25)eTSEC3 as SGMII(1-25)SATAI (3.0)SATA2(3.0)11offeTSECl as SGMII(1.25)eTSEC2 as SGMII(1-25)eTSEC3 as SGMII(1-25)PCI Express 1 X1(2.5)PCI Express 2x1(2.5)2 .芯片信号定义_MDQ(O：151食MDQ1653PWECC0：7jIO aMDC(24r3iQoMDQSO3LoAMCCS_B0：3l rAMDMO：3A攸 0:15f AMBAJOZ1。QDDflMCS_DO.OMRAS

9、_B4WGAS-B1MWE_B1：KEO：11oMCKMGK_B1MODHOzl1oMDIC0：1TSECl_TXD0：1i,158B_ALAflM_0UTI1222TSECl_TXD(2yi 588_PULSE_OUT1122TSEC1_TX_EN1TSECl_RXC(cyi588_TnG_IN1.11eTSECVTSECl_RXDiyi588_TRIG_IN2PIC(121158Gz7SECl_RXD(2yi 5S8.CLKJN1DMA,TSEC1_RXD(3P1588_CLK_OUT1GPIOTSECi_2X_DWDMA_DREQ_BIoyGPOl3.1TSEC1_RX_CUC-DMA_

10、DACK_9(OP'GPIC(14TSEC1_GTX_CLK/DMA_DDCNE_BO1 P1010TSFC1 GTX CLK12/PIC(15 _LIFC_AD(O:151IFC ADDRfl6VSDHC CLKAJS8 CLK/1FC OS B2IOFC_ADDR|' 71SDHC CIDUSB CfOyDMA DRE0_B|11IFC ADDRfUySDHC DAIJOpUSB C(iyDfXA DACK B|1)11r rC_ADOR(l0ySD4IC_DAriyueD C>(7>T>MA.DDONC D(1):1FC_ADDH20pSDHC_DAT1

11、2S9,D31FC_ADDPl2lp'SDHC_DATl3S3_D41IFCJWLHC.WP/LSB-DIS11IFC_ADDR23>SDHC_CD,*LS9_D61IFC_A0Dfl(24)<LS9_D7:11IFC_AVDIrv/1eSOHQ2JS3 ULPVIFC WE B1DMAFC.CLE1IFC-OE-B1IFC_WP_B1IFC_RB_B1IFC.BCTL1lFC_PAW0l/US8_STP11IFC_PAR11IFC_PERR_B4JS8,DIR .1IFC_CLKO1IFC_CJ<iyiFC_CS_B(31«USB_NXT111EC.MDC

12、一.EC MDIOcuieniei Marrnt1一 SPI_M0SlP!O(B一 J14.SPl.MSaGPfOfTSD"14 SPLCL»OCPIO8|GPIO1- SPLCS_B(oyGPQ9)11CAN1 TX4JAPT SOUmgM TX CATA11_ CAN 1 _RXAJART_SIN2yTDM_RX_DATACAHfi GAN2_,nOJART_SOUTl3FDM_TFSDUART/1CAN2_RXAJART_SINl3yTDM_RFSTDMIUART_SOUT011UART_SINO1_ UART_CTS_E(O1一 UART_RTS_B(0DUMT/I

13、UARLSOU 巾1 uwGPIO/14 UART_SIN(1IRQ14_ UART_CTS_B(TDM_TX_CUQGPIO：10P1RQ(10/ UART_flTS_B(TDM_RX_CUQGPiqi 11RQ(1:14IIC1,SDAIQ/C1_SCL14JIC2_SDA|2C1_ IIC2 SOL12JRQ1r彳IRQ2VTRIG INIQIRQ(3)SRESET_3n-MP_DETECTlmernjpis11IRQ OUT B1GPIOlcpiRQfDRV/BUSVDVAL1GPIO'p1RQ(5yVBUSPWRFAULT/MSaCID(01GPIOl2/lRQ(6ya(ST

14、PN_3/MS口C01GPIO1GPIO3yiRQ(7p,(XSTP_OUT_B.SRCID(2PIC/ ll£R1GPIO41RQ(BFVOP_B.-MSRCID(3MOOI1一 GPIOSKIRQ(9p-UDE_B.*MSRCID(4IHHEStT.B1HRESER_REQ_EControl1READV/TRIG_OCT/ASLEEPPcwer Mnamn!1 SYSCLKI一 RTC11USBPbY.CLK1o_ BVDD VSELTChll-ic veoJ1SCAN_MODE_B一DFT|SD2_TX1:0|L 12121o1tTCKJTAGSD2 TX ,8|1：0).TD

15、ISD2 RX1:0TDOSD2 RX B|1:0)21111141 P1010 414141 1111111.TMS、TRST BSD2 REF <XKSD2 REF OX BSD2 IMP CAL TXSD2 IMP CAL RXour i iSccOesi (x4|S01_TX,B(3;0S02_PLl_TPA产 1_RX3:0SD2 PLL TFDSO1RX B(3:0VBUSCLMPrSO1_REF_CLK.SO1_REF_CLK_BS01 IMP CAL TXBIAS REXTS01 IMP 81 RXUDP4 SO1_PLL_TPAUDMSO1_PLL_TPD-USB PH

16、Y配置信号要在HRESEJB的上升沿采样，但是普通配置信号与PLL 配置信号的建立、保持时间要求不一样。大部分复位配置信号都有内部 上拉电阻，有些没有内部上拉，需要外部上拉电阻。芯片复位过程中，会忽视绝大部分输入信号的状态，但是会将绝大 部分output信号驱动到inactive状态Table 3-2. Reset configuration signalsFunctional interfaceFunctional signal nam。Reset configuration nam。DefaultI FCIFC_AD(0:2cfg_sys_pll0:2No defaultIFC_AD7:8

17、cfg_ddr_pll0:1No defaultIFC_AD3:5cfg_core_pll0:2Must be drivenIFC_AD(6cfg_core_speed1IFC_AD9:11cfg_ifc_pb0:2J111IFC_AD15cfg_ifc_adm1IFC_WE_Bcfg_Hc_flash_mode1IFC_CLEcfg_host_agt01IFC_OE_Bcfg_ho$t_agt11IFC_AD13:14Jcfg_io_port$0:111IFC_AVDcfg_dram_typ©1IFC_AD12cfg_srds_refclk1IFC_BCTL CAN1_TXcfg_

18、boot_seq0:1j11IFC_PAR1cfg_plat_spoed1Functional interfaceFunctional signal nameReset configuration nameDefaultEthernet managementEC-MDCcfg_cpu_boot1DUARTUART_RTS_B0, UART_SOUT1Jcfg_ifc_ecc0:1J11System controlHRESET_REQ_Bcfg_sb_dis1oTSEClTSEC1_TXDO:3cfg_rom_loc0:3Must bo drivenTSEC1_TX_ENcfg_svr1PLL配

19、置:Table 4-9. CCB clock PLL ratioFunctional signalsReset configuration nameValue (Binary)CCB Clock : SYSCLK ratioIFC_AD0:2No Defaultcfg_sys_pll0:2000410015101061othersReservedDDR部分PLL的配置:Table 4-10. DDR complex clock PLL ratioFunctional signalsReset configuration nameValue (Binary)DDR complex : DDRCL

20、K ratioIFC_AD7:8No defaultcfg_ddr_pll0:1008: 10110:11012:111ReservedCore PLL配置：默认配置core工作频率2450MHz,若要V450MHz, 那么信号IFC_ADDR6要在HRESET时配置成低电平。Table 4-11. e500 core PLL ratiosFunctional signalsReset configuration nameValue (Binary)e500 core:CCB clock ratioIFC_AD3:5No Defaultcfg_core_pll0:2000Reserved001

21、Reserved0101 :10113: 2(1.5: 1)1002:11015： 2 (2.5:1)1103： 1111ReservedTable 4-12. Core speedFunctional signalsReset configuration nameValue (Binary)DescriptionIFC_ADDR(6cfg_core_spGed0Cor© clock frequency is less than 450 MHz.Default (1)1Core clock frequency is greater than or equal to 450 MHz.B

22、oot ROM启动模式选择：Table 4-13. Boot ROM locationFunctional signalsReset configuration nameValue (Binary)DescriptionTSEC1_TXDO:30000PCI Express 110001PCI Express 210010Reserved0011Reserved0100DDR controller20101Reserved0110SPI0111Reserved10008-bit NAND-512b page size10018-bit NAND-2k page size10108-bit NA

23、ND-4k page size10118-bit NOR110016-bit NAND-5l2b page size110116-bit NAND-2k page size111016-bit NAND-4k page size111116-bit NORNote: 1: Secure boot is not supported on PCIe in both root-complex and end-point modes 2: DDR controller as boot source is not supported in secure boot mode.Secure boot 配置：

24、Table 4-14. Secure bootFunctional signalsReset configuration nameValue (Binary)DescriptionHRESET_REQ_BDefault cfg_sb_dis0Device configured for trusted mode of operations.1Device configured for non-trusted mode of operations.Cfg.roncloc 选择 NAND Flash 时，IFC_AD9:11在 POR 过程中用于 选择每个block的page大小：Table 4-1

25、5. IFC pages per blockFunctional signalsReset configuration nameValue (Binary)DescriptionIFC_AD9:11Defaults 11)cfgjfc_pb(0:2000Reserved0012K pages per block0101K pages per bl<xk011512 pages per block100256 pages per block101128 pages per block11064 pages per block11132 pages per blockCfg_rom_loc

26、选择 NAND Flash 时，UART_RTS0、UART_SOUT1在 POR过底中用于选择ECC使能功能：Table 4-16. IFC ECC enable configurationFunctional signalsReset configuration nameValue (Binary)DescriptionUARTZRTS(0), UART_SOUT(1)Default 11)cfg_ifc_ecc0:100.01ECC disabled104b correction118b correctionCfg.romloc 选择 NOR Flash 时，IFC_AD 15在 POR

27、 过程中用于选 择哪些施址箱号与数据信号爱用，在此过程中IFC_AD是不能为低电平 的：Table 4-17. IFC address shift mode configurationFunctional signalsRosot configuration nameValu© (Binary)DescriptionIFC_AD15Default cfg_ifc_adm0Reserved1Higher order address bits are multiplexed with data onIFC_AD(0:15CSORO14:18 (ADM.SHFT) will be 0x07

28、IFC Flash模式配置：IFC_WE在POR过程中用于选择Flash模式功能：Table 4-18. IFC flash mode configurationFunctional signalsReset configuration nameValue (Binary)Descriptionifc_weDefault 9_ifc_flash_mode0cfg_rom_loc selected forNOR Boot: ReservedNAND Boot: Bad block indicator is at page 0 and last page of each block1cfg_rom

29、_loc selected forNOR Boot: Normal async NOR FlashNAND Boot: Bad block indicator is at page 0 and page 1 of each block.PCIe主/从模式配置：IFC_CLE和IFC.OE分别在POR过程中用于配 置芯片的PCIeO和PCIel接口的主从模式：Table 4-19. Host/agent configurationFunctional signalsReset configuration nameValue (Binary)MeaningIFC_CLEDefault cfg.ho

30、sLagtfOJ0Device acts as an end point on PCI Express 1 interface1DeviCG acts as a root complex on PCI Express 1 interfaceIFC_OtDefault(1)ctg_host_agi(i)0Dgvicg acts as an ©ndpoint on PCI Express 2 intertac©1DeviCG acts as a root complex on PCI Express 2 interface6-Lane SerDes 接口配置：IFC_AD13：

31、 14在 POR 过程中用于 6 组 SerDes 差分信号为 PCIe. SATA> SGMII 接口，当 SDn_REF_CLK 不提供时， 该Lane将关闭。Table 4-20. SerDes I/O port and protocol selectionFunctional signalReset configurati on nameValue (Binary)4-Lane SerDes2-Lane SerDes012301IFC_AD|13: 14Default (11)cfg_iojort s(0:100off0ffoffofloffoff01PCI Express 1

32、X15)PCI Express 2x1(2.5)eTSEC2 as SGMII(1.25)eTSEC 3 as SGMII(125)SATA1(3-0)SATA2(3.0)10PCI Express 1 X15)eTSECl as SGMII(1.25)eTSEC2 as SGMII(1.25)eTSEC3 as SGMII(125)SATA1(3.0)SATA2(3.0)11offeTSECl as SGMII(125)eTSEC2 as SGMII(1.25)qTSEC3 as SGMII(125)PCI Express 1 X1(2.5)PCI Express 2X15)三个TSEC接口

33、配置：IFC/D13:14在POR过程中同时用于3个TSEC 的配置选择。Table 4-21. eTSEC Interface SelectionFunctional SignalsReset configuration nameValue (Binary)eTSECl1eTSEC22eTSEC32IFC_AD(13:14JDefault (11)cfg_io_ports0:100RGMIIDisabledDisabled01RGMIISGMIISGMII10SGMIISGMIISGMII11SGMIISGMIISGMIICPU boot是否等待外部配置：EC_MDC在POR过程中决定CPU

34、是否需 要外部用于3个TSEC的配置选择。Table 4-22. CPU boot configurationFunctional signalReset configuration nameValue (Binary)MeaningEC_MDC(default 1)cfg_cpu_boot0CPU boot holdoff mode. The e500 core is prevented from booting until configured by an external master.1e500 core is allowed to boot wrthout waiting for c

35、orrfiguration by an external master.Boot顺序配置:IFC_BCTL、CAN1_TX在POR过程中决定CPU是从I2C1 上的ROM芯片启动还是不从I2C中启动。Table 4-23. Boot sequencer configurationFunctional signalReset configuration nameValue (Binary)MeaningIFC_BCTL, CAN1_TXDefault(H)cfg_boot_$eq0：i00Reserved01Normal PC addressing mode is used. Boot sequ

36、encer is enabled and loads configuration information from a ROM on the I2C1 interface. A valid ROM must be present.10Extended 12c addressing mode is used. Boot sequencer is enabled and loads configuration information from a ROM on the 12cl interlace. A valid ROM must be present.11Boot sequencer is d

37、isabled. No l2C ROM is accessed (default).DDR3 SDRAM类型选择配置：IFC_AVD在FOR过程中决定DDR3 SDRAM 的类型。Table 4-24. DDR DRAM typeFunctional signalReset configuration nameValue(Binary)MeaningIFC_AVDDefault (1)cfg_dramjype0DDR3L1.35 V. CKE low at reset1DDR31.5 V, CKE low at rosetSerDes参考时钟配置：IFCD12在POR过程中决定SerDes参考

38、 时钟是100MHz还是125MHzo4-1 ane和2-lane是分开的差分时钟输入,独立的锁相环。若SerDes PLL终止，P1010会启动。SerDes配置成的高速接口会disable直到 HRESET 完成。Table 4-25. SerDes reference clock configurationFunctional signalReset configuration nameValue(Binary )MeaningIFC_AD12Default (1)cfg_srds_refclk0SerDes expects a 125 MHz reference clock frequ

39、ency.1SerDes expects a 100 MHz reference clock frequency.Secure引擎是否使用的配置:HRESET_RE(LB在P0R过程中决定是否 用到内部Secure引擎。Table 4-26. Engineering useFunctional signalsReset configuration nameValue (Binary)MeaningHRESET.REQ.BDefault (1)cfg_sb_dis0P1010E is configured to bo a trustod system1P1010E is configured to be a non-trusted systemP1010版本号配置:TSEC1.TX.EN在P0R过程中为高,可以读取P1010 的版本号。I able 4-27. System version numberFunctional signalsReset configuration nameValue (Binary)MeaningTSEC1_TX_ENDefault (1)cfg.svr0Reserved1For P1010 this signal should be high during power on res