数字电路与逻辑设计实验报告

1、数字电路与逻辑设计实验报告学院： 班级： 班内序号：学号：姓名： 一、实验名称和实验任务要求1、 实验目的实验一：（1） 学会用QuartusII原理图输入法进行电路设计和仿真。（2） 掌握QuartusII图形模块单元的生成和调用。（3） 学会实验板的使用。（4） 加深对半加器、全加器电路原理的理解。实验二：（1） 学会用VHDL语言设计组合电路的方法。（2） 学会用QuartusII文本输入法进行电路设计。（3） 加深对数码管译码器、编码转换和奇偶校验电路原理的理解。实验三：（1）学会用VHDL语言设计时序电路的方法。（2）学会用QuartusII文本输入法进行电路设计。（3）加深对计数器

2、设计及分频器原理的理解。（4）学会用VHDL语言对结构体的行为、数据流和结构进行描述。实验四：（1） 学会用VHDL语言对状态机进行描述。（2） 掌握多个数码管动态扫描显示的原理及设计方法。2、 实验任务要求实验一： QuartusII 原理图输入法设计与实现（1） 用逻辑门设计一个半加器，仿真验证其功能，并生成新的半加器图形模块单元。（2） 用（1）生成的半加器模块和逻辑门设计实现一个全加器，仿真验证其功能，并下载到实验板测试。要求用拨码开关设定输入信号，发光二极管显示输出信号。实验二：（1） 用VHDL语言设计实现一个共阴极7段数码管译码器，仿真验证其功能，并下载到实验板测试。要求用拨码开

3、关设定输入信号，7段数码管显示输出信号。（2） 用VHDL语言设计实现一个8421BCD码转换为余3码的代码转换器，仿真验证其功能。（3） 用VHDL语言设计实现一个4位二进制奇偶校验器，输入奇数个1时，输出为1，否则输出0，仿真验证其功能。实验三：（1） 用VHDL语言设计实现一个带异步复位的8421BCD码十进制计数器，仿真验证其功能。（2） 用VHDL语言设计实现一个分频系数为12，分频输出信号占空比为50%的分频器，仿真验证其功能。（3） 用VHDL语言将（1）、（2）和数码管译码器3 个电路进行连接，仿真验证其功能，并下载到实验板测试。实验四：（1） 用VHDL语言设计实现六个数码管

4、串行扫描电路，要求同时显示0、1、2、3、4、5这六个不同的数字图形到6个数码管上，仿真验证其功能，并下载到实验板测试。（2） 用VHDL语言设计实现六个数码管滚动显示电路。循环左移动，始终点亮六个数码管，左进右出。状态为：012345->123450->234501->345012->450123->501234->012345向左滚动，用全灭的数码管填充右边，直至全部变灭，然后再依次从右边一个一个地点亮。状态为：012345->12345X->2345XX->345XXX->45XXXX->5XXXXX->XXXXXX

5、->XXXXX0->XXXX01->XXX012->XX0123->X01234->012345，其中X表示数码管不显示。二、 实验三（3）和实验四模块端口说明及连接图1、 实验三（3）模块端口说明entity cc isport(clkin: in std_logic; -连接后电路的输入时钟clearin: in std_logic; - 连接后电路的复位输入bout: out std_logic_vector (6 downto 0);- 连接后电路的输出cat:outstd_logic_vector(5 downto 0);- 确定电路某数码管亮en

6、d cc;component div12port(clk : in std_logic;- 12分频器的时钟输入clkout : out std_logic);- 12分频器的输出end component;component count10port(clk : in std_logic- 10进制计数器的的时钟输入clear : in std_logic;- 10进制计数器的复位输入cnt : out std_logic_vector(3 downto 0);- 10进制计数器的二进制输出end component;component cnt4port(a : in std_logic_ve

7、ctor (3 downto 0);- 数码管译码器的输入b : out std_logic_vector (6 downto 0);- 数码管译码器的输出end component;signal c : std_logic;signal d : std_logic_vector (3 downto 0);begincat<="110111"u1 : div12 port map(clk=>clkin, clkout=>c);u2 :count10 port map(clk=>c, clear=>clearin, cnt=>d);u3 :

8、 cnt4 port map(a=>d, b=>bout);end;端口说明：将12分频器输入时钟作为连接后电路输入时钟， 将10进制计数器的复位输入作为连接后图形的复位输入， 将数码管译码器的输出作为连接后图形的输出， 将12分频器输出连接10进制计数器时钟输入， 将10进制计数器输出连接数码管译码器输入。2、 实验三（3）连接图：3、 实验四模块端口说明：（1）数码管串行扫描电路clk:instd_logic； -输入时钟cat:outstd_logic_vector(5 downto 0)；-确定某数码管亮y:out std_logic_vector(6 downto 0)；

9、 -输出signal count:integer range 0 to 5；-6进制计数，在各个数码管之间进行切换signalcounter:integer range 0 to 2500-实现快速扫描的计数器。（2）数码管滚动显示电路clk:instd_logic;-点亮某个数码管的时钟输入y:out std_logic_vector(6 downto 0);-输出cat:outstd_logic_vector(5 downto 0); -确定某数码管亮signal count1: integer range 0 to 5；-每一次扫描的计数器，使六个管“同时”点亮signal count2

10、: integer range 0 to 5;-实现循环左滚动的计数器，共六个状态signal clk2:std_logic;-实现循环左滚动的时钟signaltmp: integer range 0 to 5000000;-实现滚动点亮的计数器signalcounter:integer range 0 to 25000;-实现快速扫描的计数器三、 实验一（2）、实验三（3）和实验四的原理图或VHDL 代码1、 实验一（2）原理图2、 实验三（3）VHDL代码library IEEE;use IEEE.std_logic_1164.all;useIEEE.std_logic_unsigned.

11、all;useIEEE.std_logic_arith.all;entity cc isport(clkin,clearin: in std_logic;bout: out std_logic_vector (6 downto 0);cat:outstd_logic_vector(5 downto 0);end cc;architecturecc_arch of cc iscomponent div12port(clk : in std_logic;clkout : out std_logic);end component;component count10port(clk,clear : i

12、n std_logic;cnt : out std_logic_vector(3 downto 0);end component;component cnt4port(a : in std_logic_vector (3 downto 0);b : out std_logic_vector (6 downto 0);end component;signal c : std_logic;signal d : std_logic_vector (3 downto 0);begincat<="110111"u1 : div12 port map(clk=>clkin,

13、 clkout=>c);u2 : count10 port map(clk=>c, clear=>clearin, cnt=>d);u3 : cnt4 port map(a=>d, b=>bout);end;3、 实验四VHDL代码实验四（1）：libraryieee;use ieee.std_logic_1164.all;useieee.std_logic_unsigned.all;useieee.std_logic_arith.all;entitysaom isport(clk:instd_logic;cat:outstd_logic_vector(5

14、downto 0);y:out std_logic_vector(6 downto 0) );endsaom; architecturesaom_arch of saom issignalcount:integer range 0 to 5;signalcounter:integer range 0 to 2500;beginprocess(clk)beginif(clk'event and clk='1')thenif counter=2500 thencounter<=0;case count iswhen 0 =>y<="1111110

15、"cat<="011111"count<=count+1;when 1 =>y<="0110000"cat<="101111"count<=count+1;when 2 =>y<="1101101"cat<="110111"count<=count+1;when 3 =>y<="1111001"cat<="111011"count<=count+1;when 4

16、=>y<="0110011"cat<="111101"count<=count+1;when 5 =>y<="1011011"cat<="111110"count<=0;end case;else counter<=counter+1;end if;end if;end process;end;实验四（2）：libraryieee;use ieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entity

17、state isport(clk:instd_logic;y:out std_logic_vector(6 downto 0);cat:outstd_logic_vector(5 downto 0);end state;architecturestate_arch of state issignal count1: integer range 0 to 5;signal count2: integer range 0 to 5;signal clk2:std_logic;signaltmp: integer range 0 to 5000000; signalcounter:integer r

18、ange 0 to 25000;beginprocess(clk)beginifclk'event and clk='1' thenif counter=25000 thencounter<=0;case count2 iswhen 0=>case count1 iswhen 0=>y<="1111110" cat<="011111"count1<=count1+1;-0when 1=> y<="0110000" cat<="101111"

19、;count1<=count1+1;-1when 2=> y <="1101101" cat<="110111"count1<=count1+1;-2when 3=> y<="1111001" cat<="111011"count1<=count1+1;-3when 4 => y <="0110011"cat<="111101"count1<=count1+1;-4when 5 => y &l

20、t;="1011011"cat<="111110"count1<= 0;-5when others=> count1<=0;end case;when 1=>case count1 iswhen 0 => y <="1111110"cat<="111110" count1<=count1+1;-0when 1 => y<="0110000"cat<="011111"count1<=count1+1;

21、-1when 2 => y<="1101101"cat<="101111" ;count1<=count1+1;-2when 3 => y<="1111001"cat<="110111"count1<=count1+1;-3when 4 => y <="0110011"cat<="111011"count1<=count1+1;-4when 5 => y <="1011011&quo

22、t;cat<="111101"count1<= 0;-5when others=> count1<=0;end case;when 2=>case count1 iswhen 0 => y <="1111110"cat<="111101" count1<=count1+1;-0when 1 => y <="0110000"cat<="111110"count1<=count1+1;-1when 2 => y &l

23、t;="1101101"cat<="011111"count1<=count1+1;-2when 3 => y <="1111001"cat<="101111"count1<=count1+1;-3when 4 => y <="0110011"cat<="110111"count1<=count1+1;-4when 5 => y <="1011011"cat<="111

24、011"count1<= 0;-5when others=> count1<=0;end case;when 3=>case count1 iswhen 0 => y <="1111110"cat<="111011" count1<=count1+1;-0when 1 => y <="0110000"cat<="111101"count1<=count1+1;-1when 2 => y <="1101101&qu

25、ot;cat<="111110"count1<=count1+1;-2when 3 => y <="1111001"cat<="011111"count1<=count1+1;-3when 4 => y <="0110011"cat<="101111"count1<=count1+1;-4when 5 => y <="1011011"cat<="110111"count1<

26、= 0;-5when others=> count1<=0;end case;when 4=>case count1 iswhen 0 => y <="1111110"cat<="110111" count1<=count1+1;-0when 1 => y <="0110000"cat<="111011"count1<=count1+1;-1when 2 => y <="1101101"cat<="11

27、1101"count1<=count1+1;-2when 3 => y <="1111001"cat<="111110"count1<=count1+1;-3when 4 => y <="0110011"cat<="011111"count1<=count1+1;-4when 5 => y <="1011011"cat<="101111"count1<= 0;-5when others=&

28、gt; count1<=0;end case;when 5=>case count1 iswhen 0 => y <="1111110"cat<="101111" count1<=count1+1;-0when 1 => y <="0110000"cat<="110111"count1<=count1+1;-1when 2 => y <="1101101"cat<="111011" ;count1&

29、lt;=count1+1;-2when 3 => y <="1111001"cat<="111101"count1<=count1+1;-3when 4 => y <="0110011"cat<="111110"count1<=count1+1;-4when 5 => y <="1011011"cat<="011111"count1<= 0;-5when others=> count1<=0;

30、end case;when others=>case count1 iswhen 0 => y <="1111110" cat<="011111"count1<=count1+1;-0when 1 => y <="0110000" cat<="101111"count1<=count1+1;-1when 2 => y <="1101101" cat<="110111"count1<=count1+1

31、;-2when 3 => y <="1111001" cat<="111011"count1<=count1+1;-3when 4 => y <="0110011" cat<="111101"count1<=count1+1;-4when 5 => y <="1011011" cat<="111110"count1<= 0;-5when others=> count1<=0;end case;

32、end case;else counter<=counter+1;end if;end if;end process;process(clk2)beginif clk2'event and clk2='1' thenif count2="111" or count2="110"or count2=5 then count2<=0;else count2<=count2+1;end if;end if;end process ;process(clk)beginifclk'event and clk=

33、9;1' theniftmp= 5000000 then tmp<=0; clk2<=not clk2;elsetmp<=tmp+1;end if;end if;end process;end;实验四（2）：libraryieee;use ieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entityrool isport(clk:instd_logic;y:out std_logic_vector(6 downto 0);cat:outstd_logic_vector(5 downto 0);endrool

34、;architecturerool_arch of rool issignal count1: integer range 0 to 5;signal count2: integer range 0 to 11;signal clk2:std_logic;signaltmp: integer range 0 to 5000000;signalcounter:integer range 0 to 25000;beginprocess(clk)beginifclk'event and clk='1' thenif counter=25000 thencounter<=

35、0;case count2 iswhen 0=>case count1 iswhen 0 => y <="1111110"cat<="011111" count1<=count1+1;-0when 1 => y <="0110000"cat<="101111"count1<=count1+1;-1when 2 => y <="1101101"cat<="110111" ;count1<=count1

36、+1;-2when 3 => y <="1111001"cat<="111011"count1<=count1+1;-3when 4 => y <="0110011"cat<="111101"count1<=count1+1;-4when 5 => y <="1011011"cat<="111110"count1<= 0;-5when others=> count1<=0;end case;w

37、hen 1=>case count1 iswhen 0 => y <="1111110"cat<="111111" count1<=count1+1;-0when 1 => y <="0110000"cat<="011111"count1<=count1+1;-1when 2 => y <="1101101"cat<="101111" ;count1<=count1+1;-2when 3 =>

38、 y <="1111001"cat<="110111"count1<=count1+1;-3when 4 => y <="0110011"cat<="111011"count1<=count1+1;-4when 5 => y <="1011011"cat<="111101"count1<= 0;-5when others=> count1<=0;end case;when 2=>case co

39、unt1 iswhen 0 => y <="1111110"cat<="111111" count1<=count1+1;-0when 1 => y <="0110000"cat<="111111"count1<=count1+1;-1when 2 => y <="1101101"cat<="011111"count1<=count1+1;-2when 3 => y <="11110

40、01"cat<="101111"count1<=count1+1;-3when 4 => y <="0110011"cat<="110111"count1<=count1+1;-4when 5 => y <="1011011"cat<="111011"count1<= 0;-5when others=> count1<=0;end case;when 3=>case count1 iswhen 0 =>

41、 y <="1111110"cat<="111111" count1<=count1+1;-0when 1 => y <="0110000"cat<="111111"count1<=count1+1;-1when 2 => y <="1101101"cat<="111111"count1<=count1+1;-2when 3 => y <="1111001"cat<=&qu

42、ot;011111"count1<=count1+1;-3when 4 => y <="0110011"cat<="101111"count1<=count1+1;-4when 5 => y <="1011011"cat<="110111"count1<= 0;-5when others=> count1<=0;end case;when 4=>case count1 iswhen 0 => y <="11111

43、10"cat<="111111" count1<=count1+1;-0when 1 => y <="0110000"cat<="111111"count1<=count1+1;-1when 2 => y <="1101101"cat<="111111"count1<=count1+1;-2when 3 => y <="1111001"cat<="111111"coun

44、t1<=count1+1;-3when 4 => y <="0110011"cat<="011111"count1<=count1+1;-4when 5 => y <="1011011"cat<="101111"count1<= 0;-5when others=> count1<=0;end case;when 5=>case count1 iswhen 0 => y <="1111110"cat<=&qu

45、ot;111111" count1<=count1+1;-0when 1 => y <="0110000"cat<="111111"count1<=count1+1;-1when 2 => y <="1101101"cat<="111111" ;count1<=count1+1;-2when 3 => y <="1111001"cat<="111111"count1<=count1+1;-

46、3when 4 => y <="0110011"cat<="111111"count1<=count1+1;-4when 5 => y <="1011011"cat<="011111"count1<= 0;-5when others=> count1<=0;end case;when 6=>case count1 iswhen 0 => y <="1111110" cat<="111111"c

47、ount1<=count1+1;-0when 1 => y <="0110000" cat<="111111"count1<=count1+1;-1when 2 => y <="1101101" cat<="111111"count1<=count1+1;-2when 3 => y <="1111001" cat<="111111"count1<=count1+1;-3when 4 => y

48、<="0110011" cat<="111111"count1<=count1+1;-4when 5 => y <="1011011" cat<="111111"count1<= 0;-5when others=> count1<=0;end case;when 7=>case count1 iswhen 0 => y <="1111110"cat<="111110" count1<=coun

49、t1+1;-0when 1 => y <="0110000"cat<="111111"count1<=count1+1;-1when 2 => y <="1101101"cat<="111111" ;count1<=count1+1;-2when 3 => y <="1111001"cat<="111111"count1<=count1+1;-3when 4 => y <="0110

50、011"cat<="111111"count1<=count1+1;-4when 5 => y <="1011011"cat<="111111"count1<= 0;-5when others=> count1<=0;end case;when 8=>case count1 iswhen 0 => y <="1111110"cat<="111101" count1<=count1+1;-0when 1 =&g

51、t; y <="0110000"cat<="111110"count1<=count1+1;-1when 2 => y <="1101101"cat<="111111"count1<=count1+1;-2when 3 => y <="1111001"cat<="111111"count1<=count1+1;-3when 4 => y <="0110011"cat<=&q

52、uot;111111"count1<=count1+1;-4when 5 => y <="1011011"cat<="111111"count1<= 0;-5when others=> count1<=0;end case;when 9=>case count1 iswhen 0 => y <="1111110"cat<="111011" count1<=count1+1;-0when 1 => y <="011

53、0000"cat<="111101"count1<=count1+1;-1when 2 => y <="1101101"cat<="111110"count1<=count1+1;-2when 3 => y <="1111001"cat<="111111"count1<=count1+1;-3when 4 => y <="0110011"cat<="111111"cou

54、nt1<=count1+1;-4when 5 => y <="1011011"cat<="111111"count1<= 0;-5when others=> count1<=0;end case;when 10=>case count1 iswhen 0 => y <="1111110"cat<="110111" count1<=count1+1;-0when 1 => y <="0110000"cat<=

55、"111011"count1<=count1+1;-1when 2 => y <="1101101"cat<="111101"count1<=count1+1;-2when 3 => y <="1111001"cat<="111110"count1<=count1+1;-3when 4 => y <="0110011"cat<="111111"count1<=count1+1;-

56、4when 5 => y <="1011011"cat<="111111"count1<= 0;-5when others=> count1<=0;end case;when 11=>case count1 iswhen 0 => y <="1111110"cat<="101111" count1<=count1+1;-0when 1 => y <="0110000"cat<="110111"

57、count1<=count1+1;-1when 2 => y <="1101101"cat<="111011" ;count1<=count1+1;-2when 3 => y <="1111001"cat<="111101"count1<=count1+1;-3when 4 => y <="0110011"cat<="111110"count1<=count1+1;-4when 5 => y

58、<="1011011"cat<="111111"count1<= 0;-5when others=> count1<=0;end case;when others=>case count1 iswhen 0 => y <="1111110" cat<="111111"count1<=count1+1;-0when 1 => y <="0110000" cat<="111111"count1<=

59、count1+1;-1when 2 => y <="1101101" cat<="111111"count1<=count1+1;-2when 3 => y <="1111001" cat<="111111"count1<=count1+1;-3when 4 => y <="0110011" cat<="111111"count1<=count1+1;-4when 5 => y <="

60、;1011011" cat<="111111"count1<= 0;-5when others=> count1<=0;end case;end case;else counter<=counter+1;end if;end if;end process;process(clk2)beginif clk2'event and clk2='1' thenif count2=15 or count2=14 or count2=13 or count2=12 or count2=11 then count2<=

61、0;else count2<=count2+1;end if;end if;end process ;process(clk)beginifclk'event and clk='1' theniftmp= 5000000 then tmp<=0; clk2<=not clk2;elsetmp<=tmp+1;end if;end if;end process;end;四、 实验一（2）、实验三（3）和实验四的仿真波形图1、 实验一（2）仿真波形图2、 实验三（3）仿真波形图3、 实验四（1）仿真波形图4、 实验四（2）仿真波形图5、 实验四（2）仿真波形图五、 仿真波形图分析1、 实验一（1）分析：a、b为本位的两个加数，c代表本位向高位的进位,s为本位的和。逻辑关系为：如：仿真波形从左到右依次为：a=0,b=0,c=0,s=0; a=1,b=0,c=0,s=1; a=0,b=1,c=0,s=1; a=1,b=1,c=1,s=0;2、 实验一（2）分析：a、b为本位的两个加数，ci为低位