Verilog程序设计交通灯控制

1、 timescale 1ns / 1ps/ Company: / Engineer:/ Create Date: 16:38:22 04/22/08/ Design Name: / Module Name: traffic/ Project Name: / Target Device: / Tool versions: / Description:/ Dependencies:/ / Revision:/ Revision 0.01 - File Created/ Additional Comments:/ /module traffic(CLK,EN,LAMPA,LAMPB,ACOUNT,B

2、COUNT);/端口说明output7:0 ACOUNT,BCOUNT;output3:0 LAMPA,LAMPB;input CLK,EN;/内部信号说明reg7:0 numa,numb;/ACOUNT和BCOUNT的内部信号reg tempa,tempb;reg2:0 counta,countb;/方向A和方向B的灯的状态reg7:0 ared,ayellow,agreen,aleft,bred,byellow,bgreen,bleft;reg3:0 LAMPA,LAMPB;/设置各交通灯的持续时间初始化值，红灯的值由另一个方向的黄灯和绿灯计算得出。always (EN)if(!EN) b

3、egin /使能信号EN无效时，对交通灯的计数值进行初始化ared =8d55; /55 秒 = 30 + 5 + 15 + 5ayellow =8d5; /5 秒agreen =8d40; /40 秒aleft =8d15; /15 秒bred =8d65; /65 秒 = 40 + 5 + 15 + 5byellow =8d5; /5 秒bleft =8d15; /15 秒bgreen =8d30; /30 秒endassign ACOUNT=numa;/8位数码管输出assign BCOUNT=numb;/8位数码管输出/控制A方向四种灯的模块always (posedge CLK) b

4、eginif(EN) begin/使能有效时，交通灯开始工作if(!tempa) begintempa=1;case(counta) /控制灯状态的顺序0: begin/状态0numa=agreen;/直行绿灯亮LAMPA=2;/输出0010counta=1;/进入下一个状态end1: begin/状态1numa=ayellow;/黄灯亮LAMPA=4;/输出0100counta=2;/进入下一个状态end2: begin/状态2numa=aleft;/左转绿灯亮LAMPA=1;/输出0001counta=3;/进入下一个状态end3: begin/状态3numa=ayellow;/黄灯亮LA

5、MPA=4;/输出0100counta=4;/进入下一个状态end4: begin/状态4numa=ared;/红灯亮LAMPA=8;/输出1000counta=0;/进入下一个状态（状态0）enddefault:/默认状态LAMPA1)/判断倒计时未归零时分别对高地位进行递减if(numa3:0=0) beginnuma3:0=4b1001;numa7:4=numa7:4-1;endelsenuma3:0=numa3:0-1;if (numa=2)tempa=0;/倒计时结束，返回灯状态变化判断，将进入下一个状态endendelse beginLAMPA=4b1000;/使能无效时，红灯亮c

6、ounta=0;/返回方向A的状态0(绿灯状态)tempa=0;/进入状态变化判断endend/控制B方向四种灯的模块，模块的语言描述与方向A的描述基本一致，这里不再重复注释，always (posedge CLK) begin if (EN) beginif(!tempb) begintempb=1;case (countb) 0: beginnumb=bred;LAMPB=8;countb=1;end1: beginnumb=bgreen;LAMPB=2;countb=2;end2: beginnumb=byellow;LAMPB=4;countb=3;end3: beginnumb=bleft;LAMPB=1;countb=4;end4: beginnumb=byellow;LAMPB=4;countb=0;enddefault:LAMPB1)if(!numb3:0) beginnumb3:0=9;numb7:4=numb7:4-1;end