现代电子技术综合实验之数字跑表

1、电 子 科 技 大 学现代电子技术综合实验实验报告实验题目：基于FPGA的数字跑表设计 姓名： 张华博 学号： 2011091010004 学院： 生命科学与技术学院 专业： 生物医学工程 指导老师： 陈学英 摘要：21世纪，电子技术获得了飞速的发展，电子计算机、数码产品、汽车、空调等都是电子科技的典型应用，现代电子产品几乎渗透了社会的各个领域，有力地推动了社会生产力的发展和社会信息化程度的提高，同时也使现代电子产品性能进一步提高，产品更新换代的节奏也越来越快。 随着人们生活水平的不断提高，不仅科学领域得到了飞速的发展，在体育领域中电子产品的应用也是对出可见。计时器作为一个简易的数字

2、集成电路的应用，可以说无处不在，计时器实用简单，携带方便，各种大小规模的比赛都离不开了计时器。随着科技的发展，计时器的精度也越来越高，运动员们都朝着“更高、更快、更强”目标发展，特别是短跑比赛要求计时器要有足够的精度，这样就出现了本课题研究的数字跑表，用以测量完场某项体育运动所用时间。用于径赛、游泳、自行车、赛马等对计时器精度要求在百分之一秒。 数字跑表具有计时功能，本设计的数字跑表有启动、停止、复位，按键消抖，选手分时显示的功能，表的最小精确值为0.01秒。 一、系统总体设计（设计要求，系统工作原理，单元电路的划分）1、设计要求指标：（1）跑表精度为0.01秒（2）跑表计

3、时范围为：1小时（3）设置开始计时/停止计时、复位两个按钮（4）显示工作方式：用六位BCD七段数码管显示读数。显示格式： 分 秒 0.01秒扩展功能：按键消抖选手分时显示要求：(1) 设计出符合设计要求的解决方案(2) 设计出单元电路(3) 利用EDA软件对各单元电路及整体电路进行仿真(4) 在开发板上实现设计(5) 撰写设计报告2、系统工作原理系统组成：消抖电路计数器石英振荡器分频器显示控制开始/复位按键时间显示选手到终点计时存/取按键数据锁存数据读取3、单元电路划分使能控制器（开关，复位等以设置到计数器中，没有单独设计模块，特此说明下）消抖模块计数器 分频器扫描显示控制器存储模块（集成在显

4、示模块中）2、 单元电路设计分频器模块 提供的标准信号是48MHz ，输出二个信号1KHz、100Hz，将原来48MHZ的频率分为100HZ和1000HZ，程序设计中采用了两个中间变量，通过控制中间变量来实现分频的目的，100HZ的中间变量的范围设置为240000，1000HZ的中变量的范围设置为24000。 分频器代码：library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity fdiv3 is Port ( clkin : in ST

5、D_LOGIC; clkout1k : out STD_LOGIC; clkout100 : out STD_LOGIC);end fdiv3;architecture Behavioral of fdiv3 issignal counter0:integer range 0 to 23999 :=0;signal counter1:integer range 0 to 4 :=0;signal clkout1k_tmp,clkout100_tmp:std_logic:='0'beginprocess(clkin)beginif clkin'event and clki

6、n='1' thenif counter0=23999 thencounter0<=0;clkout1k_tmp <=not clkout1k_tmp;elsecounter0<=counter0+1;end if;end if;end process;clkout1k<=clkout1k_tmp;process(clkout1k_tmp)beginif clkout1k_tmp'event and clkout1k_tmp='1' thenif counter1=4 thencounter1<=0;clkout100_tm

7、p <=not clkout100_tmp;elsecounter1<=counter1+1;end if;end if;end process;clkout100<=clkout100_tmp;end Behavioral;仿真代码:LIBRARY ieee;USE ieee.std_logic_1164.ALL; ENTITY testfdiv ISEND testfdiv; ARCHITECTURE behavior OF testfdiv IS COMPONENT fdiv3 PORT( clkin : IN std_logic; clkout1k : OUT std

8、_logic; clkout100 : OUT std_logic ); END COMPONENT; signal clkin : std_logic := '0' signal clkout1k : std_logic; signal clkout100 : std_logic; constant clkin_period : time := 10 ns;BEGIN uut: fdiv3 PORT MAP ( clkin => clkin, clkout1k => clkout1k, clkout100 => clkout100 ); clkin_proc

9、ess :process beginclkin <= '0'wait for clkin_period/2;clkin <= '1'wait for clkin_period/2; end process; END;仿真结果：计数器模块 计数器级联程序中本应该采用写一个六进制和十进制的计数器 ，然后采用画图的方法实现总计数器的设计（即采用两个六进制计数器和四个十进制计数器），本实验中采用了直接对总的计数器进行总体描述来实现（因为编写相对简单，不易处错误）。用了一个特别长的一大串if内嵌套if进行处理。同时，里面直接写了开始和复位的功能，相当

10、于把使能模块并入其中。分为十进制计数器和六进制计数器，代码分别如下 十进制计数器十进制计数器代码:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity counter is Port ( rst : in STD_LOGIC; clk : in STD_LOGIC; carry_out : out STD_LOGIC; count_out : out STD_LOGIC_VECTOR (3 downto 0);end counter

11、;architecture Behavioral of counter issignal count:STD_LOGIC_VECTOR (3 downto 0):="0000"beginprocess(rst,clk)beginif rst='0' thencount<="0000"elsif clk'event and clk='1' thenif count="1001"thencount<="0000"carry_out<='1'els

12、ecount<=count + 1;carry_out<='0'end if;end if;end process;count_out<=count;end Behavioral仿真代码：LIBRARY ieee;USE ieee.std_logic_1164.ALL;ENTITY testcounter ISEND testcounter; ARCHITECTURE behavior OF testcounter IS COMPONENT counter PORT( rst : IN std_logic; clk : IN std_logic; carry_

13、out : OUT std_logic; count_out : OUT std_logic_vector(3 downto 0) ); END COMPONENT; signal rst : std_logic := '0' signal clk : std_logic := '0' signal carry_out : std_logic; signal count_out : std_logic_vector(3 downto 0); constant clk_period : time := 10 ns; BEGIN uut: counter PORT

14、MAP ( rst => rst, clk => clk, carry_out => carry_out, count_out => count_out ); clk_process :process beginclk <= '0'wait for clk_period/2;clk <= '1'wait for clk_period/2; end process; stim_proc: process begin rst<='0' ; wait for 10000 ns; rst<='1&#

15、39; wait; end process;end behavior;仿真结果： 六进制计数器六进制计数器源代码： library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity counter6 is Port ( rst : in STD_LOGIC; clk : in STD_LOGIC; carry_out : out STD_LOGIC; count_out : out STD_LOGIC_VECTOR (3 downto 0);e

16、nd counter6;architecture Behavioral of counter6 issignal count:STD_LOGIC_VECTOR (3 downto 0):="0000"beginprocess(rst,clk)beginif rst='0' thencount<="0000"elsif clk'event and clk='1' thenif count="0101"thencount<="0000"carry_out<=&#

17、39;1'elsecount<=count + 1;carry_out<='0'end if;end if;end process;count_out<=count;end Behavioral;仿真代码：LIBRARY ieee;USE ieee.std_logic_1164.ALL;ENTITY testcounter6 ISEND testcounter6; ARCHITECTURE behavior OF testcounter6 IS COMPONENT counter6 PORT( rst : IN std_logic; clk : IN

18、std_logic; carry_out : OUT std_logic; count_out : OUT std_logic_vector(3 downto 0) ); END COMPONENT; signal rst : std_logic := '0' signal clk : std_logic := '0' signal carry_out : std_logic; signal count_out : std_logic_vector(3 downto 0); constant clk_period : time := 10 ns; BEGIN u

19、ut: counter PORT MAP ( rst => rst, clk => clk, carry_out => carry_out, count_out => count_out ); clk_process :process beginclk <= '0'wait for clk_period/2;clk <= '1'wait for clk_period/2; end process; stim_proc: process begin rst<='0' ; wait for 10000 ns;

20、 rst<='1' wait; end process;end behavior;仿真结果：顶层计数器模块仿真代码：LIBRARY ieee;USE ieee.std_logic_1164.ALL;USE ieee.numeric_std.ALL;LIBRARY UNISIM;USE UNISIM.Vcomponents.ALL;ENTITY bigcounter_bigcounter_sch_tb ISEND bigcounter_bigcounter_sch_tb;ARCHITECTURE behavioral OF bigcounter_bigcounter_sch

21、_tb IS COMPONENT bigcounter PORT( rst:INSTD_LOGIC; clk:INSTD_LOGIC; hs:OUTSTD_LOGIC_VECTOR (3 DOWNTO 0); ts:OUTSTD_LOGIC_VECTOR (3 DOWNTO 0); s0:OUTSTD_LOGIC_VECTOR (3 DOWNTO 0); s1:OUTSTD_LOGIC_VECTOR (3 DOWNTO 0); m0:OUTSTD_LOGIC_VECTOR (3 DOWNTO 0); m1:OUTSTD_LOGIC_VECTOR (3 DOWNTO 0); END COMPON

22、ENT; SIGNAL rst:STD_LOGIC; SIGNAL clk:STD_LOGIC; SIGNAL hs:STD_LOGIC_VECTOR (3 DOWNTO 0); SIGNAL ts:STD_LOGIC_VECTOR (3 DOWNTO 0); SIGNAL s0:STD_LOGIC_VECTOR (3 DOWNTO 0); SIGNAL s1:STD_LOGIC_VECTOR (3 DOWNTO 0); SIGNAL m0:STD_LOGIC_VECTOR (3 DOWNTO 0); SIGNAL m1:STD_LOGIC_VECTOR (3 DOWNTO 0);consta

23、nt clk_period : time := 10 ns;BEGIN UUT: bigcounter PORT MAP(rst => rst, clk => clk, hs => hs, ts => ts, s0 => s0, s1 => s1, m0 => m0, m1 => m1 ); clkin:process beginclk <= '0'wait for clk_period/2;clk <= '1'wait for clk_period/2; end process;rstin :proc

24、ess beginrst <= '0'wait for 1000ns;rst <= '1'wait;- for 40ns; end process;END;仿真结果：消抖模块在按键按下一次时会有如下的毛刺信号，这个毛刺信号持续时间虽然只有1-3ms，但是这对于硬件来说，还是很长的，最关键的是，会产生很多个下降沿和电平触发。所以必须对其进行处理，否则在按键按下一次后，run/stop 会反转多次。消抖方法分为硬件消抖和软件延时消抖。在FPGA 中可以定义三个D 触发器，进行硬件3ms 消抖（时间可以根据实际情况而定）。消抖代码如下：library IE

25、EE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_arith.ALL;use IEEE.STD_LOGIC_unsigned.ALL;entity xiaodou is Port ( clk : in STD_LOGIC; keyin : in STD_LOGIC; keyout : out STD_LOGIC);end xiaodou;architecture Behavioral of xiaodou issignal key_rst:STD_LOGIC;signal key_rst_1:STD_LOGIC;beginprocess(clk

26、,keyin)beginif clk'event and clk='1' thenif keyin='1' thenkey_rst<='1' ;key_rst_1<='1'elsekey_rst<=keyin;key_rst_1<=key_rst;end if;end if;end process;keyout<= key_rst_1 and (not key_rst);end Behavioral;仿真代码：LIBRARY ieee;USE ieee.std_logic_1164.ALL;

27、ENTITY testxiaodou ISEND testxiaodou; ARCHITECTURE behavior OF testxiaodou IS - Component Declaration for the Unit Under Test (UUT) COMPONENT xiaodou PORT( clk : IN std_logic; keyin : IN std_logic; keyout : OUT std_logic ); END COMPONENT; -Inputs signal clk : std_logic := '0' signal keyin :

28、std_logic := '0' -Outputs signal keyout : std_logic; - Clock period definitions constant clk_period : time := 10 ns; BEGIN - Instantiate the Unit Under Test (UUT) uut: xiaodou PORT MAP ( clk => clk, keyin => keyin, keyout => keyout ); - Clock process definitions clk_process :process

29、 beginclk <= '0'wait for clk_period/2;clk <= '1'wait for clk_period/2; end process; - Stimulus process stim_proc: process begin -keyin<='0'- hold reset state for 100 ns. wait for 100 ns;keyin<='1' wait for 3ns;keyin<='0'wait for 3ns;keyin<=&#

30、39;1' wait for 4ns;keyin<='0'wait for 3ns;keyin<='1' wait for 40ns;keyin<='0'wait for 3 ns;keyin<='1' wait for 3ns;keyin<='0'wait for 3ns;keyin<='1' wait for 3ns;keyin<='0' wait; end process;END;仿真结果：使能控制器模块通过一个锁存器，控制计数

31、暂停和开始。使能代码：library IEEE;use IEEE.STD_LOGIC_1164.ALL;entity enable is Port ( enin : in STD_LOGIC; enout : out STD_LOGIC);end enable;architecture Behavioral of enable issignal enouttmp:std_logic :='0'beginprocess(enin)beginif enin'event and enin='1' thenenouttmp<=not enouttmp;en

32、d if;enout<=enouttmp;end process;end Behavioral;仿真代码：LIBRARY ieee;USE ieee.std_logic_1164.ALL; ENTITY testenable ISEND testenable; ARCHITECTURE behavior OF testenable IS COMPONENT enable PORT( enin : IN std_logic; enout : OUT std_logic ); END COMPONENT; signal enin : std_logic := '0' sign

33、al enout : std_logic;BEGIN uut: enable PORT MAP ( enin => enin, enout => enout ); stim_proc: process begin enin<='0'- hold reset state for 100 ns. wait for 100 ns;enin<='1' wait for 10ns;enin<='0'wait for 500ns;enin<='1'wait for 10ns;enin<='0&

34、#39; wait; end process;END;仿真结果：显示模块程序（含存储功能）：library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity display is Port ( clk : in STD_LOGIC; rst: in STD_LOGIC; scount: in STD_LOGIC;-记录按键 m1 : in STD_LOGIC_VECTOR (3 downto 0); m0 : in STD_LOGIC_VECT

35、OR (3 downto 0); s1 : in STD_LOGIC_VECTOR (3 downto 0); s0 : in STD_LOGIC_VECTOR (3 downto 0); ts : in STD_LOGIC_VECTOR (3 downto 0); hs : in STD_LOGIC_VECTOR (3 downto 0); wei : out STD_LOGIC_VECTOR (2 downto 0); duan : out STD_LOGIC_VECTOR (6 downto 0);end display;architecture Behavioral of displa

36、y issignal cnt :STD_LOGIC_VECTOR (2 downto 0):= "000"signal data :STD_LOGIC_VECTOR (3 downto 0);signal num0 :STD_LOGIC_VECTOR (3 downto 0):="0000"signal num1 :STD_LOGIC_VECTOR (3 downto 0):="0000"signal scnt :STD_LOGIC_VECTOR (3 downto 0):= "0000"signal xiansh

37、i:STD_LOGIC_VECTOR (31 downto 0):= "00000000000000000000000000000000"signal xianshi1:STD_LOGIC_VECTOR (31 downto 0):= "00000000000000000000000000000000"signal stay1:STD_LOGIC_VECTOR (31 downto 0):= "00000000000000000000000000000000"signal stay2:STD_LOGIC_VECTOR (31 down

38、to 0):= "00000000000000000000000000000000"signal stay3:STD_LOGIC_VECTOR (31 downto 0):= "00000000000000000000000000000000"beginchuanshu:process(rst,hs,ts,s0,s1,m0,m1,num0,num1)beginif rst='1' thenxianshi1(3 downto 0)<=hs;xianshi1(7 downto 4)<=ts;xianshi1(11 downto 8

39、)<=s0;xianshi1(15 downto 12)<=s1;xianshi1(19 downto 16)<=m0;xianshi1(23 downto 20)<=m1;xianshi1(27 downto 24)<=num0;xianshi1(31 downto 28)<=num1;elsexianshi1<="00000000000000000000000000000000"end if;end process;cunchujishu:process(rst,scount)beginif rst='1' th

40、enif scount'event and scount='1' thenif scnt="0110" thenscnt<="0000"elsescnt<=scnt+1;end if;end if;elsescnt<="0000"end if;end process;process(rst,scnt,clk) beginif rst='1' thencase scnt iswhen "0000"=>stay1<=xianshi1;num0<

41、=scnt;xianshi<=xianshi1;when "0001"=>stay2<=xianshi1;num0<=scnt;xianshi<=xianshi1;when "0010"=>stay3<=xianshi1;num0<=scnt;xianshi<=xianshi1;when "0011"=>num0<=scnt;xianshi<=xianshi1;when "0100"=>xianshi<=stay1;xianshi(

42、27 downto 24)<="0001"when "0101"=>xianshi<=stay2;xianshi(27 downto 24)<="0010"when "0110"=>xianshi<=stay3;xianshi(27 downto 24)<="0011"when others =>xianshi<=xianshi1;end case;elsexianshi<="0000000000000000000000000

43、0000000"stay1<="00000000000000000000000000000000"stay2<="00000000000000000000000000000000"stay3<="00000000000000000000000000000000"end if;end process;scan:process(clk)beginif clk'event and clk = '1' thenif cnt = "111" thencnt<=&quo

44、t;000"elsecnt <=cnt + 1;end if;end if;end process;muxe:process(cnt,xianshi)begin case cnt iswhen"000"=>data<=xianshi(3 downto 0);when"001"=>data<=xianshi(7 downto 4);when"010"=>data<=xianshi(11 downto 8);when"011"=>data<=xianshi

45、(15 downto 12);when"100"=>data<=xianshi(19 downto 16);when"101"=>data<=xianshi(23 downto 20);when"110"=>data<=xianshi(27 downto 24);when others =>data<=xianshi(31 downto 28);end case;end process;bcd2led:process(data)beginduan<="1111111&qu

46、ot;case data iswhen "0000"=>duan<="0000001"when "0001"=>duan<="1001111"when "0010"=>duan<="0010010"when "0011"=>duan<="0000110"when "0100"=>duan<="1001100"when "0101

47、"=>duan<="0100100"when "0110"=>duan<="0100000"when "0111"=>duan<="0001111"when "1000"=>duan<="0000000"when "1001"=>duan<="0000100"when others=>null;end case;end process;wei

48、<=cnt;end Behavioral;仿真代码LIBRARY ieee;USE ieee.std_logic_1164.ALL; ENTITY testdiaplay ISEND testdiaplay; ARCHITECTURE behavior OF testdiaplay IS COMPONENT diaplay PORT( clk : IN std_logic; cs : IN std_logic_vector(3 downto 0); ds : IN std_logic_vector(3 downto 0); sl : IN std_logic_vector(3 downt

49、o 0); sh : IN std_logic_vector(3 downto 0); ml : IN std_logic_vector(3 downto 0); mh : IN std_logic_vector(3 downto 0); sel : OUT std_logic_vector(7 downto 0); led : OUT std_logic_vector(6 downto 0); g : OUT std_logic; dp : OUT std_logic ); END COMPONENT; signal clk : std_logic := '0' signal

50、 cs : std_logic_vector(3 downto 0) := (others => '0'); signal ds : std_logic_vector(3 downto 0) := (others => '0'); signal sl : std_logic_vector(3 downto 0) := (others => '0'); signal sh : std_logic_vector(3 downto 0) := (others => '0'); signal ml : std_lo

51、gic_vector(3 downto 0) := (others => '0'); signal mh : std_logic_vector(3 downto 0) := (others => '0'); signal sel : std_logic_vector(7 downto 0); signal led : std_logic_vector(6 downto 0); signal g : std_logic; signal dp : std_logic; constant clk_period : time := 10 ns; BEGIN

52、uut: multi PORT MAP ( clk => clk, cs => cs, ds => ds, sl => sl, sh => sh, ml => ml, mh => mh, sel => sel, led => led, g => g, dp => dp ); clk_process :process beginclk <= '0'wait for clk_period/2;clk <= '1'wait for clk_period/2; end process; sti

53、m_proc: process begin wait for 10 ns; cs <="0001"wait for 10 ns; ds <="0001"wait for 10 ns; sl <="0001"wait for 10 ns; sh <="0001"wait for 10 ns; ml <="0001"wait for 10 ns; mh <="0001"wait for 10 ns;cs <="0101"wait for 10 ns; ds <="0101"wait for 10 ns; sl <="0101"wait for 10 ns; sh <="0101"wait for 10 ns; ml <="0101"wait for 10 ns; mh <="0101"wait for 10 ns; wait; end proc