多功能数字钟课程设计VHDL代码书上程序改

1、library ieee;entity clock isport(clk1hz:in std_logic;-1hz脉冲-clk100:in std_logic;-100hz脉冲-weekclk:in std_logic;-星期调整脉冲-start_stop:in std_logic;-秒表启动/停止控制-reset:in std_logic;-秒表复位-adclk:in std_logic;-校时脉冲-setselect:in std_logic;-调整位选择脉冲-mode:in std_logic;-功能选择脉冲-showdate:in std_logic;-日期显示-dis:out std

2、_logic_vector(23 downto 0;-显示输出- glisten:out std_logic_vector(5 downto 0;-闪烁指示- weekout:out std_logic_vector(3 downto 0;-星期输出- qh:out std_logic-整点报时-;end clock;architecture arch of clock iscomponent adjustport (adclk: in std_logic;data_in: out std_logic_vector(7 downto 0;end component;component cont

3、rolport (setclk: in std_logic;setlap: out std_logic_vector (1 downto 0;mode: in std_logic;module: out std_logic_vector (2 downto 0;end component;component weekcounterport (clk: in std_logic;clk2: in std_logic;q: out std_logic_vector(3 downto 0;end component;component stopwatchport (clk: in std_logic

4、;reset: in std_logic;start_stop: in std_logic;centsec: out std_logic_vector(7 downto 0;sec: out std_logic_vector(7 downto 0;min: out std_logic_vector(7 downto 0;end component;component h_m_s_countport (clk: in std_logic;set: in std_logic;setlap: in std_logic_vector (1 downto 0;d:in std_logic_vector(

5、7 downto 0;sec:out std_logic_vector(7 downto 0;min:out std_logic_vector(7 downto 0;hour:out std_logic_vector(7 downto 0;qh:out std_logic;qc: out std_logic;end component;component y_m_d_countport (clk: in std_logic;set: in std_logic;setlap: in std_logic_vector(1 downto 0;data_in: in std_logic_vector(

6、7 downto 0;day: out std_logic_vector (7 downto 0;month: out std_logic_vector (7 downto 0;year: out std_logic_vector (7 downto 0;end component;component displayport (module: in std_logic_vector (2 downto 0;showdate:in std_logic;clk:in std_logic;setlap:in std_logic_vector(1 downto 0;watch: in std_logi

7、c_vector (23 downto 0;time:in std_logic_vector(23 downto 0;date:in std_logic_vector(23 downto 0;dis: out std_logic_vector (23 downto 0;glisten:out std_logic_vector(5 downto 0 ;end component;signal data_in,mcentsec,msec,mmin,ssec,smin,shour,sdate,smonth,syear:std_logic_vector(7 downto 0;signal setlap

8、:std_logic_vector(1 downto 0;signal module:std_logic_vector(2 downto 0;signal qc:std_logic;signal watch,time,date:std_logic_vector(23 downto 0;beginu1:adjust port map(adclk,data_in;u2:control port map(setselect,setlap,mode,module;u3:stopwatch port map(clk100,reset,start_stop,mcentsec,msec,mmin;u4:h_

9、m_s_count port map(clk1hz,module(1,setlap,data_in,ssec,smin,shour,qh,qc;u5:y_m_d_count port map(qc,module(2,setlap,data_in,sdate,smonth,syear;u6:display port map(module,showdate,clk1hz,setlap,watch,time,date,dis,glisten;u7:weekcounter port map(qc,weekclk,weekout;watch<=mmin&msec&mcentsec;

10、time<=shour&smin&ssec;date<=syear&smonth&sdate;end arch;library ieee;entity adjust isport (adclk: in std_logic;data_in: out std_logic_vector(7 downto 0;end adjust;architecture arch of adjust issignal temp2,temp1:std_logic_vector(3 downto 0;beginprocess(adclkbeginif rising_edge(

11、adclkthenif temp1="1001" thentemp2<=temp2+'1'temp1<="0000"elsetemp1<=temp1+'1'end if;if temp2="1001" and temp1="1001" thentemp1<="0000"temp2<="0000"end if;end if;data_in<=temp2&temp1;end process;end arc

12、h;library ieee;entity control isport (setclk: in std_logic;-调整脉冲-setlap: out std_logic_vector (1 downto 0;-调整位选择脉冲- mode: in std_logic;-功能选择脉冲-module: out std_logic_vector (2 downto 0-功能输出-;end control;architecture arch of control issignal ssetlap:std_logic_vector(1 downto 0;signal s:std_logic_vecto

13、r(3 downto 0;beginprocess(mode,setclkbeginif mode='1'thenssetlap<="00"elsif rising_edge(setclk thenif ssetlap="10"thenssetlap<="00"elsessetlap<=ssetlap+'1'end if;end if;end process;setlap<=ssetlap;process(modebeginif rising_edge(mode thencase

14、 s iswhen"0001"=>s<="0010"when"0010"=>s<="0100"when"0100"=>s<="1000"when"1000"=>s<="0001"when others=>s<="0010"end case;end if;end process;module<=s(3 downto 1;end arch;library

15、ieee;entity counter60 isport (clk: in std_logic;-计数脉冲-clr: in std_logic;-复位-q: out std_logic_vector(7 downto 0;-计数值- qc:out std_logic-进位输出-;end counter60;architecture arch of counter60 issignal temp1,temp2:std_logic_vector(3 downto 0; beginprocess(clr,clkbeginif clr='1'thentemp1<="00

16、00"temp2<="0000"elsif rising_edge(clkthenif temp1="1001" thentemp2<=temp2+'1'temp1<="0000"elsetemp1<=temp1+'1'end if;if temp2="0101" and temp1="1001" thentemp1<="0000"temp2<="0000"qc<='

17、;1'elseqc<='0'end if;end if;q<=temp2&temp1;end process;end arch;library ieee;entity counter99 isport (clk: in std_logic;-100vhz计数脉冲-en: in std_logic;-计数使能-clr: in std_logic;-复位-q: out std_logic_vector(7 downto 0;-计数值-qc: out std_logic-进位-;end counter99 ;architecture arch of cou

18、nter99 issignal temp1,temp2:std_logic_vector(3 downto 0; beginprocess(clr,clkbeginif clr='1'thentemp1<="0000"temp2<="0000"elsif rising_edge(clkthenif en='1' thenif temp1="1001" thentemp2<=temp2+'1'temp1<="0000"elsetemp1<=

19、temp1+'1'end if;if temp2="1001" and temp1="1001" thentemp1<="0000"temp2<="0000"qc<='1'elseqc<='0'end if;end if;end if;q<=temp2&temp1;end process;end arch;library ieee;entity daycounter isport (clk: in std_logic;-计数脉冲-

20、set: in std_logic;-调整信号-day_in: in std_logic_vector(7 downto 0;-调整输入- day_out: out std_logic_vector(7 downto 0;-天输出- qc: out std_logic;-进位-day28: in std_logic;-该位为1表示该月为28天-day29: in std_logic;-该位为1表示该月为29天-day30: in std_logic; -该位为1表示该月为30天- day31: in std_logic-该位为1表示该月为31天-;end daycounter;architec

21、ture arch of daycounter issignal temp1,temp2:std_logic_vector(3 downto 0; signal days:std_logic_vector(7 downto 0;begindays<="00101000" when day28='1'else"00101001"when day29='1'else"00110000"when day30='1'else "00110001"when day31=&

22、#39;1'else"00000000"process(clk,set,day_in,daysbeginif set='1' thentemp2<=day_in(7 downto 4;temp1<=day_in(3 downto 0;elsif rising_edge(clkthenif temp1="1001" thentemp2<=temp2+'1'temp1<="0000"elsetemp1<=temp1+'1'end if;if temp2&

23、amp;temp1=days thentemp2<="0000"temp1<="0001"qc<='1'elseqc<='0'end if;end if;end process;day_out<=temp2&temp1;end arch;library ieee;entity days_control isport (month: in std_logic_vector(7 downto 0;-月份-year2: in std_logic;-年份高位数字bcd码最低位-year1: i

24、n std_logic_vector(1 downto 0;-年份低位数字bcd码末两位-day28: out std_logic; -该位为1表示该月为28天-day29: out std_logic; -该位为1表示该月为29天-day30: out std_logic; -该位为1表示该月为30天-day31: out std_logic-该位为1表示该月为31天-;end days_control;architecture arch of days_control isbeginprocess(month,year2,year1begincase month iswhen "

25、00000001"=>day28<='0'day29<='0'day30<='0'day31<='1'when "00000010"=>if (year2='0'and year1="00"or (year2='1'and year1="10" then day28<='0'day29<='1'day30<='0'day31<

26、;='0'elseday28<='1'day29<='0'day30<='0'day31<='0'end if;when "00000011"=>day28<='0'day29<='0'day30<='0'day31<='1'when "00000100"=>day28<='0'day29<='0'day30&

27、lt;='1'day31<='0'when "00000101"=>day28<='0'day29<='0'day30<='0'day31<='1'when "00000110"=>day28<='0'day29<='0'day30<='1'day31<='0'when "00000111"=>day28&

28、lt;='0'day29<='0'day30<='0'day31<='1'when "00001000"=>day28<='0'day29<='0'day30<='0'day31<='1'when "00001001"=>day28<='0'day29<='0'day30<='1'day31<='

29、0'when "00010000"=>day28<='0'day29<='0'day30<='0'day31<='1'when "00010001"=>day28<='0'day29<='0'day30<='1'day31<='0'when "00010010"=>day28<='0'day29<='

30、0'day30<='0'day31<='1'when others=>day28<='0'day29<='0'day30<='0'day31<='1'end case;end process;end arch;library ieee;entity display isport (module: in std_logic_vector (2 downto 0;-功能选择-showdate:in std_logic;-显示日期-clk:in std_l

31、ogic;-闪烁脉冲-setlap:in std_logic_vector(1 downto 0;-闪烁位选择- watch: in std_logic_vector (23 downto 0;-秒表计数值输入- time:in std_logic_vector(23 downto 0;-时分秒计数值输入- date:in std_logic_vector(23 downto 0;-年月日计数值输入- dis: out std_logic_vector (23 downto 0;-显示输出-glisten:out std_logic_vector(5 downto 0-闪烁输出-;end di

32、splay;architecture arch of display isbeginprocess(module,showdate,watch,time,datebeginif showdate='1'thendis<=date;elsecase module iswhen"001"=>dis<=watch;when"010"=>dis<=time;when"100"=>dis<=date;when others=>dis<=time;end case;end if

33、;end process;process(clk,module,setlapbeginif module="010"or module="100"thencase setlap iswhen"00"=>glisten(1 downto 0<=clk&clk;glisten(5 downto 2<="0000"when"01"=>glisten(3 downto 2<=clk&clk;glisten(5 downto 4<="00&qu

34、ot;glisten(1 downto 0<="00"when"10"=>glisten(5 downto 4<=clk&clk;glisten(3 downto 0<="0000"when others=>glisten<="000000"end case;else glisten<="000000"end if;end process;end arch;library ieee;entity dmux isport (set:in std_l

35、ogic;-调整信号-setlap: in std_logic_vector (1 downto 0;-调整位选择- d: in std_logic_vector(7 downto 0;-调整输入-set1:out std_logic;set2:out std_logic;set3:out std_logic;q1: out std_logic_vector(7 downto 0;q2: out std_logic_vector(7 downto 0;q3: out std_logic_vector(7 downto 0;end dmux;architecture arch of dmux i

36、sbeginprocess(set,setlap,dbeginif set='1' thencase setlap iswhen"00"=>set1<='1'set2<='0'set3<='0'q1<=d;when"01"=>set1<='0'set2<='1'set3<='0'q2<=d;when"10"=>set1<='0'set2&

37、lt;='0'set3<='1'q3<=d;when others=>set1<='0'set2<='0'set3<='0'end case;elseset1<='0'set2<='0'set3<='0'end if;end process;end arch;library ieee;entity h_m_s_count isport (clk: in std_logic;-1hz脉冲-set: in std_lo

38、gic;-调整信号-setlap: in std_logic_vector (1 downto 0;-调整位选择- d:in std_logic_vector(7 downto 0;-调整输入-sec:out std_logic_vector(7 downto 0;-秒输出-min:out std_logic_vector(7 downto 0;-分输出-hour:out std_logic_vector(7 downto 0;-小时输出- qh:out std_logic;-整点报时-qc: out std_logic-进位-;end h_m_s_count;architecture arc

39、h of h_m_s_count iscomponent sec_mincounterport (clk: in std_logic;set:in std_logic;d:in std_logic_vector(7 downto 0;q:out std_logic_vector(7 downto 0;qc:out std_logic;end component;component hourcounterport (clk: in std_logic;set:in std_logic;d:in std_logic_vector(7 downto 0;q: out std_logic_vector

40、(7 downto 0;qc:out std_logic;end component;component dmuxport (set:in std_logic;setlap: in std_logic_vector (1 downto 0;d: in std_logic_vector(7 downto 0;set1:out std_logic;set2:out std_logic;set3:out std_logic;q1: out std_logic_vector(7 downto 0;q2: out std_logic_vector(7 downto 0;q3: out std_logic

41、_vector(7 downto 0;end component;signal secset,minset,hourset: std_logic;signal secin,minin,hourin:std_logic_vector(7 downto 0;signal qcsec,qcmin,qchour: std_logic;beginu1:dmux port map(set,setlap,d,secset,minset,hourset,secin,minin,hourin; u2:sec_mincounter port map(clk,secset,secin,sec,qcsec;u3:se

42、c_mincounter port map(qcsec,minset,minin,min,qcmin;u4:hourcounter port map(qcmin,hourset,hourin,hour,qchour;qh<=qcmin;qc<=qchour;end arch;entity hourcounter isport (clk: in std_logic;-计数脉冲-set:in std_logic;-调整信号-d:in std_logic_vector(7 downto 0;-调整时间-q: out std_logic_vector(7 downto 0;-小时输出- q

43、c:out std_logic-进位-;end hourcounter;architecture arch of hourcounter issignal temp1,temp2:std_logic_vector(3 downto 0; beginprocess(clk,setbeginif set='1'thentemp2<=d(7 downto 4;temp1<=d(3 downto 0;elsif rising_edge(clk thenif temp1="1001" thentemp2<=temp2+'1'temp1

44、<="0000"elsetemp1<=temp1+'1'end if;if temp2="0010" and temp1="0100" thentemp1<="0000"temp2<="0000"qc<='1'elseqc<='0'end if;end if;end process;q<=temp2&temp1;end arch;library ieee;entity monthcounter is

45、clk: in std_logic;-计数脉冲-set: in std_logic;-调整信号-month_in: in std_logic_vector(7 downto 0;-调整输入- month_out: out std_logic_vector(7 downto 0;-月输出- qc: out std_logic-进位-;end monthcounter;architecture arch of monthcounter issignal temp1,temp2:std_logic_vector(3 downto 0;beginprocess(clk,set,month_inbegi

46、nif set='1' thentemp2<=month_in(7 downto 4;temp1<=month_in(3 downto 0;elsif rising_edge(clk thenif temp1="1001" thentemp2<=temp2+'1'temp1<="0000"elsetemp1<=temp1+'1'end if;if temp2="0001"and temp1="0010" thentemp2<=&qu

47、ot;0000"temp1<="0001"qc<='1'elseqc<='0'end if;end if;end process;month_out<=temp2&temp1;end arch;library ieee;entity sec_mincounter isport (clk: in std_logic;-计数脉冲-set:in std_logic;-调整信号-d:in std_logic_vector(7 downto 0;-调整时间输入-q:out std_logic_vector(7

48、downto 0;-分和秒输出-qc:out std_logic-进位-;end sec_mincounter;architecture arch of sec_mincounter issignal temp1,temp2:std_logic_vector(3 downto 0;beginprocess(clk,setbeginif set='1'thentemp2<=d(7 downto 4;temp1<=d(3 downto 0;elsif rising_edge(clk thenif temp1="1001" thentemp2<=

49、temp2+'1'temp1<="0000"elsetemp1<=temp1+'1'end if;if temp2="0101" and temp1="1001" thentemp1<="0000"temp2<="0000"qc<='1'elseqc<='0'end if;end if;end process ;q<=temp2&temp1;end arch;library ieee

50、;entity stopwatch isport (clk: in std_logic;-100hz脉冲-reset: in std_logic;-复位-start_stop: in std_logic;-启动/停止-centsec: out std_logic_vector(7 downto 0;-百分秒输出,当超过60分转为秒- sec: out std_logic_vector(7 downto 0;-秒输出,当超过60分转为分-min: out std_logic_vector(7 downto 0-分输出,当超过60分转为小时-;end stopwatch;architecture arch of stopwatch iscomponent counter99port (clk: in std_logic;en: in std_logic;clr: in std_logic;q: out std_logic_vector(7 downto 0;qc: out std_logic;end component;component