数电加法计数器无效态000110

1、目录1课程设计的目的与作用················································

2、;·························1 1.1设计目的及设计要求······················

3、83;················································1 1.2设计作用

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5、···································12设计任务··············

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7、·························13 三位二进制加法计数器的设计······················&#

8、183;·········································1 3.1设计原理·······

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10、;····························1 3.2设计过程····················&#

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12、183;··············240110串行序列检测器的设计································

13、3;··································4 4.1设计原理··············&

14、#183;·················································&

15、#183;····················4 4.2设计过程···························

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17、3;·······55. 12及10进制可控计数器的设计·······································

18、83;·······················7 5.1设计原理·························

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20、··········7 5.2设计过程······································

21、83;··············································76.仿真结果分析··

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23、································8 6.1三位二进制加法计数器仿真···············&

24、#183;···············································8 6.2 0110串航序

25、列检测器仿真·················································

26、···············12 6.3 12及10进制可控计数器仿真·······························

27、83;·····························147.设计总结···················&

28、#183;·················································&

29、#183;··················158.参考文献······························

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31、;········15.1设计目的与作用.1.1设计目的及设计要求根据设计要求设计三位二进制加法计数器，串行序列检测器及12和10进制可控计数器，加强对数字电子技术的了解，巩固课堂上学到的知识，了解计数器，串行序列检测器的工作原理。.1.2设计作用通过电路箱及multisim仿真软件的使用，可以使我们对计数器及串行检测器有更深的理解，并且学会分析仿真结果，与理论结果作比较。加强了自我动手动脑的能力。.2设计任务1.三位二进制加法计数器（无效态：000，110）2.串行序列检测器（检测序列：0110）3.12及10进

32、制可控计数器的设计及仿真.3 三位二进制加法计数器的设计.3.1设计原理设计一个三位二进制同步加法计数器，要求无效状态为000,110001 010 011 100 101 111图3.1.1 状态图 排列.3.2设计过程1 选择触发器，求时钟方程、输出方程和状态方程 a选择触发器 由于JK触发器的功能齐全，使用灵活，在这里选用3个CP下降沿触发的边沿JK触发器。 b求时钟方程 采用同步方案，故取CP是整个要设计的时序电路的输入时钟脉冲。 c求状态方程 由3.1所示状态图可直接画出电路次态卡诺图。再分解开便可以得到如图各触发器的卡诺图 Q1nQ0nQ2n 00 01 11 10xxx01010

33、0011101111001xxx 图3.2.1次态卡诺图Q1nQ0nQ2n 00 01 11 10x010110x 图3.2.2 的卡诺图 Q1nQ0nQ2n 00 01 11 10x101010x图3.2.3 的卡诺图Q1nQ0nQ2n 00 01 11 10x001111x图3.2.4 的卡诺图状态方程（2）求驱动方程JK触发器的特性方程为（3）画逻辑电路图根据所选用的触发器和时钟方程，输出方程，驱动方程，便可以画出如图所示的逻辑电路图。图3.2.5 三位二进制同步加法计数器逻辑电路（4）检查电路能否自启动，可见在CP操作下都能回到有效状态，电路能够自启动。.4 0110串行序列检测器的设

34、计.4.1设计原理设计一个串行序列信号检测器，检查输入信号中是否有“0110”序列信号。 设计步骤如下。1 逻辑抽象，画出电路状态转换图a输入变量用X表示，X=0表示位数据为0，X=1表示位数据为1。输出变量用Z表示，Z=1表示检测到0110序列信号，Z=0表示未检测到。b电路状态量为4个，电路状态编号分别用表示 各电路状态的含义：初始状态，电路还未收到一个有效的0：收到一个0或连续收到0后状态：连续收到01后的状态：连续收到011后的状态c.列出电路状态转换图如图所示。图中圆圈表示电路的各个状态，箭头表示在一个脉冲作用下，电路转换方向和结果；斜线上方和下方的数字表示转换前输入，输出变量的值.

35、0/0S0S1S2S31/00/00/11/01/00/01/0图4.1.1电路状态转换图从图中知，检测器的输出不仅取决于输入变量，而且还取决于电路的当前状态。.4.2设计过程(1) a.确定触发器的数目 电路状态数量M=4，代入，计算得n=2，电路需要两个触发器。b.电路状态编码电路状态用两个触发器的状态组合来表示，取的编码为00,01,11,10。(2)选定触发器，求出电路状态方程、输出方程和驱动方程a 确定触发器类型，JK触发器。b 逻辑函数化简，写出状态方程，输出方程，驱动方程。选用卡诺图化简的方法。可得次态变量，和输出变量Z的卡诺图， Q1nQ0nQ2 00 01 11 1001/001/001/001/100/011/010/000/0 图4.2.1 ，和输出变量Z的卡诺图 n Q1nQ0nQ2 00 01 11 1000 0 0 0 1 1 0 0 图4.2.2 Q1nQ0nQ2n 00 01 11 1011 1 1 0 1 0 0 图4.2.3 Q1nQ0nQ2n 00 01 11 1000010000 图4.2.4 Z在卡诺图中，用X，表示现态变量，并作为输入变量，进行化简后，得到电路状态方程电路输出方程 将式中的两个逻辑式与JK触发器特性方程进行比较，得到两个触发器的驱动方程2 画出逻辑电路图 根据驱动方程，画出0110序列信号检测器逻辑图，如图所示