数字逻辑与数字系统课程设计

1、 数字逻辑与数字系统课程设计 2013-12-15一、功能简介： 该课程设计的内容为数字时钟，能显示秒、分、时，且能在整点报时。时钟的变化在数码显像管中显示，因为时钟设计成60秒=1分，60分=1时，在整点报时时，过程太麻烦就做成15秒=1分，15=1时，这样在一会就回出现现象，更容易检查出对错。逢整点蜂鸣器在“15分钟的第11、13、秒发频率为512Hz的低音，在“15分钟的第15秒发频率为1024Hz的高音。 二、总体结构框图： 三、各模块框图：1、动态显示：八选一：library ieee; use ieee.std_logic_1164.all;ENTITY mux8_1 ISPORT

2、(d0,d1,d2,d3,d4,d5,d6,d7 : IN STD_LOGIC_VECTOR(3 DOWNTO 0); sel : IN STD_LOGIC_VECTOR(2 DOWNTO 0); y : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);END mux8_1;ARCHITECTURE rtl OF mux8_1 ISBEGIN PROCESS ( sel) BEGINCASE sel ISWHEN "000" =>y<=d0;WHEN "001" =>y<=d1;WHEN "010&qu

3、ot; =>y<=d2;WHEN "011" =>y<=d3;WHEN "100" =>y<=d4;WHEN "101" =>y<=d5;WHEN "110" =>y<=d6;WHEN "111" =>y<=d7; WHEN OTHERS =>y<="XXXX"END CASE; END PROCESS;END rtl;模八计数器library ieee; use ieee.std_logic

4、_1164.all;use ieee.std_logic_unsigned.all;entity count_8 is port(clk,clr: in std_logic; en : in std_logic; - '1'-count '0' -keep ql: out std_logic_vector(2 downto 0); c8 : out std_logic);end count_8;architecture rtl of count_8 issignal qcl :std_logic_vector(2 downto 0);begin process(

5、clk) begin if (clr='0') then qcl<="000" elsif (clk'event and clk='1') then if(en='1') then if(qcl="111") then qcl<="000"c8<='1' else qcl<=qcl+'1'c8<='0' end if; end if; end if; end process; ql<=qcl;en

6、d rtl;2、时钟控制模块：模16计数器：- count_16.vhd -library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity count_16 isport(clk,clr: in std_logic; en : in std_logic; - '1'-count,'0' -keep ql, qh : out std_logic_vector(3 downto 0); c16: out std_logic);end count_16;architectu

7、re behav of count_16 issignal qcl: std_logic_vector(3 downto 0);signal qch: std_logic_vector(3 downto 0);begin process(clk) begin if(clr='0') then qcl<="0000"qch<="0000" elsif(clk'event and clk='1') then c16<='0' if(en='1' and qch=&quo

8、t;0001" and qcl="0101") then qcl<="0000"qch<="0000"c16<='1' else if(en='1' and qcl<"1001") then qcl<=qcl+'1' elsif(en='1' and qcl="1001") then qch<=qch+'1'qcl<="0000" end if;

9、 end if; end if; qh<=qch; ql<=qcl; end process;end behav;模12计数器;- count_12.vhd -library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity count_12 isport(clk,clr: in std_logic; en : in std_logic; - '1'-count,'0' -keep ql, qh : out std_logic_vector(3 downto

10、 0); c12: out std_logic);end count_12;architecture behav of count_12 issignal qcl: std_logic_vector(3 downto 0);signal qch: std_logic_vector(3 downto 0);begin process(clk) begin if(clr='0') then qcl<="0000"qch<="0000" elsif(clk'event and clk='1') then c1

11、2<='0' if(en='1' and qch="0001" and qcl="0001") then qcl<="0000"qch<="0000"c12<='1' else if(en='1' and qcl<"1001") then qcl<=qcl+'1' elsif(en='1' and qcl="1001") then qch<

12、=qch+'1'qcl<="0000" end if; end if; end if; qh<=qch; ql<=qcl; end process;end behav;3、报时library ieee; use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity count is port(clk1,clk2: in std_logic; m1,m2,s1,s2 : in std_logic_vector(3 downto 0); cout : out std_log

13、ic);end count;architecture rtl of count isbegin process(clk1,clk2) begin if(m1="0001" and m2="0101") then if(s1="0001")then if(s2="0001")then cout<=clk1; elsif(s2="0011")then cout<=clk1; elsif(s2="0101")then cout<=clk2; end if; end

14、 if; end if; end process;end rtl;4、分频：用的模8计数器：模8计数器：library ieee; use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity count_8 is port(clk,clr: in std_logic; en : in std_logic; - '1'-count '0' -keep ql: out std_logic_vector(2 downto 0); c8 : out std_logic);end count_8;architecture rtl of count_8 issignal qcl :std_logic_vector(2 downto 0);begin process(clk) begin if (clr='0') then qcl<="000" elsif (clk'event