EDA考试题目和答案

1、精选优质文档-倾情为你奉上设计实验与考核1、 设计一个带计数使能、异步复位、带进位输出的增1六位二进制计数器，计数结果由共阴极七段数码管显示。答：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity counter is port(clk,clk1,en,clr:in std_logic; ledout:out std_logic_vector(6 downto 0); scanout,scanout1,co:out std_logic);end counter;architecture

2、a of counter issignal cnt:std_logic_vector(7 downto 0);signal led:std_logic_vector(6 downto 0);signal scan:std_logic;signal hex:std_logic_vector(3 downto 0);begin process(clk) begin if(clk'event and clk='1')then if en='1'then if clr='1'then cnt<=(others=>'0'

3、); else if cnt=""then cnt<="" co<='1' else cnt<=cnt+'1' co<='0' end if; end if; end if; end if; end process;process(clk1) begin if clk1'event and clk1='1'then scan<=not scan; end if;Scanout=scan;Scanout1=not scan;end process;ledo

4、ut<=not led;hex<=cnt(7 downto 4) when scan='1'else cnt(3 downto 0);with hex selectled<=""when"0001", ""when"0010", ""when"0011", ""when"0100", ""when"0101", ""when"0110

5、", ""when"0111", ""when"1000", ""when"1001", ""when"1010", ""when"1011", ""when"1100", ""when"1101", ""when"1110", ""when&quo

6、t;1111", ""when others;end a;2、 设计一个带计数使能、同步复位、带进位输出的增1二十进制计数器，计数结果由共阴极七段数码管显示。答：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity counter isport(clk,clk1,en,clr:in std_logic; co,scanout:out std_logic; ledout:out std_logic_vector(6 downto 0);end counter;a

7、rchitecture rtl of counter is signal cnt:std_logic_vector(7 downto 0); signal led:std_logic_vector(6 downto 0); signal scan:std_logic; signal hex:std_logic_vector(3 downto 0);begin process(clk,clr) begin if clr='1'then cnt<=(others=>'0'); elsif clk'event and clk='1'

8、 then if en='1'then if cnt=""then cnt<="" co<='0' elsif cnt=""then -注意此处，前面跳过了A到F的计数,所以计数到11001 cnt<="" co<='1' else cnt<=cnt+'1' co<='0' end if; end if; end if; end process; process(clk1) begin if clk1

9、'event and clk1='1'then scan<=not scan; end if; end process; ledout<=not led; scanout<=scan; hex<=cnt(7 downto 4) when scan='1'else cnt(3 downto 0); with hex select led<=""when"0001", ""when"0010", ""when"0011&

10、quot;, ""when"0100", ""when"0101", ""when"0110", ""when"0111", ""when"1000", ""when"1001", ""when"0000", ""when others;end rtl;3、 设计一个带计数使能、异步复位、同步装载的

11、可逆七位二进制计数器，计数结果由共阴极七段数码管显示。答：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity counter isport(clk,clks,clr,en,stdl,dir:in std_logic; din:in std_logic_vector(6 downto 0); ledout:out std_logic_vector(6 downto 0); scanout:out std_logic);end counter;architecture a of counte

12、r is signal cnt:std_logic_vector(6 downto 0); signal hex:std_logic_vector(3 downto 0); signal led:std_logic_vector(6 downto 0); signal scan:std_logic;begin process(clk) begin if(clk'event and clk='1')then if clr='1'then cnt<=(others=>'0'); elsif stdl='0'then

13、 cnt<=din; elsif en='1'then if dir='1'then cnt<=cnt+'1' else cnt<=cnt-'1' end if; end if; end if; end process; process(clks) begin if(clks'event and clks='1')then scan<=not scan; end if; end process; scanout<=scan; ledout<=not led; hex<

14、;='0'&cnt(6 downto 4)when scan='1' else cnt(3 downto 0); with hex select led<=""when"0001", ""when"0010", ""when"0011", ""when"0100", ""when"0101", ""when"0110&qu

15、ot;, ""when"0111", ""when"1000", ""when"1001", ""when"1010", ""when"1011", ""when"1100", ""when"1101", ""when"1110", ""when"1

16、111", ""when others;end a;4、 设计一个带计数使能、同步复位、异步装载、可逆计数的通用计数器。计数结果由共阴极七段数码管显示。答：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY counter IS GENERIC (count_value:INTEGER:=9);PORT(clk,clr,en,load,dir:IN STD_LOGIC; data_in:IN INTEGER RANGE 0 TO count_value; l

17、edout:OUT STD_LOGIC_VECTOR(6 DOWNTO 0);END counter;ARCHITECTURE a OF counter IS SIGNAL cnt:INTEGER RANGE 0 TO count_value; SIGNAL led:STD_LOGIC_VECTOR(6 DOWNTO 0);BEGIN PROCESS(load,clk) BEGIN IF load='1' THEN cnt<=data_in; elsif clr='1' THEN cnt<=0; ELSIF (clk'EVENT AND cl

18、k='1')THEN IF en='1' THEN IF dir='1' THEN IF cnt=count_value THEN cnt<=0; ELSE cnt<=cnt+1; end if; else IF cnt=0 THEN cnt<=count_value; else cnt<=cnt-1; end if; end if; end if; end if; END PROCESS; ledout<=NOT led; WITH cnt SELECT led<=""WHEN 1, &q

19、uot;"WHEN 2, ""WHEN 3, ""WHEN 4, ""WHEN 5, ""WHEN 6, ""WHEN 7, ""WHEN 8, ""WHEN 9, ""WHEN 0, ""WHEN others;END a;5、 设计一个具有16分频、8分频、4分频和2分频功能的多用分频器。答：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LO

20、GIC_UNSIGNED.ALL;ENTITY div4 ISPORT(clk:IN STD_LOGIC; din:IN STD_LOGIC_VECTOR(3 DOWNTO 0); fout:OUT std_LOGIC);END div4;ARCHITECTURE a OF div4 ISbegin process(clk) variable cnt:std_logic_vector(3 downto 0); begin if(clk'event and clk='1') then if cnt="1111" then cnt:="0000

21、" else cnt:=cnt+'1' end if; if din="0000" then fout<=cnt(3); elsif din="1000" then fout<=cnt(2); elsif din="1100" then fout<=cnt(1); elsif din="1110" then fout<=cnt(0); else fout<='1' end if; end if; end process;end a;6、 设计一

22、个正负脉宽相等的通用分频器。答：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY div ISGENERIC (num:INTEGER:=2);PORT (clk:IN STD_LOGIC; co:OUT STD_LOGIC);END div;ARCHITECTURE rtl OF div ISBEGIN PROCESS(clk) VARIABLE cnt:STD_LOGIC_VECTOR(num downto 0); BEGIN IF(clk'event and clk=&#

23、39;1')THEN cnt:=cnt+'1' END IF; co<=cnt(num); END PROCESS;END rtl;7、 根据需要设计一个多用分频器：可以控制实现四种分频形式：第一种：5分频第二种：8分频第三种：15分频第四种：16分频答：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity fenpin isport(clk:in std_logic; en:in std_logic_vector(1 downto 0); cout:out

24、std_logic; ledout:out std_logic_vector(6 downto 0);end fenpin;architecture dgnfenpin of fenpin is signal led:std_logic_vector(6 downto 0);signal hex:std_logic_vector(3 downto 0);beginprocess(clk) variable cnt:std_logic_vector(3 downto 0)=”0000”;begin if(clk'event AND clk='1')then if(en=&

25、quot;00")then if(cnt>="0101")then cnt:="0000" else cnt:=cnt+'1' end if; cout<=cnt(2); elsif(en="01")then if(cnt>="1000")then cnt:="0000" cout<='1' else cnt:=cnt+'1' cout<='0' end if; elsif(en="

26、10")then if(cnt>="1110")then cnt:="0000"cout<='1' else cnt:=cnt+'1'cout<='0' end if; else if(cnt>="1111")then cnt:="0000" else cnt:=cnt+'1' end if; cout<=cnt(3); end if;end if;end process; with en select led&

27、lt;=""when"00", ""when"01", ""when"10", ""when"11", ""when others;ledout<=led;end dgnfenpin;8、 设计一个M序列发生器，M序列为“”library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity xulie isport(cl

28、k:in std_logic; fout:out std_logic);end xulie;architecture fashengqi of xulie issignal cnt:std_logic_vector(2 downto 0);beginprocess(clk)beginif(clk'event AND clk='1')then if(cnt="111")then cnt<="000" else cnt<=cnt+'1' end if;end if;end process;with cnt

29、select fout<='1'when"000", '1'when"001", '1'when"010", '1'when"011", '0'when"100", '1'when"101", 0when “110”,1when”111”, 0'when others;end fashengqi;9、 设计一个彩灯控制器，彩灯共有16个，每次顺序点亮相邻的四个彩灯，如

30、此循环执行，循环的方向可以控制。答：library ieee;use ieee.std_logic_1164.all;entity caideng isport( rl,clk:in std_logic;ledout:out std_logic_vector(15 downto 0);end caideng;architecture a of caideng issignal led:std_logic_vector(15 downto 0);signal k:std_logic;beginprocess(clk)beginif(clk'event and clk='1'

31、;)then if(k='0')then led<=(0=>1,1=>1,2=>1,3=>1,others=>'0'); elsif(rl='1')then led<=led(14 downto 0)&led(15); elsif(rl='0')then led<=led(0)&led(15 downto 1); end if;end if;ledout<=led;end process;end a;10、 设计一个具有左移、右移控制，同步并行装载和串行装载的8

32、位串行移位寄存器LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY shifter1 ISPORT(clk,clr,ser,dir,stld:IN STD_LOGIC;din: IN STD_LOGIC_VECTOR(0 TO 7) ;qh:OUT STD_LOGIC);END shifter1;ARCHITECTURE rt1 OF shifter1 ISSIGNAL reg:STD_LOGIC_VECTOR(0 TO 7);beginprocess(clk,clr)beginif clr='1' thenreg<=(othe

33、rs=>'0');elsif clk'event and clk='1'then if stld='0'then reg<=din; else if(dir='0')then reg<=reg(1 to 7)&ser;qh<=reg(0); else reg<=ser&reg(0 to 6);qh<=reg(7); end if;end if;end if;end process;end rt1;11、 设计一个9人表决电路，参加表决者为9人，同意为1，不同意为0，同意者

34、过半则表决通过，绿指示灯亮，表决不通过则红指示灯亮。数码管显示赞成人数。library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity selector isport(a:in std_logic_vector(8 downto 0);clr:in std_logic; red,gree:out std_logic; ledout:out std_logic_vector(6 downto 0);end selector;architecture rtl of selector is signal

35、led:std_logic_vector(6 downto 0); signal count:std_logic_vector(3 downto 0);beginprocess(a)variable cnt:std_logic_vector(3 downto 0);begincnt:=”0000”;for i in 0 to 8 loop if a(i)=1then cnt:=cnt+1; end if;end loop; if(cnt>=”0101”and cnt<=”1001”)then gree<=1;red<=0; elsif(cnt>=”0000”and

36、 cnt<=”0100”)thengree<=0;red<=1; end if;count<=cnt;end process;ledout<=not led;with count selectled<=""when"0001",""when"0010",""when"0011",""when"0100",""when"0101",""when

37、"0110",“”when”0111”,“”when”1000”,“”when”1001”,""when others;end rtl;12、 设计一个同步复位，异步并行装载的8位串行左移移位寄存器LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;Entity exam13 isPort(clk,clr,ser,stld:in std_logic;Din:in std_logic_vector(0 to 7);Qh:out std_logic);End exam13;Architecture rtl of exam13 i

38、sSignal reg:std_logic_vector(0 to 7);BeginProcess(clk,stld)Begin If stld=1 thenReg<=din; Elsif clkevent and clk=1 thenIf clr=1 then Reg<=(others>=0);Elsif(stld=0)then Reg<=reg(1 to 7)&ser;End if; End if;End process;Qh<=reg(0);End rtl;13、 有16个开关，编号为0到15，编号0的优先级最高。当某一个拨码开关为1时由共阴极七段数

39、码管显示其编号（可用16进制数显示，亦可用十进制显示）答：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY bhxs ISPORT(INPUT:IN STD_LOGIC_VECTOR(15 DOWNTO 0); LEDOUT: out STD_LOGIC_VECTOR(6 DOWNTO 0);END bhxs;ARCHITECTURE RT1 OF bhxs IS SIGNAL LED:STD_LOGIC_VECTOR(6 DOWNTO 0);BEGIN process(INPUT)

40、begin LEDOUT<=NOT LED; IF(INPUT(0)='1')then LED<="" ELSIF(INPUT(1)='1')then LED<="" ELSIF(INPUT(2)='1')then LED<="" ELSIF(INPUT(3)='1')then LED<="" ELSIF(INPUT(4)='1')then LED<="" ELSIF(INPUT(

41、5)='1')then LED<="" ELSIF(INPUT(6)='1')then LED<="" ELSIF(INPUT(7)='1')then LED<="" ELSIF(INPUT(8)='1')then LED<="" ELSIF(INPUT(9)='1')then LED<="" ELSIF(INPUT(10)='1')then LED<="

42、" ELSIF(INPUT(11)='1')then LED<="" ELSIF(INPUT(12)='1')then LED<="" ELSIF(INPUT(13)='1')then LED<="" ELSIF(INPUT(14)='1')then LED<="" ELSIF(INPUT(15)='1')then LED<="" END IF; END PROCESS;END

43、 RT1;14、 设计一个全自动洗衣机水位控制器。 要求：当水位超过某一上限值时，停止加水，启动洗衣机；当水位低于某一下限值时，加水，停止洗衣机；否则启动洗衣机，停止加水。LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;Entity washer isPort(clk,water_high,water_low:in std_logic;Jiashui,qidong:out std_logic);End washer;Architecture style of washer is Type state is(just_right,too_high,too_low

44、); Signal now_state,next_state:state;Begin Process(now_state,water_high,water_low) Begin Case now_state is When just_right=>jiashui<=0;qidong<=1; If water_low=1then next_state<=too_low; Elsif water_high=1then next_state<=too_high; Else next_state<=just_right; End if; When too_low=&

45、gt;jiashui<=1;qidong<=0; If water_low=1then next_state<=too_low; Elsif water_high=1then next_state<=too_high; Else next_state<=just_right; End if; When too_high=>jiashui<=0;qidong<=1; If water_low=1then next_state<=too_low; Elsif water_high=1then next_state<=too_high; E

46、lse next_state<=just_right; End if; End case, End process;Process(clk) Begin If(clkevent and clk=1)then Now_state<=next_state; End if; End process;End style;15、 根据真值表设计一位全加器，然后用结构的描述方法设计一个8位加法器。LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY full_adder ISPORT(a,b,cin:IN STD_LOGIC; s,co:OUT STD

47、_LOGIC);END full_adder;ARCHITECTURE full1 of full_adder isSIGNAL comb:STD_LOGIC_VECTOR(2 downto 0);BEGIN comb<=a&b&cin;PROCESS(comb)BEGINIF(comb="000")then s<='0'co<='0'elsif(comb="001")then s<='1'co<='0'elsif(comb="100&

48、quot;)then s<='1'co<='0'elsif(comb="010")then s<='1'co<='0'elsif(comb="011")thens<='0'co<='1'elsif(comb="101")thens<='0'co<='1'elsif(comb="110")thens<='0'co<=

49、'1'elses<='1'co<='1'end if;end process;end full1;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity full_adder8 isport(clk,cin:in std_logic; x,y:in std_logic_vector(7 downto 0); ledout:out std_logic_vector(6 down

50、to 0);scan_out:out std_logic_vector(1 downto o); co:out std_logic);end full_adder8;architecture stru of full_adder8 iscomponent full_adderport(a,b,cin:in std_logic; s,co:out std_logic);end component; signal z:std_logic_vector(6 downto 0);signal sum:std_logic_vector(7 downto 0);signal scan:std_logic_

51、vector(1 downto 0);signal hex:std_logic_vector(3 downto 0);signal led:std_logic_vector(6 downto 0);beginuo:full_adder port map(x(0),y(0),cin,sum(0),z(0);u1:full_adder port map(x(1),y(1),z(0),sum(1),z(1);u2:full_adder port map(x(2),y(2),z(1),sum(2),z(2);u3:full_adder port map(x(3),y(3),z(2),sum(3),z(

52、3);u4:full_adder port map(x(4),y(4),z(3),sum(4),z(4);u5:full_adder port map(x(5),y(5),z(4),sum(5),z(5);u6:full_adder port map(x(6),y(6),z(5),sum(6),z(6);u7:full_adder port map(x(7),y(7),z(6),sum(7),co);scan_out<=scan;ledout<=not led;process(clk)begin if(clkevent and clk=1)then if scan=”10” the

53、n scan<=”01”; else scan<=”10”; end if; end if;end process;hex<=sum(7 downto 4)when scan=”10” else sum(3 downto 0);with hex selectled<=”when”0000”, “”when”0001”, “”when”0010”, “”when”0011”, “”when”0100”, “”when”0101”, “”when”0110”, “”when”0111”, “”when”1000”, “”when”1001”, “”when”1010”, “

54、”when”1011”, “”when”1100”, “”when”1101”, “”when”1110”, “”when”1111”, “XXXXXXX”when others;End stru;16、 设计6位二进制数到BCD码（8421码）的转换器。结果由共阴极数码管显示。LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;use ieee.std_logic_unsigned.all;ENTITY trans ISPORT( scanclk:IN STD_LOGIC; shu:IN STD_LOGIC_VECTOR(5 DOWNTO 0); ledout:

55、OUT STD_LOGIC_VECTOR(6 DOWNTO 0); scanout:out integer range 0 to 1);END trans;ARCHITECTURE rtl OF trans IS signal yh,yl:integer range 0 to 9; signal scan:integer range 0 to 1; signal led:std_logic_vector(6 downto 0); signal y,hex:integer range 0 to 63;BEGIN y<=conv_integer(shu); yh<=1 when y&g

56、t;=10 and y<20 else2 when y>=20 and y<30 else3 when y>=30 and y<40 else4 when y>=40 and y<50 else5 when y>=50 and y<60 else6 when y>=60 and y<64 else 0; yl<=(y-0) when y>=0 and y<10 else (y-10)when y>=10 and y<20 else(y-20)when y>=20 and y<30 els

57、e(y-30)when y>=30 and y<40 else(y-40)when y>=40 and y<50 else(y-50)when y>=50 and y<60 else(y-60)when y>=60 and y<70 else0; process(scanclk) begin if(scanclk'event and scanclk='1')then if scan=1 then scan<=0; else scan<=1; end if; end if; end process; with s

58、can select hex<=yh when 1, yl when others; ledout<=not led; scanout<=scan; with hex select led<=""when 1, ""when 2, ""when 3, ""when 4, ""when 5, ""when 6, ""when 7, ""when 8, ""when 9, ""

59、when 0,“”when others;END rtl; 17、 设计一个跑马灯控制器。一共有8个彩灯，编号为LED0LED7，点亮方式为：先从左往右顺序点亮，然后从右往左，如此循环往复。答：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY lighten IS PORT( CLK:IN STD_LOGIC; ledout:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);END lighten;ARCHITECTURE b OF lighten ISSIGNAL c

60、nt:STD_LOGIC_VECTOR(3 DOWNTO 0);BEGIN PROCESS(CLK) BEGIN IF(CLK'EVENT AND CLK='1')THEN IF (cnt="1110")THEN cnt<="0000" ELSE cnt<=cnt+'1' END IF; END IF; END PROCESS;WITH cnt SELECTledout<= ""WHEN"0000", ""WHEN"0001&q

61、uot;, ""WHEN"0010", ""WHEN"0011", ""WHEN"0100", ""WHEN"0101", ""WHEN"0110", ""WHEN"0111", ""WHEN"1000", ""WHEN"1001", ""WHEN"

62、1010", ""WHEN"1011", ""WHEN"1100", ""WHEN"1101", ""WHEN"1110", ""WHEN OTHERS;END b; 10位的LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY lighten IS PORT( CLK:IN STD_LOGIC; le

63、dout:OUT STD_LOGIC_VECTOR(9 DOWNTO 0);END lighten;ARCHITECTURE b OF lighten ISSIGNAL cnt:STD_LOGIC_VECTOR(4 DOWNTO 0);BEGIN PROCESS(CLK) BEGIN IF(CLK'EVENT AND CLK='1')THEN IF (cnt="10010")THEN cnt<="00000" ELSE cnt<=cnt+'1' END IF; END IF; END PROCESS;WITH cnt SELECTledout<=