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电动助力车电机驱动系统设计说明书含开题及程序文件

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1-4244-1253-6/07/$25.00 2007 IEEE Proceedings of HDP07 Design of PWM Controller in a MCS-51 Compatible MCU Yue-Li Hu, Wei Wang Microelectronic Research & Development Center, Key Laboratory of Advanced Display and System Applications (Shanghai University), Ministry of Education Campus P.O.B.221, 149 Yanchang Rd, Shanghai 200072, China E-mail: Abstract This paper presents a design of Pulse-Width Modulated (PWM) controller module in a MCU based on MCS-51 structure. The design can generate 2-channel programmable periodic PWM signals. These output PWM signals from MCU can be used for a variety of applications including motor control. The function of the design allows users to select independent or complementary inversion timing relationships between 2 PWM wave forms. The latter mode selection also includes optional dead time function to support driving H-bridges and inverters. Therefore, users can control the output PWM signals through setting the duty-cycle registers. After the successful simulation at the front end, practical experiments made on a NIOS development board verify the design. 1. Introduction PWM technology is a kind of voltage regulation method by controlling the switch frequency of DC power with fixed voltage to modify the two-end voltage of load. This technology can be used for a variety of applications including motor control, temperature control and pressure control and so on. In the motor control system shown as Fig. 1, through adjusting the duty cycle of power switch, the speed of motor can be controlled. As shown in Fig. 2, under the control of PWM signal, the average of voltage that controls the speed of motor changes with Duty-cycle ( D = t1/T in this Figure ), thus the motor speed can be increased when motor power turn on, decreased when power turn off. Fig.1 PWM control block diagram Fig. 2: The Relationship between Voltage of Armature and Duty-cycle Therefore, the motor speed can be controlled with regularly adjusting the time of turn-on and turn-off. There are three methods could achieve the adjustment of duty cycle: (1) Adjust frequency with fixed pulse-width. (2) Adjust both frequency and pulse-width. (3) Adjust pulse-width with fixed frequency. Generally, there are four methods to generate the PWM signals as the following: (1) Generated by the device composed of separate logic components. This method is the original method which now has been discarded. (2) Generated by software. This method need CPU to continuously operate instructions to control I/O pins for generating PWM output signals, so that CPU can not do anything other. Therefore, the method also has been discarded gradually. (3) Generated by ASIC. The ASIC makes a decrease of CPU burden and steady work generally has several functions such as over-current protection, dead-time adjustment and so on. Then the method has been widely used in many kinds of occasion now. (4) Generated by PWM function module of MCU. Through embedding PWM function module in MCU and initializing the function, PWM pins of MCU can also automatically generate PWM out signals without CPU controlling only when need to change duty-cycle. It is the method that will be implemented in this paper. In this paper, we propose a PWM module embedded in a 8051 microcontroller. The PWM module can support PWM pulse signals by initializing the control register and duty-cycle register with three methods just mentioned above to adjust the duty cycle and several operation modes to add flexibility for user. The following section explains the architecture of the PWM module and the architectures of basic functional blocks. Section3 describes two operation modes. Experimental and simulation results verifying proper system operation are also shown in that section. Depending on mode of operation, the PWM module creates one or more pulse-width modulated signals, whose duty ratios can be independently adjusted. 2. Implementation of PWM module in MCU 2.1 Overview of the PWM module A block diagram of PWM module is shown in Fig.3. It is clearly from the diagram that the whole module is composed of two sections: PWM signal generator and dead-time generator with channel select logic. The PWM function can be started by the user through implementing some instructions for initializing the PWM module. In particular, the following power and motion control applications are supported: DC Motor Uninterruptablel Power Supply (UPS) Proceedings of HDP07 Fig.3 Architecture of PWM Module The PWM module also has the following features: Two PWM signal outputs with complementary or independent operation Hardware dead-time generators for complementary mode Duty cycle updates are configurable to be immediated or synchronized to the PWM 2. 2 Details of the architecture 2.2.1 PMW generator The architecture of the 2-output PWM generator shown in Fig.3 is based on a 16-bit resolution counter which creates a pulse-width modulated signal. The system is synthesized by a system clock signal whose frequency can be divided by 4 times or 12 times through setting the value of T3M for PWM0 or T4M for PWM1 in the special register PWMCON as shown in Fig.4. To PWM0 generator, the clock to 16-bit counter will be pre-divided by 4 times by default when T3M is set to zero. And the clock will be divided by 12 times when T3M is set to 1. This is also true for PWM1. The other bits in PWMCON are explained in detail in Table 1. Fig .4 Bit Mapping of PWMCON Table 1: The Bit Definition in PWMCON BIT Description TF4 Interrupt Request for PWM0 TR4 RUN bit for PWM0 TF3 Interrupt Request for PWM1 TR3 RUN bit for PWM1 PSEL Channel Select in Complementary Mode CPWM Mode Select T4M Clock Prescaler for PWM1 T3M Clock Prescaler for PWM0 2.2.2 Channel-select logic The follow Fig. 5 shows the channel-select logic which is useful in Complementary Mode. From this diagram, it is clear to know that signal CP and CPWM control the source of PWMH and PWML. And the details about the two control signals will be discussed in the section 3, and the architecture of dead-time generator will also be discussed in section 3.1 for the continuity of Complementary Mode. Fig. 5 Diagram of Channel-select Logic 3. Operation Mode and Simulation Results The design has two operation modes: Independent Mode and Complimentary Mode. By setting the corresponding bit CPWM in register PWMCON shown in Fig. 4, user can select one of the two operation modes. When CPWM is set to zero, PWM module will work in Independent Mode, whereas, PWM module will work in Complimentary Mode. In the following of this section, the two operation mode will be explained respectively in detail and the simulation results of the PWM module from the Synoposys VCS EDA platform which verify the design will also be shown. 3.1 Independent PWM Output Mode An Independent PWM Output mode is useful for driving loads such as the one shown in Figure 1. A particular PWM output is in the Independent Output mode when the corresponding CP bit in the PWMCON register is set to zero. In this case, two-channel PWM outputs are independent of each other. The signal on pin PWM0/PWMH is from PWM0 generator, and the signal on pin PWM1/PWML is from PWM0 generator. The separate case is achieved by the channel-select logic shown in Fig. 6. The PWM I/O pins are set to independent mode by default upon advice reset. The dead-time generator is disabled in the Independent mode. The simulation result is shown in Figure 4 as the following Fig.5. Tr4 and tr3 are run bits to PWM0 and PWM1, respectively. Actually, from this diagram, Pin P15/ P14 of MCU is used for PWMH/ PWML or normal I/O ,alternatively. Fig.6 the Waveform of PWM Outputs in Independent Mode 3.2 Complementary PWM Output Mode The Complementary Output mode is used to drive inverter loads similar to the one shown in Figure 7. This inverter topology is typical for DC applications. In Complementary Output Mode, the pair of PWM outputs cannot be active simultaneously. The PWM channel and output pin pair are internally configured through channel-select logic as shown in Figure 5. A dead-time may be optionally inserted during device switching where both outputs are inactive for a short period. Proceedings of HDP07 Fig 7: Typical Load for Complementary PWM Outputs The Complementary mode is selected for PWM I/O pin pair by setting the appropriate CPWM bit in PWMCON. In this case, PSEL is in effect. PWMH and PWML will come from PWM0 generator when PSEL is set to zero, when the signals from PWM1 generator is useless, whereas PWMH and PWML will come from PWM1 generator when PSEL is set to 1, when the signals from PWM0 generator is useless. In the process of producing the PWM outputs in Complementary Mode, the dead-time will be inserted to be discussed in the following section. 3.3 Dead-time Control Dead-time generation is automatically enabled when PWM I/O pin pair is operating in the Complementary Output mode. Because the power output devices cannot switch instantaneously, some amount of time must be provided between the turn-off event of one PWM output in a complementary pair and the turn-on event of the other transistor. The 2-output PWM module has one programmable dead-time with 8-bit register. The complementary output pair for the PWM module has an 8-bit down counter that is used to produce the dead-time insertion. As shown in Figure 8, the dead time unit has a rising and falling edge detector connected to PWM signal from one of PWM generator. The dead times is loaded into the timer on the detected PWM edge event. Depending on whether the edge is rising or falling, one of the transitions on the complementary outputs is delayed until the timer counts down to zero. A timing diagram indicating the dead time insertion for the pair of PWM outputs is shown in Figure 8. Fig.8 Dead-time Unit Block Diagram Fig. 9 the Waveforms of PWM Outputs in Complementary Mode Conclusions In this paper, we have designed PWM module based on an 8-bit MCU compatible with 8051 family. The design can generate 2-channel programmable periodic PWM signals with two operation mode, Independent Mode and Complementary Mode in which dead-time will be inserted. The simulation results on the EDA platform have proven its correctness and usefulness. Acknowledgments The authors would like to thank Shanghai Leading Academic Discipline Project (Project Number: T0103) for the financial support. References 1. Xiang hui-fang and Hu yue-li, Computer measurement and control, 14(7) p. 942(2
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