第六讲VHDL复杂电路描述方法ppt课件

1、第六讲 复杂电路的描述方法;VHDL for SpecificationVHDL for SimulationVHDL for Synthesis;Levels of design descriptionAlgorithmic levelRegister Transfer LevelLogic (gate) levelCircuit (transistor) levelPhysical (layout) levelLevel of description most suitable for synthesis;Register Transfer Logic (RTL) Design Descr

2、iption Combinational Logic Combinational LogicRegistersTodays Topic;VHDL Design StylesComponents andinterconnectsstructuralVHDL Design StylesdataflowConcurrent statementsbehavioral Registers State machines Test benchesSequential statementsSubset most suitable for synthesis VHDLVHDL的执行语句的执行语句描述结构体中电路

3、硬件的变化特点；描述结构体中电路硬件的变化特点；结构体中的任何执行语句都是并行语句；结构体中的任何执行语句都是并行语句；并行语句的种类有：并行语句的种类有：赋值类语句：数据流描述赋值类语句：数据流描述 ( (逻辑函数的运算逻辑函数的运算) )元件类语句：结构描述元件类语句：结构描述 （逻辑符号的连接）（逻辑符号的连接）进程语句：行为描述进程语句：行为描述 （电路功能的流程）（电路功能的流程）;XOR3 Example;Entity (XOR3 Gate)entity XOR3 is port( A : in STD_LOGIC; B : in STD_LOGIC; C : in STD_LOG

4、IC; RESULT : out STD_LOGIC );end XOR3;Dataflow Architecture (XOR3 Gate)architecture XOR3_DATAFLOW of XOR3 issignal U1_OUT: STD_LOGIC;begin U1_OUT=A xor B;RESULT A, I2 = B, Y = U1_OUT); U2: XOR2 port map (I1 = U1_OUT, I2 = C, Y = RESULT);end XOR3_STRUCTURAL;I1I2YXOR2ABCRESULTU1_OUTXOR3ABCRESULTXOR3;B

5、ehavioral Architecture (XOR Gate)architecture XOR3_BEHAVIORAL of XOR3 isbeginXOR3_BEHAVE: process (A,B,C)beginif (A xor B xor C) = 1) thenRESULT = 1;elseRESULT = 0;end if;end process XOR3_BEHAVE;end XOR3_BEHAVIORAL;Dataflow Description Describes how data moves through the system and the various proc

6、essing steps. Data Flow uses series of concurrent statements to realize logic. Concurrent statements are evaluated at the same time; thus, order of these statements doesnt matter. Data Flow is most useful style when series of Boolean equations can represent a logic. ;Data-flow VHDL concurrent signal

7、 assignment () conditional concurrent signal assignment (when-else) selected concurrent signal assignment (with-select-when) generate scheme for equations (for-generate)Major instructionsConcurrent statements;Data-flow VHDL concurrent signal assignment () conditional concurrent signal assignment (wh

8、en-else) selected concurrent signal assignment (with-select-when) generate scheme for equations (for-generate)Major instructionsConcurrent statements;Data-flow VHDL: Example0 0 0 1 0 1 1 1 c i 1 + 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 c i x i y i 000111100 1 x i y i c i 1 1 1 1 s i x i y i

9、 c i = 000111100 1 x i y i c i 1 1 1 1 c i 1 + x i y i x i c i y i c i + + = c i x i y i s i c i 1 + (a) Truth table (b) Karnaugh maps (c) Circuit 0 1 1 0 1 0 0 1 s i ;Data-flow VHDL: ExampleLIBRARY ieee ;USE ieee.std_logic_1164.all ;ENTITY fulladd ISPORT (x, y, Cin: IN STD_LOGIC ; s, Cout: OUT STD_

10、LOGIC ) ;END fulladd ;ARCHITECTURE LogicFunc OF fulladd ISBEGINs = x XOR y XOR Cin ;Cout = (x AND y) OR (Cin AND x) OR (Cin AND y) ;END LogicFunc ;Logic Operators Logic operators Logic operators precedenceand or nand nor xor not xnor notand or nand nor xor xnorHighestLowest; Wanted: Y = ab + cdIncor

11、rectY = a and b or c and d equivalent toY = (a and b) or c) and d equivalent toY = (ab + c)dCorrectY = (a and b) or (c and d)No Implied Precedence ;Concatenationsignal A: STD_LOGIC_VECTOR(3 downto 0);signal B: STD_LOGIC_VECTOR(3 downto 0);signal C, D, E: STD_LOGIC_VECTOR(7 downto 0);A = ”0000”; B =

12、”1111”; C = A & B; - C = ”00001111”D = 0 & ”0001111”; - D = ”00001111”E = 0 & 0 & 0 & 0 & 1 & 1 & 1 & 1; - E = ”00001111”;Rotations in VHDLA(3)A(2)A(1)A(0)A(2) A(1)A(0)A(3)A1A_rotL = A(2 downto 0) & A(3);Arithmetic Functions in VHDL (1)To use basic arithmetic

13、operations involving std_logic_vectors you need to include thefollowing library packages:library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;Arithmetic Functions in VHDL (2)You can use standard +, - operatorsto perform addition and subtraction: signal A : STD_LOGIC_VECTOR(3 down

14、to 0); signal B : STD_LOGIC_VECTOR(3 downto 0); signal C : STD_LOGIC_VECTOR(3 downto 0); C = A + B;Data-flow VHDL concurrent signal assignment () conditional concurrent signal assignment (when-else) selected concurrent signal assignment (with-select-when) generate scheme for equations (for-generate)

15、Major instructionsConcurrent statements;Data Flow Instructions (1)target_signal = value1 when condition1 else value2 when condition2 else . . . valueN-1 when conditionN-1 else valueN;When - Else.Value NValue N-1Condition N-1Condition 2Condition 1Value 2Value 1Target Signal;Operators Relational opera

16、tors Logic and relational operators precedence= /= = not= /= =and or nand nor xor xnorHighestLowest; compare a = bcIncorrect when a = b and c else equivalent to when (a = b) and c else Correct when a = (b and c) else Priority of logic and relational operators ;Data-flow VHDL concurrent signal assign

17、ment () conditional concurrent signal assignment (when-else) selected concurrent signal assignment (with-select-when) generate scheme for equations (for-generate)Major instructionsConcurrent statements;Data Flow Instructions (2)with choice_expression select target_signal = expression1 when choices1,

18、 expression2 when choices2, . . . expressionN when choicesN;With - Selectchoices1choices2choicesNexpression1target_signalchoice expressionexpression2expressionN;MLU Example;MLU: Block DiagramBANEG_ANEG_BIN0IN1IN2IN3OUTPUTSEL1SEL0MUX_4_1L0L1NEG_YYY1A1B1MUX_0MUX_1MUX_2MUX_3;MLU: Entity Declarationlibr

19、ary IEEE;use IEEE.STD_LOGIC_1164.all;entity MLU is port( NEG_A : in STD_LOGIC; NEG_B : in STD_LOGIC; NEG_Y : in STD_LOGIC; A : in STD_LOGIC; B : in STD_LOGIC; L1 : in STD_LOGIC; L0 : in STD_LOGIC; Y : out STD_LOGIC );end MLU;MLU: Architecture Declarative Sectionarchitecture MLU_DATAFLOW of MLU issig

20、nal A1:STD_LOGIC;signal B1:STD_LOGIC;signal Y1:STD_LOGIC;signal MUX_0:STD_LOGIC;signal MUX_1:STD_LOGIC;signal MUX_2:STD_LOGIC;signal MUX_3:STD_LOGIC;signal L: STD_LOGIC_VECTOR(1 downto 0);MLU - Architecture BodybeginA1= not A when (NEG_A=1) elseA;B1= not B when (NEG_B=1) else B;Y = not Y1 when (NEG_

21、Y=1) elseY1;MUX_0 = A1 and B1;MUX_1 = A1 or B1;MUX_2 = A1 xor B1;MUX_3 = A1 xnor B1; L=L1 & L0;with (L) select Y1 = MUX_0 when 00, MUX_1 when 01, MUX_2 when 10, MUX_3 when others;end MLU_DATAFLOW;Data-flow VHDL concurrent signal assignment () conditional concurrent signal assignment (when-else)

22、selected concurrent signal assignment (with-select-when) generate scheme for equations (for-generate)Major instructionsConcurrent statements;PARITY Example;PARITY: Block Diagram;For Generate StatementFor Generatename: for parameter_specification generate Declaration Statements begin Concurrent State

23、ments end generate name;PARITY: Entity Declarationlibrary IEEE;use IEEE.STD_LOGIC_1164.all;entity PARITY is port( Parity_in : in STD_LOGIC_VECTOR(7 downto 0); Parity_out : out STD_LOGIC );end PARITY;PARITY: Block DiagramXor_out(1)Xor_out(2)Xor_out(3)Xor_out(4)Xor_out(5)Xor_out(6)Xor_out(7);PARITY: A

24、rchitecturearchitecture PARITY_DATAFLOW of PARITY is signal Xor_out: std_logic_vector (7 downto 1);beginXor_out(1) = Parity_in(0) xor Parity_in(1);G2: for i in 1 to 6 generateXor_out(i+1) = Xor_out(i) xor Parity_in(i+1);end generate G2; Parity_out B01 if AB1010 independently of A and B0101 independe

25、ntly of A and B11 (invalid inputs)-;ABX_OUTY_OUTBIT_COMPAREentity BIT_COMPARE is port(A, B, X_IN, Y_IN: in STD_LOGIC; X_OUT, Y_OUT: out STD_LOGIC);end BIT_COMPARE;X_INY_INBasic building block;X_IN & Y_INX_OUT & Y_OUT0000 if A=B10 if A=1 and B=001 if A=0 and B=11010 independently of A and B01

26、01 independently of A and B11 (invalid inputs)-Basic building block Truth Table;8-bit comparator - ArchitectureA(7) B(7)CMP_IN(1)CMP_IN(0)A(6) B(6)A(0) B(0)CMP_OUT(1)CMP_OUT(0)INT_X(7)INT_X(1)INT_Y(7)INT_Y(1)INT_X(6)INT_Y(6);architecture STRUCTURE of COMPARE8 is component BIT_COMPARE port(A, B, X_IN

27、, Y_IN: in STD_LOGIC; X_OUT, Y_OUT: out STD_LOGIC); end component; signal INT_X, INT_Y: STD_LOGIC_VECTOR(7 downto 1);begin C7: BIT_COMPARE port map(A(7), B(7), CMP_IN(1), CMP_IN(0), INT_X(7), INT_Y(7); C6: BIT_COMPARE port map(A(6), B(6), INT_X(7), INT_Y(7), INT_X(6), INT_Y(6); . . . C0: BIT_COMPARE

28、 port map(A(0), B(0), INT_X(1), INT_Y(1), CMP_OUT(0), CMP_OUT(1);end STRUCTURE;Architecture without for-generate;8-bit comparator - ArchitectureA(7) B(7)CMP_IN(1)CMP_IN(0)A(6) B(6)A(0) B(0)CMP_OUT(1)CMP_OUT(0)INT_X(7)INT_X(1)INT_Y(7)INT_Y(1)INT_X(8)INT_Y(8)INT_X(0)INT_Y(0);architecture STRUCTURE of

29、COMPARE8 is component BIT_COMPARE port(A, B, X_IN, Y_IN: in STD_LOGIC; X_OUT, Y_OUT: out STD_LOGIC); end component; signal INT_X, INT_Y: STD_LOGIC_VECTOR(8 downto 0);begin INT_X(8) = CMP_IN(1); INT_Y(8) = CMP_IN(0); CASCADE: for I in 7 downto 0 generate C: BIT_COMPARE port map(A(I), B(I), INT_X(I+1)

30、, INT_Y(I+1), INT_X(I), INT_Y(I); end generate; CMP_OUT(1) = INT_X(0); CMP_OUT(0) = INT_Y(0);end STRUCTURE;Architecture with for-generate;Structural VHDL component instantiation (port map) generate scheme for component instantiations (for-generate) component instantiation with generic (generic map,

31、port map)Major instructions;N-bit Comparator Entity declarationentity COMPAREN is generic(N: positive); - N width of operands port( A, B: in BIT_VECTOR(N-1 downto 0); CMP_IN: in BIT_VECTOR(1 downto 0); CMP_OUT: out BIT_VECTOR(1 downto 0);end COMPAREN;architecture STRUCTURE of COMPAREN is component B

32、IT_COMPARE port(A, B, X_IN, Y_IN: in STD_LOGIC; X_OUT, Y_OUT: out STD_LOGIC); end component; signal INT_X, INT_Y: STD_LOGIC_VECTOR(N downto 0);begin INT_X(N) = CMP_IN(1); INT_Y(N) = CMP_IN(0); CASCADE: for I in N-1 downto 0 generate C: BIT_COMPARE port map(A(I), B(I), INT_X(I+1), INT_Y(I+1), INT_X(I

33、), INT_Y(I); end generate; CMP_OUT(1) = INT_X(0); CMP_OUT(0) 16) port map(A = P1, B = P2, CMP_IN = SIG_IN, CMP_OUT = SIG_OUT );N-bit Comparator Instantiation;Behavioral Design Style;Behavioral VHDL (subset) process statement (process) sequential signal assignment ()Major instructionsSequential state

34、mentsGeneralRegisters, counters, shift registers, etc. if-then-else statementState machines case-when statementTestbenches loops (for-loop, while-loop) ;Anatomy of a Processlabel: process (sensitivity list) declaration partbegin statement partend process;OPTIONAL; A process can be given a unique nam

35、e using an optional LABEL This is followed by the keyword PROCESS The keyword BEGIN is used to indicate the start of the process All statements within the process are executed SEQUENTIALLY. Hence, order of statements is important. A process must end with the keywords END PROCESS.TESTING: process beg

36、inTEST_VECTOR=“00”;wait for 10 ns;TEST_VECTOR=“01”;wait for 10 ns;TEST_VECTOR=“10”;wait for 10 ns;TEST_VECTOR=“11”;wait for 10 ns;end process; A process is a sequence of instructions referred to as sequential statements.What is a PROCESS?The Keyword PROCESS;PROCESS with a SENSITIVITY LIST List of si

37、gnals to which the process is sensitive. Whenever there is an event on any of the signals in the sensitivity list, the process fires. Every time the process fires, it will run in its entirety. WAIT statements are NOT ALLOWED in a processes with SENSITIVITY LIST.label: process (sensitivity list) decl

38、aration part begin statement part end process; ;Processes in VHDL Processes Describe Sequential Behavior Processes in VHDL Are Very Powerful Statements Allow to define an arbitrary behavior that may be difficult to represent by a real circuit Not every process can be synthesized Use Processes with C

39、aution in the Code to Be Synthesized Use Processes Freely in Testbenches;Use of Processes in the Synthesizable Code;Component Equivalent of a Process All signals which appear on the left of signal assignment statement (=) are outputs e.g. y, z All signals which appear on the right of signal assignme

40、nt statement (=) or in logic expressions are inputs e.g. w, a, b, c All signals which appear in the sensitivity list are inputs e.g. clk Note that not all inputs need to be included in the sensitivity listpriority: PROCESS (clk)BEGINIF w(3) = 1 THENy = 11 ;ELSIF w(2) = 1 THEN y = 10 ;ELSIF w(1) = c

41、THENy = a and b;ELSEz = 00 ;END IF ;END PROCESS ;wayzprioritybcclk;Registers;Clock D 0 1 1 0 1 0 1 Truth table Graphical symbolt 1 t 2 t 3 t 4 TimeClock D Q Timing diagramQ(t+1)Q(t)D latchD Q Clock ;Clk D 0 1 0 1 Truth table t 1 t 2 t 3 t 4 TimeClock D Q Timing diagramQ(t+1)Q(t)D flip-flopD Q Clock

42、Graphical symbol0 Q(t)1 ;LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY latch IS PORT ( D, Clock : IN STD_LOGIC ; Q : OUT STD_LOGIC) ; END latch ;ARCHITECTURE Behavior OF latch IS BEGINPROCESS ( D, Clock ) BEGINIF Clock = 1 THEN Q = D ; END IF ; END PROCESS ; END Behavior; D latchD Q Clock ;LIB

43、RARY ieee ; USE ieee.std_logic_1164.all ; ENTITY flipflop IS PORT ( D, Clock : INSTD_LOGIC ; Q: OUT STD_LOGIC) ; END flipflop ;ARCHITECTURE Behavior_1 OF flipflop IS BEGINPROCESS ( Clock ) BEGIN IF ClockEVENT AND Clock = 1 THEN Q = D ; END IF ; END PROCESS ; END Behavior_1 ; D flip-flopD Q Clock ;LI

44、BRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY flipflop IS PORT ( D, Clock : INSTD_LOGIC ; Q: OUT STD_LOGIC) ; END flipflop ;ARCHITECTURE Behavior_2 OF flipflop IS BEGINPROCESSBEGIN WAIT UNTIL ClockEVENT AND Clock = 1 ; Q = D ; END PROCESS ; END Behavior_2 ; D flip-flopD Q Clock ;LIBRARY ieee ; U

45、SE ieee.std_logic_1164.all ; ENTITY flipflop IS PORT ( D, Resetn, Clock : IN STD_LOGIC ; Q : OUT STD_LOGIC) ; END flipflop ;ARCHITECTURE Behavior OF flipflop IS BEGINPROCESS ( Resetn, Clock ) BEGIN IF Resetn = 0 THEN Q = 0 ; ELSIF ClockEVENT AND Clock = 1 THEN Q = D ; END IF ; END PROCESS ;END Behav

46、ior ; D flip-flop with asynchronous resetD Q Clock Resetn ;LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY flipflop IS PORT ( D, Resetn, Clock : IN STD_LOGIC ; Q : OUT STD_LOGIC) ; END flipflop ;ARCHITECTURE Behavior OF flipflop IS BEGINPROCESS BEGIN WAIT UNTIL ClockEVENT AND Clock = 1 ; IF Rese

47、tn = 0 THEN Q = 0 ; ELSEQ = D ; END IF ; END PROCESS ;END Behavior ; D flip-flop with synchronous resetD Q Clock Resetn ;8-bit register with asynchronous resetLIBRARY ieee ;USE ieee.std_logic_1164.all ;ENTITY reg8 ISPORT ( D: IN STD_LOGIC_VECTOR(7 DOWNTO 0) ;Resetn, Clock: IN STD_LOGIC ;Q : OUT STD_

48、LOGIC_VECTOR(7 DOWNTO 0) ) ;END reg8 ;ARCHITECTURE Behavior OF reg8 ISBEGINPROCESS ( Resetn, Clock )BEGINIF Resetn = 0 THENQ = 00000000 ;ELSIF ClockEVENT AND Clock = 1 THENQ = D ;END IF ;END PROCESS ;END Behavior ;ResetnClockreg888DQ;N-bit register with asynchronous resetLIBRARY ieee ;USE ieee.std_l

49、ogic_1164.all ;ENTITY regn ISGENERIC ( N : INTEGER := 16 ) ;PORT ( D: IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ;Resetn, Clock: IN STD_LOGIC ;Q: OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ;END regn ;ARCHITECTURE Behavior OF regn ISBEGINPROCESS ( Resetn, Clock )BEGINIF Resetn = 0 THENQ 0) ;ELSIF ClockEVENT AND Clo

50、ck = 1 THENQ = D ;END IF ;END PROCESS ;END Behavior ;ResetnClockregnNNDQ;LIBRARY ieee ;USE ieee.std_logic_1164.all ;ENTITY regn ISGENERIC ( N : INTEGER := 8 ) ;PORT (D : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ;Enable, Clock: IN STD_LOGIC ;Q : OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ;END regn ;ARCHITECTURE B

51、ehavior OF regn ISBEGINPROCESS (Clock)BEGINIF (ClockEVENT AND Clock = 1 ) THENIF Enable = 1 THENQ = D ;END IF ;END IF;END PROCESS ;END Behavior ;N-bit register with enableQDEnableClockregnNN;Counters;LIBRARY ieee ;USE ieee.std_logic_1164.all ;USE ieee.std_logic_unsigned.all ;ENTITY upcount ISPORT (C

52、lear, Clock: IN STD_LOGIC ;Q : BUFFER STD_LOGIC_VECTOR(1 DOWNTO 0) ) ;END upcount ;ARCHITECTURE Behavior OF upcount ISBEGINupcount: PROCESS ( Clock )BEGINIF (ClockEVENT AND Clock = 1) THENIF Clear = 1 THENQ = 00 ;ELSEQ = Q + “01” ;END IF ;END IF;END PROCESS;END Behavior ;2-bit up-counter with synchr

53、onous resetQClearClockupcount2;LIBRARY ieee ;USE ieee.std_logic_1164.all ;USE ieee.std_logic_unsigned.all ;ENTITY upcount ISPORT ( Clock, Resetn, Enable : IN STD_LOGIC ;Q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0) ;END upcount ;4-bit up-counter with asynchronous reset (1)QEnableClockupcount4Resetn;ARCHITEC

54、TURE Behavior OF upcount ISSIGNAL Count : STD_LOGIC_VECTOR (3 DOWNTO 0) ;BEGINPROCESS ( Clock, Resetn )BEGINIF Resetn = 0 THENCount = 0000 ;ELSIF (ClockEVENT AND Clock = 1) THENIF Enable = 1 THENCount = Count + 1 ;END IF ;END IF ;END PROCESS ;Q = Count ;END Behavior ;4-bit up-counter with asynchrono

55、us reset (2)QEnableClockupcount4Resetn;Shift Registers;Shift registerDQSinClockDQDQDQQ(3)Q(2)Q(1)Q(0)Enable;Shift Register With Parallel LoadD(3)DQClockEnableSinD(2)DQD(1)DQD(0)DQQ(0)Q(1)Q(2)Q(3)Load;LIBRARY ieee ;USE ieee.std_logic_1164.all ;ENTITY shift4 ISPORT ( D : IN STD_LOGIC_VECTOR(3 DOWNTO 0

56、) ;Enable: IN STD_LOGIC ;Load: IN STD_LOGIC ;Sin : IN STD_LOGIC ;Clock : IN STD_LOGIC ;Q : BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0) ) ;END shift4 ;4-bit shift register with parallel load (1)QEnableClockshift44DLoadSin4;ARCHITECTURE Behavior_1 OF shift4 ISBEGINPROCESS (Clock)BEGINIF ClockEVENT AND Clock =

57、 1 THENIF Load = 1 THENQ = D ;ELSIF Enable = 1 THENQ(0) = Q(1) ;Q(1) = Q(2); Q(2) = Q(3) ; Q(3) = Sin; END IF ;END IF ;END PROCESS ;END Behavior_1 ;4-bit shift register with parallel load (2)QEnableClockshift44DLoadSin4;ARCHITECTURE Behavior_2 OF shift4 ISBEGINPROCESSBEGINWAIT UNTIL ClockEVENT AND C

58、lock = 1 ;IF Load = 1 THENQ = D ;ELSIF Enable = 1 THENQ(3) = Sin; Q(2) = Q(3) ; Q(1) = Q(2); Q(0) = Q(1) ;END IF ;END PROCESS ;END Behavior_2 ;4-bit shift register with parallel load (3)Incorrect!QEnableClockshift44DLoadSin4;LIBRARY ieee ;USE ieee.std_logic_1164.all ;ENTITY shiftn ISGENERIC ( N : IN

59、TEGER := 8 ) ;PORT (D : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ;Enable: IN STD_LOGIC ;Load: IN STD_LOGIC ;Sin : IN STD_LOGIC ;Clock : IN STD_LOGIC ;Q : BUFFER STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ;END shiftn ;N-bit shift register with parallel load (1)QEnableClockshiftnNDLoadSinN;ARCHITECTURE Behavior OF shi

60、ftn ISBEGINPROCESS (Clock)BEGINIF (ClockEVENT AND Clock = 1 ) THENIF Load = 1 THENQ = D ;ELSIF Enable = 1 THENGenbits: FOR i IN 0 TO N-2 LOOPQ(i) = Q(i+1) ;END LOOP ;Q(N-1) = Sin ;END IF;END IF ;END PROCESS ;END Behavior ;N-bit shift register with parallel load (2)QEnableClockshiftnNDLoadSinN;Sequential Statements;Anatomy of a Processlabel: proc