电路设计专题

1、电路设计专题 Design Entry Schematic capture Hardware Description Languages Logic Synthesis Pre layout verification Functional simulation Formal methods Timing Analysis Floorplanning Placement Routing Extraction Post layout verificationLogic DesignPhysical DesignTypical Design Flow形式验证是一个系统性的过程，将使用数学推理来验证设

2、计意图（指标）在实现(RTL)中是否得以贯彻。形式验证可以克服所有3种仿真挑战，由于形式验证能够从算法上穷尽检查所有随时间可能变化的输进值。套用特定的时序模型，针对特定电路分析其是否违反设计者给定的时序限制。 CLBs Composed of: LUTs (lookup tables): perform combinational logic Flip-flops: perform sequential functions Multiplexers: connect LUTs and flip-flops实际FPGA中实现逻辑的方式 Field programmable gate arrays

3、 (FPGAs) Array of configurable logic blocks (CLBs) LUT as key component Perform combinational and sequential logic Configuration is based on SRAMComposed of: CLBs (Configurable logic blocks): perform logic IOBs (Input/output buffers): interface with outside world Programmable interconnection: connec

4、t CLBs and IOBs Some FPGAs include other building blocks such as multipliers and RAMs目录组合逻辑时序逻辑同步时序逻辑储存逻辑（包括rom逻辑）优化方式（流水线、并行、retiming）组合逻辑组合逻辑Single-input: NOT gate, bufferTwo-input: AND, OR, XOR, NAND, NOR, XNORMultiple-inputNOTY = AAY0110AYBUFY = AAY0011AYANDY = ABABY000010100111ABYORY = A + BABY

5、000011101111ABYXNORY = A + BABY00011011ABYXORNANDNORY = A + BY = ABY = A + BABY000011101110ABY001011101110ABY001010100110ABYABYABY1001NOR3Y = A+B+CBCY00011011ABYCA0000000110111111AND4Y = ABCDABYCDBCY00011011A0000000110111111NOR3Y = A+B+CBCY00011011ABYCA000000011011111110000000AND4Y = ABCDABYCDBCY000

6、11011A000000011011111100000001选择器Y0001101101010000000110111111001101SD0YD1D1D0SY01D1D0S2:1 Mux这就是lookup tableABY000010100111Y = AB00Y011011A BAppropriate data inputaddress这个元件叫multiplexerBool代数Truth table lookup tableK mapLUT电路lookuptableABYCDABYCD技巧技巧 Reducing the size of the Mux Reduce the width o

7、f address Flow: Move some lines to input The remaining lines in the address are looped overall Generate the appropriate logic using the moved linesABY000010100111Y = ABAY01001ABYBVerilogmodule example(input wire a, b, c, output wire y); assign y = a & b & c | a & b & c | a & b &a

8、mp; c;Endmodulemodule mux2(input logic 3:0 d0, d1, input logic s, output logic 3:0 y); assign y = s ? d1 : d0; endmoduleVerilogNOT*, /, %mult, div, mod+, -add,subshiftarithmetic shift, , =comparison=, !=equal, not equal&, &AND, NAND, XOR, XNOR|, |OR, NOR?:ternary operatorNumber# BitsBaseDeci

9、mal EquivalentStored3b1013binary5101b11unsizedbinary30000118b118binary3000000118b1010_10118binary171101010113d63decimal61106o426octal341000108hAB8hexadecimal1711010101142Unsizeddecimal42000101010Verilog/ combinational logic using an always statementmodule gates(input 3:0 a, b, output reg 3:0 y1, y2,

10、 y3, y4, y5); always (*) / need begin/end because there is begin / more than one statement in always y1 = a & b; / AND y2 = a | b; / OR y3 = a b; / XOR y4 = (a & b); / NAND y5 = (a | b); / NOR endendmoduleVerilogmodule sevenseg(input 3:0 data, output reg 6:0 segments); always (*) case (data)

11、 / abc_defg 0: segments = 7b111_1110; 1: segments = 7b011_0000; 2: segments = 7b110_1101; 3: segments = 7b111_1001; 4: segments = 7b011_0011; 5: segments = 7b101_1011; 6: segments = 7b101_1111; 7: segments = 7b111_0000; 8: segments = 7b111_1111; 9: segments = 7b111_1011; default: segments = 7b000_00

12、00; / required, or produces / latch endcaseendmodule 时序逻辑时序逻辑1.Bistable CircuitQQQQI1I2I2I1RSQQN1N22.SR (Set/Reset) LatchSRQQSR LatchSymbolSRQQQQDCLKDRSCLKDQQ3.D Latch Internal Circuit时序逻辑元件最终进化版CLKDQQCLKDQQQQDN1CLKL1L24. D Flip-Flop DQQRegistersCLKDQDQDQDQD0D1D2D3Q0Q1Q2Q3D3:044CLKQ3:0Verilog代码：可以看做

13、在触发器处保存了一个值，在每次上升延时修改它。同时，这个值就是触发器输出。Verilogmodule flop(input clk, input 3:0 d, output reg 3:0 q); always (posedge clk) q = d; / pronounced “q gets d”endmoduleVerilogmodule flopr(input clk, input reset, input 3:0 d, output reg 3:0 q); / synchronous reset always (posedge clk) if (reset) q = 4b0; else

14、 q = d;endmoduleq3:0q3:03:0d3:03:0resetclk3:0Q3:03:0D3:0RVerilogmodule flopr(input clk, input reset, input 3:0 d, output reg 3:0 q); / asynchronous reset always (posedge clk, posedge reset) if (reset) q = 4b0; else q = d;endmoduleq3:0Rq3:03:0d3:03:0resetclk3:0Q3:03:0D3:0Verilogmodule flopren(input c

15、lk, input reset, input en, input 3:0 d, output reg 3:0 q); / asynchronous reset and enable always (posedge clk, posedge reset) /not good if (reset) q = 4b0; else if (en) q = d; /what happens if en=0?endmodule Verilogmodule latch(input clk, input 3:0 d, output reg 3:0 q); always (clk, d) if (clk) q =

16、 d;endmoduleWarning: We wont use latches in this course, but you might write code that inadvertently implies a latch. So if your synthesized hardware has latches in it, this indicates an error.la tq 3 :0 q3:0 3: 0d3:03:0clk3: 0D3:03:0Q 3:0C Every cyclic path contains at least one register. why？ 在回路中

17、没有状态机会导致在其中一些输入中输出或中间变量的值迅速发生改变，这导致了系统无法维持某一恒定状态。Synchronous sequential logic使用触发器记录系统状态，并且系统的状态会影响输出；同时系统的状态会维持一定时间，这段时间内输入无法影响输出。实现了：FSM记忆系统流水线触发器充当闸门优化设计组合逻辑实现功能逻辑，时序逻辑构建架构。Synchronous sequential logicFSMCLKMNkknextstatelogicoutputlogicMoore FSMCLKMNkknextstatelogicoutputlogicinputsinputsoutputso

18、utputsstatestatenextstatenextstateMealy FSMMooreS0LA: greenLB: redS1LA: yellowLB: redS3LA: redLB: yellowS2LA: redLB: greenTATATBTBReset交通灯Current StateInputsNext StateS1S0TATBS1S0000X01001X0001XX1010X01110X11011XX00Current StateOutputsS1S0LA1LA0LB1LB0000010010110101000111001S1 = S1 S0 S0 = S1S0TA +

19、S1S0TBLA1 = S1LA0 = S1S0LB1 = S1LB0 = S1S0S1S0S1S0CLKnext state logicoutput logicstate registerResetLA1LB1LB0LA0TATBinputsoutputsS1S0rS0LA: greenLB: redS1LA: yellowLB: redS3LA: redLB: yellowS2LA: redLB: greenTATATBTBReset输出比状态的转变迟一个周期不使用flip-flop会怎样？触发器记录系统当前的状态，使用有限状态机的意义在于使每个状态持续特定的时间，然后在上升沿触发。如果不

20、使用触发器会导致设计不符合要求。Pattern Recognizer Moore FSMmodule patternMoore(input clk, input reset, input a, output y); reg 2:0 state, nextstate; parameter S0 = 3b000; /state encoding parameter S1 = 3b001; parameter S2 = 3b010; parameter S3 = 3b011; parameter S4 = 3b100; / State Register always (posedge clk, po

21、sedge reset) if (reset) state = S0; else state = nextstate; / Next State Logic always (*) case (state) S0: if (a) nextstate = S1; else nextstate = S0; S1: if (a) nextstate = S2; else nextstate = S0; S2: if (a) nextstate = S2; else nextstate = S3; S3: if (a) nextstate = S4; else nextstate = S0; S4: i

22、f (a) nextstate = S2; else nextstate = S0; default: nextstate = S0; endcase / Output Logic assign y = (state = S4);endmodulePattern Recognizer Moore FSMmodule patternMoore(input clk, input reset, input a, output y); reg 2:0 state; parameter S0 = 3b000; /state encoding parameter S1 = 3b001; parameter

23、 S2 = 3b010; parameter S3 = 3b011; parameter S4 = 3b100; / Next State Logic always (posedge clk, posedge reset) if (reset) state = S0;else case (state) S0: if (a) state = S1; else state = S0; S1: if (a) state = S2; else state = S0; S2: if (a) state = S2; else state = S3; S3: if (a) state = S4; else

24、state = S0; S4: if (a) state = S2; else state = S0; default: state = S0; endcase / Output Logic assign y = (state = S4);endmodule同时包含了触发器和状态转换逻辑 （组合逻辑）不同的代码风格，但能得到同样的仿真结果（？）为什么要做电路图分析？Verilog是面向硬件的变成，使用verilog描述电路：1 必须可综合； 2 不同的代码风格得到不同的电路。心中有电路，才能写出好的verilog代码。虽然verilog代码在fpga板上使用的是可编程门阵列电路实现，不一定是按

25、照综合出的电路（测试过程），但是综合出的电路才能生产asic（专用集成电路）工程中第二种实现方式对应的电路图是什么？同样，两个组合逻辑电路，一个D触发器为什么第一种方法会导致输出延期？理论上两种代码都会这是moore状态机的结构决定的resetS0S1S2S30/01/01/00/01/10/01/00/0Mealy FSM蜗牛在1101时微笑Current StateInputNext StateOutputS1S0AS1S0Y000000001010010000011100100110101100110000111011MealyS1S0CLKResetS1S0AYS0S1Pattern

26、Recognizer Mealy FSMmodule patternMealy(input clk, input reset, input a, output y); reg 1:0 state, nextstate; parameter S0 = 2b00; /state encoding parameter S1 = 2b01; parameter S2 = 2b10; parameter S3 = 2b11; / State Register always (posedge clk, posedge reset) if (reset) state = S0; else state = n

27、extstate;/ Next State Logic always (*) case (state) S0: if (a) nextstate = S1; else nextstate = S0; S1: if (a) nextstate = S2; else nextstate = S0; S2: if (a) nextstate = S2; else nextstate = S3; S3: if (a) nextstate = S1; else nextstate = S0; default: nextstate = S0; endcase / Output Logic assign y = (a & state = S3);endmoduleSynchronous logicPipelining(优化）ROM logicAddressData11100100depth0 1 01 0 01 1 00 1 1width X = AB Y = A + B Z = A BMem