浅谈多核处理器和系统软件研发ppt课件

1、 浅谈多核处置器与系统软件研发-实例研讨: 思科QuantumFlow处置器与系统软件构造 陈怀临陈怀临tektalk系统软件 工业动态 系统了解实例研讨：思科QuantumFlow终了语提纲提纲目的：非盈利性智库机构领域：科技跟踪专题分析人物报道学术打假 tektalk 最近任务总结： 专题分析 tektalk 最近任务总结： 科技书籍： The Linux Kernel)下 The Linux Kernel)中The Linux Kernel)上下上 tektalk 最近任务总结： 人物评述： 上下 tektalk 操作系统桌面操作系统效力器操作系统嵌入式操作系统 编译器与工具链gcc,

2、binutil, gdb)编程环境，中间件PVM，MPI，OpenMPMapreduce，HadoopCORBA，DCOM系统软件系统软件 嵌入式操作系统-传统分时系统：Linux，FreeBSD-微内核： QNX/Neutrino， L4，Mach-大型通讯操作系统：华为/VRP思科/IOS，IOS-XR，IOS-XE系统软件系统软件通讯业工业研发动态通讯业工业研发动态 多核系统的继续运用 多核系统的多样化微观分布式并行计算系统工业动态工业动态 系统System与操作系统Operating System，中心Kernel)的关系计算单元的多样化ASIC，FPGA，CPU，NP互连网络的多样化

3、Bus，Switch Fabric，Interconnect数据报文Packet驱动，调度。中断，异常处置的简化性能的考量，牺牲层次性和透明性系统了解系统了解实例研讨：思科实例研讨：思科QuantumFlow 实例研讨：思科实例研讨：思科QuantumFlow 工程启动时间：2019年Q3或Q4【笔者注：SPP是2019年流片的。CRS-1是2019年推出的。】研发耗资：1亿美金芯片主要定位：边缘Edge路由器，企业路由器。芯片处理问题：Stateful Service与转发Forwarding)合一。 首发系统：ASR1000主频：1.2GHZ【笔者注：ESP-5G:900MHz. ESP-

4、10G:900MHz.ESP-20G:1.2GHz】晶体管数目：8亿PFE内存：DDR2。 数据报文内存Packet Buffer：ESP-5G:64M.ESP-10G:128M.ESP-20G:256m*CAM:外挂TCAM 【笔者注：ESP-5G:10M. ESP-10G:10M.ESP-20G:40M】功耗：80瓦多核：40，4 Way-Thread。来自Tensica的Xtensa。片内互联Interconnect：Crossbar Switch片外互联：ESI 【笔者注：在未来的新QFPzhong，将是Interlaken】数据报文接口：4个10GBPS SPI4.2 。工艺：90n

5、m流片：德州仪器实例研讨：思科实例研讨：思科QuantumFlow 实例研讨：思科实例研讨：思科QuantumFlow 实例研讨：思科实例研讨：思科QuantumFlow 实例研讨：思科实例研讨：思科QuantumFlow 实例研讨：思科实例研讨：思科QuantumFlow 实例研讨：思科实例研讨：思科QuantumFlow 实例研讨：思科实例研讨：思科QuantumFlow 实例研讨：思科实例研讨：思科QuantumFlow SPA Slots# of ESP Slots# of RP Slots# of SIP SlotsIOS RedundancyBuilt in GigEHeightB

6、andwidthPerformanceAir FlowPower Supply (Watts) 3-slot1Integrated (RP1)Integrated (SIP10)S/W43.5 (2RU)5-10 Gbps4-8 MppsFront to Back4708-slot112S/Wn/a7 (4RU)10-40+ Gbps8-16+ MppsFront to Back76512-slot223H/Wn/a10.5 (6RU)10-40+ Gbps8-16+ MppsFront to Back1275Aggregated Services & ScaleCisco ASR 1

7、000 SeriesASR1000 ILT NamingCPP = Cisco Packet Processor now known as the QuantumFlow Processor (QFP)CC = CarrierCard now known as the SPA Interface Processor (SIP)FP = Forwarding Processor now known as the Embedded Services Processor (ESP)FRU = Field Replaceable UnitRP = Route Processor IOSd = IOS

8、daemon, IOS process running on RPChassis Options: ASR1006RP1 (in slots “r0 & “r1)ESP10SIP10SPAsRack Mounts and Cable Mgt not shownSystem Architecture - DataplaneRoute Processor (standby)RPInterconn.Embedded ServicesProcessor(active)FECPInterconn.SPI4.2CPP subsys-temCrypto assistEmbedded Services

9、Processor(standby)FECPInterconn.SPI4.2CPP subsys-temCrypto assistSPASPAIOCPSPA Agg.Interconn.SPASPAIOCPSPA Agg.Interconn.SPASPAIOCPSPA Agg.Interconn.MidplaneRoute Processor (active)RPInterconn.SPA-SPI, 11.2GbpsHypertransport, 10Gbps ESI, 11.5GbpsAll data forwarding is through FPException: Punt path

10、for Legacy protocols handled by the RPInterconnect ASIC in each of the functional elements provides the backplane connection through ESI linksESI (Enhanced Services Interface) links are used for Data forwardingSPA-SPI links connect to the backplane through the SPA-Agg ASICDDR2-500 SDRAM MiniDIMM2.5

11、Hard disk or Solid-state driveUSB InterfaceUSB 2.0 controllerStratum-3 Network clock circuitConsole and AuxDDR2-500 SDRAM MiniDIMMMgmt ENETFP1FP0GE Switch4 CCsFP0 FP1Output clocksOther RPI2C Muxbootflash :1GB(Bulk Storage, NVRAM)Temp SensorPower CtlrEEPROMRTCUSBPowerPC CPU(SC854x SOC PowerQUICC III)

12、Interconn.SIPsESPsRPSIPsESPsRPESPsMisc.CtrlSATA controllernvarm: 32MB x 2 (part of bootflash: device)BITSSIPsSIPsIn ref clocksRPRP1 Block DiagramGE, 1GbpsI2C Inter-ICSPA ControlSPA BusESI, 11.2GbpsSPA-SPI, 11.2GbpsHypertransport, 10Gbps OtherESP10 Block DiagramGE, 1GbpsI2CSPA ControlSPA BusESI, 11.2

13、GbpsSPA-SPI, 11.2GbpsHypertransport, 10Gbps OtherFECP(SC854x SOC PowerQUICC III)Temp SensorPower CtlrEEPROMBoot Flash (OBFL, )JTAG CtrlDDR2-500 SDRAM MiniDIMMInterconn.Interconn.Reset / Pwr CtrlPkt Buffer DRAM (128MB)Part Len/ BW SRAMResource DRAM (512MB)SPI MuxCryptoRPsRPsRPsESPSIPsTCAM4 (10Mbit)E-

14、RP*PCI*E-CSRSA table DRAMProcessor poolPPE0PPE0PPE0PPE1PPE0PPE0PPE0PPE6PPE0PPE0PPE0PPE2PPE0PPE0PPE0PPE5PPE0PPE0PPE0PPE3PPE0PPE0PPE0PPE40PPE0PPE0PPE0PPE4Buffer, queue, schedule (BQS)QFPBuffer, queue, schedule (BQS)Buffer, queue, schedule (BQS)Dispatcher/Pkt BufferASR System BWSIP10 Block DiagramIOCP(

15、SC854x SOC)Temp SensorPower CtlrEEPROMBoot Flash (OBFL, )JTAG CtrlDDR2-500 SDRAM MiniDIMMReset / Pwr CtrlRPsRPsInterconn.Ingress classifierIngress SchedulerEgress Buffer StatusGE, 1GbpsI2CSPA ControlSPA BusESI, 11.2GbpsSPA-SPI, 11.2GbpsHypertransport, 10Gbps Other4 SPAs4 SPAsIngress Buffers (per por

16、t)Egress Buffers (per port)ESPs4 SPAsC2WEV-FCEV-RPNetwork clock distributionIn ref clocksNetwork clocks4 SPAs 4 SPAsRPsRPsSPA Agg.SPA Aggregation ASIC IOS-XE IOS XE Virtual MachineIOS UpgradeASR 1002 & 1004 (No HW Redundancy)Zero Packet LossIOS UpgradeZero Packet LossIOS UpgradeISSUISSUIOS XE Vi

17、rtual MachineIOS XE Virtual MachineIOS ActiveIOS StandbyIOS ActiveIOS StandbyIOS StandbyIOS ActiveStep 1Step 2Software VirtualizationIndustry first, delivering hitless upgrades without costly hardware redundancyCapable of broad scope of services: SP and enterprise, hosted or managedDecreases OpEx, i

18、ncreases return on training investmentFeatureBenefitCombines rich edge feature set of IOSProvides IOS command line, common look and feel for transparency to operatorSoftware Architecture IOS XEEmbedded Services ProcessorRoute ProcessorSPA Interface ProcessorControl MessagingKernelKernelKernelQFPClient/Driver IOS XE = IOS + IOS XE Middleware + Platform Software Operational Consistency - same look and feel as IOS Router IOS runs as its own Linux process for control p