数字电路英文版第十单元

1、KEY TERMS Bidirectional Having two directions. In a bidirectional shift register, the stored data can be shifted right or left. Johnson counter A type of register in which a specified prestored pattern of 1s and 0s is shifted through the stages, creating a unique sequence of bit patterns. Load To en

2、ter data into a shift register. Ring counter A register in which a certain pattern of 1s and 0s is continuously recirculated. Stage One storage element in a register. Shift To move binary data from state to stage within a shift register or other storage device or to move binary data into or out of t

3、he device. Universal shift register A register that has both serial and parallel input and output capability. Shift registers consist of an arrangement of flip-flops and are important in applications involving the storage and transfer of data in a digital system.2.D0QC0CLKD1QC1CLK1 is stored0 is sto

4、redThe flip-flop as a storage element.3.DatainDataoutDatainDataout(a) Serial in/shift right/serial out(b) Serial in/shift left/serial out4.Data inData out(c) Parallel in/serial outData inData out(d) Serial in/ parallel out5.Data inData out(e) Parallel in/ parallel out(f) Rotate right(g) Rotate left6

5、. The serial in/serial out shift register accepts data serially that is , one bit at a time on a single line. It produces the stored information on its output also in serial form.7.DCDCDCDCQ0Q1Q2Q3Q3Serial data outputSerial data outputSerial data inputCLKSerial in/ serial out shift register8.FF0FF1F

6、F2FF3DCDCDCDCFF0FF1FF2FF3CLKData inputRegisterinitiallyCLEAR0000Q3DCDCDCDCFF0FF1FF2FF31st dataAfter CLK10000Q3bit = 0CLK 19.DCDCDCDCFF0FF1FF2FF32st dataAfter CLK20100Q3bit = 1CLK 2DCDCDCDCFF0FF1FF2FF33st dataAfter CLK31000Q3bit = 0CLK 310.DCDCDCDCFF0FF1FF2FF34st dataAfter CLK40110Q3bit = 1CLK 4Four

7、bit ( 1010 ) being entered serially into the register. 11.DCDCDCDCFF0FF1FF2FF3After CLK401100CLKregistercontains1010DCDCDCDCFF0FF1FF2FF31st dataAfter CLK51001Q3bitCLK 5Q302nd date bit 12.DCDCDCDCFF0FF1FF2FF3After CLK70001CLK 70DCDCDCDCFF0FF1FF2FF3After CLK60010CLK 60Q3Q34th date bit 3rd date bit 13.

8、DCDCDCDCFF0FF1FF2FF3After CLK80000CLK 80Q3registeris CLEARFour bit ( 1010 ) being serially shiftedout of the register and replaced by all zeros. 14.EXAMPLE 10-1 Q4Q3Q2Q1Q0 =11010DCDCDCDCFF0FF1FF2FF3DCFF4Q0Q1Q2Q3Q4Data inputData outputCLK 15.CLKData inputQ0Q1Q2Q3Q41111110000Data bitstoredafterpulsecl

9、ockfive16. Data bits are entered serially into this type of register in the same manner as discussed in Section 10-2. The difference is the way in which the data bits are taken out of the register; in the parallel output register, the output of each stage is available. 17.Once the data are stored, e

10、ach bit appears on its respective output line, and all bits are available simultaneously, rather than on a bit-by-bit basis as with the serial output.18.DCDCDCDCFF0FF1FF2FF3DataCLKQ3inputQ0Q1Q2SRG 4DCQ3Q0Q1Q2Data inputCLK19.EXAMPLE 10-2 The register contains 0110.SRG 4DCQ3Q0Q1Q2CLKQ0Q1Q2Q31111000020

11、. For a register with parallel data inputs, the bits are entered simultaneously into their respective stages on parallel lines rather than on a bit-by-bit basis on one line as with serial data inputs. The serial output is the same as described in Section 10-2, once the data are completely stored in

12、the register. 21.DCDCDCDCdataCLKQ3outputQ0Q1Q2SHIFT/LOADD3D0D1D2SerialG3G1G2G6G5G422.SRG 4CD3D0D1D2SHIFT/LOADCLKSerial data out(b) Logic symbol23.Data in Parallel entry of data was described in Section10-4, and parallel output of data has also been discussed previously. The parallel in/parallel out

13、register employs both methods. Immediately following the simultaneous entry of all data bits, the bits appear on the parallel outputs.24.DCDCDCDCQ0Q1Q2Q3D3CLKD0D1D2Parallel data outputParallel data input25. A bidirectional shift register is one in which the data can be shift either left or right. It

14、 can be implemented by using gating logic that enables the transfer of a data bit from one stage to the next stage to the right or to the left, depending on the level of a control line.26.DCDCDCDCCLKQ3Serial data inQ0Q1Q2R/LG8G6G7G4G3G2G1G527.CLKQ0Q1Q2123456789Q31111111111111111000000000000000000000

15、00( right )( right )( left )( left )0EXAMPLE 10-4 Q3Q2Q1Q0=1011R/L28. The Johnson Counter: In a Johnson counter the complement of the output of the last flip-flop is connected back to the D input of the first flip-flop.29.Clock Pulse Q0 Q1 Q2 Q3 0 0 0 0 0 1 1 0 0 0 2 1 1 0 0 3 1 1 1 0 4 1 1 1 1 5 0

16、1 1 1 6 0 0 1 1 7 0 0 0 1Four-bit Johnson sequence. 2n states30.DCDCDCDCQ0Q1Q2FF1Q3FF2FF3FF0CLK(a) Four-bit Johnson counter31.CLKQ0Q1Q212345678Q3Timing sequence for a 4-bit Johnson counter32. The Ring Counter : The ring counter utilizes one flip-flop for each state in its sequence.33.DCDCDCDCQ0Q1Q2F

17、F1CLRFF3PRECLKDCDCQ3Q4Q5A 6-bit ring counter 34.Clock Pulse Q0 Q1 Q2 Q3 Q4 Q5 0 1 0 0 0 0 0 1 0 1 0 0 0 0 2 0 0 1 0 0 0 3 0 0 0 1 0 0 4 0 0 0 0 1 0 5 0 0 0 0 0 1Six-bit ring counter sequence.35.CLKQ0Q1Q212345678Q3Q5Q436.Time DelaySRG 8ACCLKData in123456789Data outData in1 us8 usQ7Q7CLK 1MHzEXAMPLE 1

18、0-6 Determine the amount of time delay between the serial input and each output in Figure 10-29. Show a timing diagram to illustrate.SRG 8*ACCLK 500 kHzQ7Q0Q1Q2Q3Q4Q6Q5CLRData inB* Data shift from Q0 toward Q7CLK123456789Data inQ6Q0Q1Q2Q3Q4Q5Q72 us16 usSRG 4Data BitsCQ7D0Q3+V+SH/LDSRG 87419574195D4D

19、1D2D3D6D5D7Start bitStop bitCLKCSRG 4Data BitsCQ7D0Q3+V+SH/LDSRG 87419574195D4D1D2D3D6D5D7Start bitStop bitCLKC43. See Figure as follow for one possible implementation.Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 D0 D1 D2 D3 D4 D5 D6 D7 74LS16474LS199SRSLS1S0CLRBACLR+5VQ0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q0

20、Q1 Q2 Q3 Q4 Q5 Q6 Q7 D0 D1 D2 D3 D4 D5 D6 D7 74LS16474LS199SRSLS1S0CLRBACLR+5VLOADENPENTCLRD3 D2 D1 D0Q3 Q2 Q1 Q074LS163JKCLRPREQRCO+5V+5V+5VParallel Data Out ( HIGH) Parallel Data Out (LOW) Data In CLK Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 D0 D1 D2 D3 D4 D5 D6 D7 74LS16474LS199SRSLS1S0CLR

21、BACLR+5VQ0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 D0 D1 D2 D3 D4 D5 D6 D7 74LS16474LS199SRSLS1S0CLRBACLR+5VLOADENPENTCLRD3 D2 D1 D0Q3 Q2 Q1 Q074LS163JKCLRPREQRCO+5V+5V+5VParallel Data Out ( HIGH) Parallel Data Out (LOW) Data In CLK 42. Portions of the circuit that require modification for 16-b

22、it conversion.7476Digital System Design with VHDL Combinational building blocks 1.Decoder 1.1 2 to 4 decoder library ieee; use ieee.std_logic_1164.all; entity decoder is port ( a: in std_ulogic_vector(1 downto 0); z: out std_ulogic_vector(3 downto 0); end entity decoder; architecture when_else of de

23、coder is begin z = “0001” when a = “00” else “0010” when a = “01” else “0100” when a = “10” else “1000” when a = “11” else “XXXX” ; end architecture when_else;Seven-segment display library ieee; use ieee.std_logic_1164.all; entity seven_seg is port ( a: in integer range 0 to 15; z: out std_ulogic_ve

24、ctor(6 downto 0); end entity seven_seg; architecture with_select of seven_seg is begin z = “1111110” when 0, “0110000” when 1, “1101101” when 2, “1111001” when 3, “0110011” when 4, “1011011” when 5, “1011111” when 6, “1010010” when 7, “1111111” when 8, “1111011” when 9, “1001111” when 10 to 15; end

25、architecture with_select;Multiplexers 4 to 1 multiplexer library ieee; use ieee.std_logic_1164.all; entity mux is port ( a, b, c, d: in std_ulogic; s: in std_ulogic_vector(1 downto 0); y: out std_ulogic); end entity mux; architecture mux1 of mux is begin with s select y = a when “00” ; b when “01” ; c when “10” ; d when “11” ; “X” when others; end architecture mux1; architecture mux2 of mux is begin y = a when s = “00” else; b when s = “01” else; c when s = “10” else; d when s = “11” else; “X”; end architecture mux2;VHDL models