第十一低功耗学习教案

1、会计学1第十一低功耗第十一低功耗第一页，共54页。第1页/共54页第二页，共54页。 for 110V/20A plug第2页/共54页第三页，共54页。第3页/共54页第四页，共54页。第4页/共54页第五页，共54页。第5页/共54页第六页，共54页。C = node capacitancesNsw = switching activities (number of gate transitions per clock cycle)F = frequency of operationVDD = supply voltageQsc = charge carried byshort circu

2、it currentper transitionIleak = leakage current第6页/共54页第七页，共54页。第7页/共54页第八页，共54页。Long Channel(L1um)Very small leakageShort channel(L180nm,tox30A)Subthreshold leakageVery short channel(L90nm, tox20A)subthreshold+gate leakageNano-scaled(L90nm,Tox20A) Subthreshold+gate+junction leakageSub-threshold lea

3、kage current Has become quite important with technology scalingGate leakage currentIs becoming important with shrinking device dimensions PN junction leakage currentNegligible 第8页/共54页第九页，共54页。第9页/共54页第十页，共54页。第10页/共54页第十一页，共54页。第11页/共54页第十二页，共54页。第12页/共54页第十三页，共54页。第13页/共54页第十四页，共54页。nPower aware O

4、peration System, compiler, SW design etc.第14页/共54页第十五页，共54页。第15页/共54页第十六页，共54页。第16页/共54页第十七页，共54页。High Vt cell on Critical PathHints:1.You need to have dual Vt library2.You need to pay for the extra layer mask for multi-vt 第17页/共54页第十八页，共54页。nLibrary design for freely mix and match on SoC design第18页

5、/共54页第十九页，共54页。第19页/共54页第二十页，共54页。第20页/共54页第二十一页，共54页。Triple well structure CMOS InverterHint:Do you have the triple well structuredstandard cell lib?第21页/共54页第二十二页，共54页。第22页/共54页第二十三页，共54页。第23页/共54页第二十四页，共54页。Toggling consume power.Enable the module clock only when neededgated_clkEnableLogicGlobalC

6、lkComb.LogicDataReg第24页/共54页第二十五页，共54页。clk_enclkgclk第25页/共54页第二十六页，共54页。clk_enclkgclkAdd a transparent-low latchMake sure the clk gating cells are placed tightly for correct function clk cell hardeningCommonly in SoC: make a “hardmacro” - clk gating cellRTL code for clk cell:always (clk or clk_en) i

7、f(!clk) ctrl_latch = clk_en;assign gclk = ctrl_latch & clkClock gating cells and a glitch free clock gatingDQGLatchclk_enclkgclk第26页/共54页第二十七页，共54页。第27页/共54页第二十八页，共54页。第28页/共54页第二十九页，共54页。mappingnlow power cell第29页/共54页第三十页，共54页。第30页/共54页第三十一页，共54页。第31页/共54页第三十二页，共54页。AABBCdelay = 1delay = 2ABCAbuff

8、erdelay=1AABBCdelay = 1delay = 2ABCA第32页/共54页第三十三页，共54页。第33页/共54页第三十四页，共54页。nHave seen in filler cell at 0.13um processnBut the leakage on decoupling cap itself at 90nm and below must take into account第34页/共54页第三十五页，共54页。Global Clock RoutingReduce Clock LoadnReduce oversized clock drivernReduce # of

9、 clock driversnReduce # of clock tracksMinimum Width Clock Tracks are resistance limitednLower R for drivabilitynLower C for powernIncrease width & space to minimize C & R where possible.nAdd enough vias to reduce resistance第35页/共54页第三十六页，共54页。第36页/共54页第三十七页，共54页。Bank 1Bank 2.Bank 0activewaitPowerdo

10、wn.第37页/共54页第三十八页，共54页。第38页/共54页第三十九页，共54页。Source: ARM. IEM: Intellectual Energy Management第39页/共54页第四十页，共54页。WRRService Queue(SQ)Service Provider(SP)Linux Online!h ht tt tp p: :w ww ww w. .l li in nu ux x. .o or rg gCommandsPower Management(PM)A AR RMMService Requestor(SR)第40页/共54页第四十一页，共54页。PowerS

11、avingWork SleepDeepSleepOffProgram 1Program 2Program 3Application Program InterfaceKernelDevice DriversI/OCPUHard DiskOSControl Systemresources. It can alsocontrol the power statesof the resourcesACPI(Advanced Configuration andPower Interface)provides and interfacebetween the OS andsystem resourcesS

12、ystem ResourcesACPI-Power Saving ModesPower ConsumptionNeed to developpower managementpolicies第41页/共54页第四十二页，共54页。needs while saving energynReduce the processors voltage and frequency to obtain quadric energy saving第42页/共54页第四十三页，共54页。DVS & DFS designed by ARM & National Semiconductor ARM & National

13、 Semiconductor第43页/共54页第四十四页，共54页。第44页/共54页第四十五页，共54页。Source: conference papers, magazine articles低功耗技术漏电功耗的减小静态功耗的减小时序影响面积影响设计方法影响验证复杂度影响仿真影响面积优化10%10%0%-10%无低无多阈值工艺80%0%0%2%低低无时钟门控020%0%2%低低无多电压50%40-50%0%10%中中低电源门控90-98%0%4-8%5-15%中高低动态电压及动态频率缩放 50-70%40-70%0%10%高高高体偏置90%-10%10%高高高第45页/共54页第四十六页，

14、共54页。第46页/共54页第四十七页，共54页。第47页/共54页第四十八页，共54页。第48页/共54页第四十九页，共54页。Accuracy vs. Efficiency Tradeoff第49页/共54页第五十页，共54页。第50页/共54页第五十一页，共54页。Analysis levelAnalysis ToolNotesRTLPowerTheater Power Complier(synthesis)Quick RTL power analysis;Power-aware synthesis and gate level optimizationGatePrimePower(simulation)Accurate dynamic power analysis, pattern-dependent modeling of captive switching, short-circuit & static powerTransistorPowerMill (simulation)Transistor-level, pattern dependant, high speed, high capa