cadence设计全ca版图其他the wireless solution

1、1CADENCE DESIGN SYSTEMS, INC.The Cadence Wireless Solution2Seminar Agenda10:15 - 10:35IntroductionCadence wireless initiative What is Bluetooth?10:35 - 11:25 Capture, analysis, and optimization of digital basebandwireless designs using SPW 11:25 - 12:15Capture, analysis and optimization of wirelessp

2、latforms using VCC12:15 - 1:15Lunch 1:15 - 1:45Hardware-based system verification solutions forclosed-loop power control, BER analysis and SWdevelopment 1:45 - 2:05SPW link with NC-SIM for digital baseband verification and cross debugging with C/C+ test benches and RTL 2:05 - 2:35Synthesizing Digita

3、l Baseband designs using theBuildGates Wireless Datapath Synthesis Option 2:35 - 3:15 Demo, Q&A 3CadenceLeading Edge Wireless Design Solution Enhanced productivity Improved simulation accuracy Improved simulation speed Better implementation results gate efficiency/clock rate Unique mixed-signal desi

4、gn and verification capabilities Corporate Focus on improving design flows for wireless4SatelliteMacro-CellMicro-CellZone 2: UrbanZone 1: In-BuildingPico-CellZone 4: GlobalZone 3: SuburbanBasic TerminalPDA TerminalAudio/Visual TerminalChallenges of Leading-edge Wireless Development Exploding System

5、Design & Verification Verification Complexity Will it be the right product? Will it work in the real operating environment? Is my product differentiated enough? How can I ensure a smooth flow from specification to implementation?5AlgorithmDesign Function-Architecture ExplorationFunctional Verificati

6、onSynthesisPlace &RoutePhysicalVerificationICPackagingFabricationWireless Platform Design- Including Digital, SW and Analog/RFFront-EndBack-EndSystem-LevelASIC Customer Ericsson, Compaq, HP ASIC Vendor IBM, LSI, NEC,. Integrated Device Manufacturer Intel, TI, Fujitsu, ST, Philips. COT Customer Cisco

7、, Broadcom, Empowertel FoundryFoundrySystem CustomerPlatform Provider Philips, ST Micro, IBMFabless Platform Provider Trisend, etcSystem CustomerCompaq,Ericsson,HPImplementation PathTSMC,Chartered6TechnologyAlgorithmDesignSynthesisFunctional VerificationFunctionArchitectureExplorationThe Customer De

8、sign ChallengeDelivery of integration platformsGeneralized system-level tradeoff analysisHigher Level of AbstractionThe first and only solution in this spaceSystem level HW/SW tradeoffsLinks to the Cadence IC flowONLY solution that spans SW & HWStrongest Mixed-language Support(Verilog, VHDL AND Anal

9、og)Integrated Testbench Analysis3G wireless - data1-6M gates2.5-5 GHz (SoC)Quality of Results (QoR)Low PowerCapacitySignal processing algorithm designSpeed and increased capacityAdvanced Wireless librariesLinks to Cadence IC flow including RFAutomatic improved results for wireless DatapathCustomer C

10、hallengeCadence Solution FocusAnalogMixed-SignalIntegration of RF +Baseband DSP 5GHzCan handle larger circuitsFastest simulation7 Small cells of 10 m radius 10 picoNets/cell Located in ISM band (2.45 GHz) FFH/DS spread-spectrum radios (1400 hops/sec) 432 kbs full-duplex, 721/56 kbs asymmetric half-d

11、uplex 0 dBm (1 mW) output power 80 mW and 300 mW in send and listening modes, respectivelyBluetooth: The Demonstration Theme Initiative by Intel, Ericsson, Nokia, IBM, and Toshiba Goal: Provide wireless I/F between PC and periphery using picocell technology83G WirelessHello HelloHelloBluetooth Wirel

12、ess Applications PC wire connector replacement Multimedia device integration New consumer applications9DSP processingSystem I/ORISC/DSP/ASICAutofocusDemosaic, GammaRGB-YUV, JPEG2000 I/O & Network StackMEMORYA/DMicA/DMEMORYRISC/DSP/ASICAudio CompressionVideo processingPhotoMEMORYFlashBATTERYCHARGER/P

13、WR MGMTAmpSensorBlue Tooth3G WCDMAKeyboard DisplayView FinderA Bluetooth Enabled Cell-phoneBluetooth Design & Verification ChallengesDoes my algorithm work?Can the architecture be reconfigured to support new features?What is my processor, bus, memory, and RTOS overhead?Will my RF system work?Which a

14、ntenna design will deliver the performance I need?11Digital baseband designCreate RF portion of design Wireless Design FlowPlace and RouteWhat should be in HW and what in SW?Does my design work the way I want it to?Does my entire system work correctly?Synthesize baseband design into gatesRF DesignSi

15、gnal processing designHW/SW CoDesignSignal processing-RTL co-simulationData path logic synthesisSystem EmulationSpectre RFSPWVCCSPW and NC-SIMQuickturn Mercury/RPSBuild Gates with data path option12Seminar Agenda10:15 - 10:35IntroductionCadence wireless initiative What is Bluetooth?10:35 - 11:25 Cap

16、ture, analysis, and optimization of digital basebandwireless designs using SPW 11:25 - 12:15Capture, analysis and optimization of wirelessplatforms using VCC12:15 - 1:15Lunch 1:15 - 1:45Hardware-based system verification solutions forclosed-loop power control, BER analysis and SWdevelopment 1:45 - 2

17、:05SPW link with NC-SIM for digital baseband verification and cross debugging with C/C+ test benches and RTL 2:05 - 2:35Synthesizing Digital Baseband designs using theBuildGates Wireless Datapath Synthesis Option 2:35 - 3:15 Demo, Q&A 13Digital Baseband Design With SPWTestBenchHDLHDLTestBenchHDLC+,

18、OMIC/C+, MATLABVerilog-AImpl. ModelsHDL, C HDLSWSDL, OMI14Design Challenges Market factors: Exploding market growth with complex communication standards Cost and power sensitive consumer markets Faster time to market pressures with increased IP reuse Wireless design and verification challenges: Incr

19、eased complexity Wireless designers scarce Integrated Voice, Video & Data15Cadence System-level DesignSatelliteMacro-CellMicro-CellZone 2: UrbanZone 1: In-BuildingPico-CellZone 4: GlobalZone 3: SuburbanFirmwareCORESOC IPBased DesignSoftwareSOC P/CAnalogEmbedded SoftwareMemoryEmbedded Systems DesignS

20、ystemEnvironmentPCB Design16Spectre RF (J&K link)System LevelDesign FlowAmbit Synthesis / Place & Route etc.SPW-NC-SIM C+/RTL Cross DebugQuickturn - Verification CockpitSPW HDS Block ImplementationHardwareDevelopmentSPW Fixed Point Algorithm AnalysisSPW Floating Point Algorithm AnalysisSoftwareDevel

21、opmentSPW DSP Behavioral SpecificationCore ISS models Block LevelSpecificationC+RTLFull System SpecificationVCC Platform IntegrationC/C+, MatLab, HDLRF J-K models3G Wireless LibrariesMultimedia Libraries17SPWApplication Specific Libraries& AnalysisInteractive TestbenchesPowerful System& ASIC DesignT

22、oolsIntegrated WithNC Simulators18Floating Point AlgorithmS SZ ZS SK KK KDoes the algorithm work?Graphical ExecutableAlgorithmic ModelsCadence Signal Processing Worksystem Block Authoring of DSP IP19UntimedFixed Point AlgorithmZK KS SS SK KDoes the algorithm work at certain bit data width?Graphical

23、ExecutableFixed PointAlgorithmic ModelsPolymorphismFloating Point AlgorithmS SZ ZS SK KK KDoes the algorithm work?Graphical ExecutableAlgorithmic ModelsCadence Signal Processing Worksystem Block Authoring of DSP IP20Cadence Signal Processing WorksystemBlock Authoring of the Bluetooth ReceiverClocked

24、HW / SW ImplementationsTest Bench EnvironmentHDL ExportConsistent Test BenchRTL H/W Architecture DesignDoes the algorithm work after pipelining?Graphical ExecutableFixed PointAlgorithmic ModelsMPEGVideo DecoderMPEGAudio DecoderGraphicsEngineuCSoftwareTasksSOCUntimedFixed Point AlgorithmZK KS SS SK K

25、Does the algorithm work at certain bit data width?Graphical ExecutableFixed PointAlgorithmic ModelsPolymorphismFloating Point AlgorithmS SZ ZS SK KK KDoes the algorithm work?Graphical ExecutableAlgorithmic Models21Complete IP Authoring to Implementation DSP System Design Comprehensive application-sp

26、ecific libraries shorten time to market Fastest simulation in the industry Powerful features to optimize system performance parametric studies, polymorphism, application-specific analysis tools FSM, filter design, data management IP Creation Create parameterized & reusable IP Generate efficient RTL

27、for ASIC or FPGA Generate C code for software Verification Create application-specific testbenches Verify the ASIC in the context of the system22SPW Improves Productivity Extended Flow SPW - NC Sim Link for System C+/RTL ASIC co-development Very Fast RF / Baseband system verification with Spectre RF

28、 Model export to VCC for IP reuse & platform integration Leading-edge Communication and Multimedia Libraries Comprehensive Application Libraries Shorten Time to Market 3G WCDMA & digital video Simulation Speed and Capacity for multimillion gate designs Special Productivity Features Polymorphic techn

29、ology for data type independent blocks and ports Block wizard simplifies creation and import of IP23SPW 4.6 Highlights SystemC version 1.0 co-simulation Libraries GSM with GPRS library updated to include latest EDGE DVB-T 3GPP updates WLAN Library with: Bluetooth, IEEE802.11 New OMI Export to VCC -

30、export designs which include RTL blocks, fixed-point signals and polymorphic signals Polymorphic Modeling improvements New documentation on Polymorphic modeling and custom C blocks - 120 pages, 3 chapters 2-3x Faster simulation speed New HTML manuals24Complete Solution for Advanced Digital Communica

31、tions Building Blocks Sequence generation Acquisition Tracking Channel estimation Interference cancellation Reference Libraries Wideband CDMA (3GPP) CDMA2000/IS2000 (NIST) Adaptive antenna models GSM - GPRS - EDGE IEEE802.11 WLAN Bluetooth WLAN IS-54/136, IS-95 RF & Radar Libraries ADSL DVB - T (Dig

32、ital TV Comms) Matrix library Galios field 25Complete Solution for Multimedia Apps Building Blocks Image Acquisition Image Compression Video Compression Video Quality Analysis Video Viewer Reference Systems Full MPEG 1,2 Codecs Hierarchical Polymorphic Encoder Polymorphic Decoder Complete Digital Ca

33、mera Prototype Optical Lens, sensor, autofocus, CFA and compression system. Wireless Video System JPEG2000 compressed bitstream over WCDMA forward link. NTSC Codec Design NTSC signal creation with color separation26SPW with HDS Provides Seamless Flow from System to ASICS and FPGAS Parameterized desi

34、gns maximize design reuse Mixed Block diagram, FSM and RTL Multiple clocks, asynchronous reset Automatic generation of VHDL,Verilog RTL & testbench Flow to ASIC & FPGA Synthesis Tools Powerful integration with NC simulators Seamless integration of external HDL IP Cross debug Testbench and RTL27ttwos

35、 complementuunsignedData type values can change through the designREGMEMMEM14 From 1 to 256 bits5 Shifteable Plus or Minus 1024S 1 0 1 0 1 1 0 0 1 0 0 1 1clip,roundHDS Fixed Point Data Type Word length selection Dynamic range Accuracy Arithmetic modes Signed/Unsigned Wrap and Clip Truncate plus 6 Ro

36、unding Modes Error handling Match System spec: Desired fidelity At minimum size28Problems Solved Reduces time to market Accelerates creation of market differentiating IP and its reuse Increased first time success Complex communication systems Best signal to noise, BER, stability and predictability I

37、ntegration at system specification level over world-wide teams/skills Integration of design flows to further improve productivity29SPW Links the Wireless FlowTestBenchHDLHDLTestBenchHDLC+, OMIC/C+, MATLABVerilog-AImpl. ModelsHDL, C HDLSWSDL, OMI30RF Design SolutionTestBenchHDLHDLTestBenchHDLC+, OMIC

38、/C+, MATLABVerilog-AImpl. ModelsHDL, C HDLSWSDL, OMI31RF DesignSystems Verification with SPW Common problem: RF IC is designed, but system simulation doesnt accurately model the impairments of the IC! Co-sim of an accurate IC model with the full system is too slow Spectre RF Circuit Simulator - SPW

39、link allows input of RFIC simulation data into SPW through the use of SPW K, J-Models Simulate baseband performance of RFIC once in Spectre RF and use these data files as a “model” in SPW for fast data flow simulations System improvements can now be done in either the RFIC or in DSP the processing32

40、Spectre RF link to SPW Model Link to SPW for system simulation Helps optimize system metrics e.g bit error rate 100,000 x faster than co-simulation methods enables complete end-to-end model of RF to baseband DSP ASCII data format Simulates RF IC system impairments K-Model for receivers; RF to baseba

41、nd Dynamic model with memory Models AM/AM, AM/PM conversion, and amplitude dependant pole-zero movement J-Model for transmitters ; baseband to RF Models static AM/AM, AM/PM, PM/AM, PM/PM conversion (distortion) mechanisms Can use different models for different system tests, i.e. with or without inte

42、rferes33RF-to-Baseband Simulation Link34SpectreRF Baseband Library Aids RF Architectural Exploration Define the optimal RF system to meet specification and time-to-profit Saves time and money = eliminate re-code/re-spin Ideal for digital communications systems: 3G, WLAN, etc. Fast, Fast, Fast: compl

43、ex simulations run in seconds Enables RF/Digital trade-off analyses RF, PLL , and behavioural Verilog-A modules included The competition uses slower passband models, we also have these models available. Useful throughout the top-down design process Integrated into Cadence Custom IC design environmen

44、t Links to SPW for complex DSP-RF-DSP system simulations FOC enhancement to SpectreRF IC446 version35Seminar Agenda10:15 - 10:35IntroductionCadence wireless initiative What is Bluetooth?10:35 - 11:25 Capture, analysis, and optimization of digital basebandwireless designs using SPW 11:25 - 12:15Captu

45、re, analysis and optimization of wirelessplatforms using VCC12:15 - 1:15Lunch 1:15 - 1:45Hardware-based system verification solutions forclosed-loop power control, BER analysis and SWdevelopment 1:45 - 2:05SPW link with NC-SIM for digital baseband verification and cross debugging with C/C+ test benc

46、hes and RTL 2:05 - 2:35Synthesizing Digital Baseband designs using theBuildGates Wireless Datapath Synthesis Option 2:35 - 3:15 Demo, Q&A 36TestBenchHDLHDLTestBenchHDLC+, OMIC/C+, MATLABVerilog-AImpl. ModelsHDL, C HDLSWSDL, OMIWireless System Platform Integration37UA 960 SFO CDG (Paris)on time 7:30

47、pmThe Application ChallengeBluetooth Enabled Airport Services The meeting ran over you are late for your flight! You enter the airport You get rid of the car as fast as possible (while you are on the cell phone) While you are in line for the garage you pass a Bluetooth cell Your cell phone automatic

48、ally downloads via Bluetooth a current airport map and the flight status38The Design Challenge How can I add the additional JPWG decoder function and a Bluetooth core? How fast will the software run under this cache conditions? Do I have confidence that the HW/SW system will work in the lab? How do

49、I partition between HW and SW running on a processor? Which processor type should I select? Will I have bottlenecks on my bus? How about bus contention? Do I meet throughput and latency requirements in a proposed architecture? Will I meet decoding deadlines? Will I service a critical interrupt in ti

50、me? Will the Architecture Platform be sufficient?39The Platform-based Design ConceptTaking Design Block Reuse to the Next LevelRapid Prototype forEnd-Customer EvaluationSoC Derivative DesignMethodologiesSystem-level performanceevaluation environmentApplicationSpaceMethodology / Flows:Foundation Bloc

51、kMEMFPGACPUProcessor(s), RTOS(es) and SW architecture*IP can be hardware (digital or analogue) or software. IP can be hard, soft orfirm (HW), source orobject (SW)Scaleablebus, test, power, IO,clock, timing architectures+ Reference DesignProgrammableSW IPHardware IPPre-Qualified/VerifiedFoundation-IP

52、*Foundry-SpecificPre-QualificationFoundry Targeting Flow40Unifying the Integration Platform Supply Chain Customer Challenge System and semi conductor house “speak different languages” System integrators take a pre-implementation view of the design Designers focus on “what” needs to happen in design

53、not “how” Semiconductor houses are more silicon focused RTL Verilog has been considered “high level” until recently This leads to difficulty in communication between the two ends of the platform supply chain Cadence Solution System houses use VCC to design product platforms at a pre-implementation l

54、evel SPW for System Block creation and validation Semi house uses VCC to deliver system-level view of silicon platform to their system customers SPWs HDS to connect to IC implementation flows41Evaluate System Integration!Before Implementation? Where And How?Today Integration of Implementation level

55、models happens after the module implementation and after partitioning has been decidedTomorrow This will fail if users did not assess implementation aspects earlierTimed/Clocked Implementation ModelsAssemblerAbstractionSPWSDL, UMLMatlabC/C+CossapCoCentricModelsRTL VerilogSystemC 1.0BehavioralSynthes

56、isHDSTestBenchBHDLC/C+SPWUn-timed Design Entry / Modeling TechniquesHWSWImpl.ModelsSynthesis / Place & Route etc.Implementation Level VerificationSoftwareAssemblyHardwareAssembly42Timed/Clocked Implementation ModelsAssemblerAbstractionRTL VerilogSystemC 1.0SWHWCharacterizedPerformanceEstimated and C

57、haracterized Performance ModelsModelsImpl.ModelsSPWSDL, UMLMatlabC/C+CossapCoCentricBHDLC/C+SPWUn-timed Design Entry / Modeling TechniquesSystemModelsOMICadence Virtual Component Co-design Enables IP IntegrationSynthesis / Place & Route etc.Implementation Level VerificationSoftwareAssemblyHardwareAs

58、semblyCommunication Refinement Communication IntegrationIP Block System IntegrationPerformance Analysis and Platform ConfigurationSystem IntegrationPlatform FunctionPlatform ArchitectureEmbedded System RequirementsIP Integration from general abstractsystem requirements(un-timed, behavioral) through

59、various steps of interface refinements to the integration of implementation modelswith interface synthesisIP Block System IntegrationEmbedded System Requirements43Executable System LevelBlock Level SpecificationIP Block DefinitionPerformance Analysis and Platform ConfigurationSystem IntegrationPlatf

60、orm FunctionPlatform ArchitectureEmbedded System RequirementsIP Block Integration for Evaluation is only feasible at the un-clocked System LevelThe VCC Frontend Efficient Design Space Exploration44Functional IP Integration Question: How does the functional integrated design work? VCC allows to impor