基于VHDL语言串口控制器课程设计(共13页)

1、EDA课程设计题目(tm)：串口控制器设计(shj) 班级(bnj)： 姓名： 学号： 一：串口简介(jin ji)串口是可以在使用一根线发送数据的同时用另一根线接收数据。串口通信协议也可以用于获取远程采集设备(shbi)的数据。通过RS232以实现计算机之间、计算机与设备之间相互(xingh)通信，目前仍是通讯领域广泛使用的方法之一。几乎每台计算机都有一两个串行接口，用来与调制解调器、实验室设备、工控设备、POS终端等进行数据传输。RS-232以其方便、经济的实现特点，一直深受工程界的青睐。不论是在电力、工控还是电信、金融交通等诸多行业都有广泛的应用。系统主芯片采用RS-232串口通信控制器

2、，由基本时钟发生电路模块，复位电路模块，波特率选择模块，数据帧格式选择模块，串并转换模块组成。经编译和仿真所设计的程序，在可编程逻辑器件上下载验证，结合FPGA技术高度灵活性与模块化的特点，实现基本RS-232总线通信的功能，以实现串口数据帧结构选择，串并转换，波特率选择等功能。通过软件仿真，得到功能的验证，并进行功能逻辑模块的整合，从而验证设计的可行性与可靠性。本模块的功能是验证实现和PC机进行基本的串口通信的功能。需要在PC机上安装一个串口调试工具来验证程序的功能。程序实现了一个收发一帧10个bit（即无奇偶校验位）的串口控制器，10个bit是1位起始位，8个数据位，1个结束位。串口的波特

3、率由程序中定义的div_par参数决定，更改该参数可以实现相应的波特率。程序当前设定的div_par 的值是0 x104，对应的波特率是9600。用一个8倍波特率的时钟将发送或接受每一位bit的周期时间划分为8个时隙以使通信同步.程序的工作过程是：串口处于全双工工作状态，按动SW0，FPGA向PC发送“welcome字符串（串口调试工具设成按ASCII码接受方式）；PC可随时向FPGA发送0-F的十六进制数据，FPGA接受后显示在7段数码管上。二：设计方案。1:接收模块设计串口接收模块针对于接收串行数据进行协议包的解析，实现串行数据输入，并行数据输出的功能，从接收判断的角度，实现了对于串口协议

4、的解析功能。2: 发送模块设计串口发送模块针对于接收并行数据进行协议的组包设计，实现并行数据输入，串行数据输出的功能，从发送的角度，实现了对于串口协议的组合功能。发送模块设计与接收模块类似，依然针对波特率，数据位，校验位，停止位进行控制，实现全双向的串口通信控制功能。三：电路原理图四：软件(run jin)流程五：实验(shyn)源程序library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY UART IS PORT ( clk :

5、IN std_logic; rst : IN std_logic; rxd : IN std_logic; txd : OUT std_logic; en : OUT std_logic_vector(7 downto 0); seg_data : OUT std_logic_vector(7 DOWNTO 0); key_input : IN std_logic ); END UART;ARCHITECTURE arch OF UART IS - /inner reg/ SIGNAL div_reg : std_logic_vector(15 DOWNTO 0); SIGNAL div8_t

6、ras_reg : std_logic_vector(2 DOWNTO 0); SIGNAL div8_rec_reg : std_logic_vector(2 DOWNTO 0); SIGNAL state_tras : std_logic_vector(3 DOWNTO 0); SIGNAL state_rec : std_logic_vector(3 DOWNTO 0); SIGNAL clkbaud_tras : std_logic; SIGNAL clkbaud_rec : std_logic; SIGNAL clkbaud8x : std_logic; SIGNAL recstar

7、t : std_logic; SIGNAL recstart_tmp : std_logic; SIGNAL trasstart : std_logic; SIGNAL rxd_reg1 : std_logic; SIGNAL rxd_reg2 : std_logic; SIGNAL txd_reg : std_logic; SIGNAL rxd_buf : std_logic_vector(7 DOWNTO 0); SIGNAL txd_buf : std_logic_vector(7 DOWNTO 0); SIGNAL send_state : std_logic_vector(2 DOW

8、NTO 0);- SIGNAL cnt_delay : std_logic_vector(19 DOWNTO 0);- SIGNAL start_delaycnt : std_logic; SIGNAL key_entry1 : std_logic; SIGNAL key_entry2 : std_logic; -/ CONSTANT div_par : std_logic_vector(15 DOWNTO 0) := 0000000100000100; SIGNAL txd_xhdl3 : std_logic; BEGIN en =01010101 ;- txd = txd_xhdl3; t

9、xd_xhdl3 = txd_reg ; PROCESS(clk,rst) BEGIN IF (NOT rst = 1) THEN cnt_delay = 00000000000000000000; start_delaycnt = 0; ELSIF(clkEVENT AND clk=1)THEN IF (start_delaycnt = 1) THEN IF (cnt_delay /= 11000011010100000000) THEN cnt_delay = cnt_delay + 00000000000000000001; ELSE cnt_delay = 00000000000000

10、000000; start_delaycnt = 0; END IF; ELSE IF (NOT key_input=1) AND (cnt_delay = 00000000000000000000) THEN start_delaycnt = 1; END IF; END IF; END IF; END PROCESS; PROCESS(clk,rst) BEGIN IF (NOT rst = 1) THEN key_entry1 = 0; ELSIF(clkEVENT AND clk=1)THEN IF (key_entry2 = 1) THEN key_entry1 = 0; ELSE

11、IF (cnt_delay = 11000011010100000000) THEN IF (NOT key_input = 1) THEN key_entry1 = 1; END IF; END IF; END IF; END IF; END PROCESS; PROCESS(clk,rst) BEGIN IF (NOT rst = 1) THEN div_reg = 0000000000000000; ELSIF(clkEVENT AND clk=1)THEN IF (div_reg = div_par - 0000000000000001) THEN div_reg = 00000000

12、00000000; ELSE div_reg = div_reg + 0000000000000001; END IF; END IF; END PROCESS; PROCESS(clk,rst) BEGIN IF (NOT rst = 1) THEN clkbaud8x = 0; ELSIF(clkEVENT AND clk=1)THEN IF (div_reg = div_par - 0000000000000001) THEN clkbaud8x = NOT clkbaud8x; END IF; END IF; END PROCESS; PROCESS(clkbaud8x,rst) BE

13、GIN IF (NOT rst = 1) THEN div8_rec_reg = 000; ELSE IF(clkbaud8xEVENT AND clkbaud8x = 1) THEN IF (recstart = 1) THEN div8_rec_reg = div8_rec_reg + 001; END IF; END IF; END IF; END PROCESS; PROCESS(clkbaud8x,rst) BEGIN IF (NOT rst = 1) THEN div8_tras_reg = 000; ELSE IF(clkbaud8xEVENT AND clkbaud8x = 1

14、) THEN IF (trasstart = 1) THEN div8_tras_reg = div8_tras_reg + 001;- END IF; END IF; END IF; END PROCESS; PROCESS(div8_rec_reg) BEGIN IF (div8_rec_reg = 111) THEN clkbaud_rec = 1; ELSE clkbaud_rec = 0; END IF; END PROCESS; PROCESS(div8_tras_reg) BEGIN IF (div8_tras_reg = 111) THEN clkbaud_tras = 1;

15、ELSE clkbaud_tras = 0; END IF; END PROCESS; PROCESS(clkbaud8x,rst) BEGIN IF (NOT rst = 1) THEN txd_reg = 1; trasstart = 0; txd_buf = 00000000; state_tras = 0000; send_state = 000; key_entry2 = 0; ELSE IF(clkbaud8xEVENT AND clkbaud8x = 1) THEN IF (NOT key_entry2 = 1) THEN IF (key_entry1 = 1) THEN key

16、_entry2 = 1; txd_buf IF (NOT trasstart=1) AND (send_state 111) ) THEN trasstart = 1; ELSE IF (send_state 111) THEN IF (clkbaud_tras = 1) THEN txd_reg = 0; state_tras = state_tras + 0001; END IF; ELSE key_entry2 = 0; state_tras - IF (clkbaud_tras = 1) THEN txd_reg = txd_buf(0); txd_buf(6 DOWNTO 0) =

17、txd_buf(7 DOWNTO 1); state_tras IF (clkbaud_tras = 1) THEN txd_reg = txd_buf(0); txd_buf(6 DOWNTO 0) = txd_buf(7 DOWNTO 1); state_tras IF (clkbaud_tras = 1) THEN txd_reg = txd_buf(0); txd_buf(6 DOWNTO 0) = txd_buf(7 DOWNTO 1); state_tras IF (clkbaud_tras = 1) THEN txd_reg = txd_buf(0); txd_buf(6 DOW

18、NTO 0) = txd_buf(7 DOWNTO 1); state_tras IF (clkbaud_tras = 1) THEN txd_reg = txd_buf(0); txd_buf(6 DOWNTO 0) = txd_buf(7 DOWNTO 1); state_tras IF (clkbaud_tras = 1) THEN txd_reg = txd_buf(0); txd_buf(6 DOWNTO 0) = txd_buf(7 DOWNTO 1); state_tras IF (clkbaud_tras = 1) THEN txd_reg = txd_buf(0); txd_

19、buf(6 DOWNTO 0) = txd_buf(7 DOWNTO 1); state_tras IF (clkbaud_tras = 1) THEN txd_reg = txd_buf(0); txd_buf(6 DOWNTO 0) = txd_buf(7 DOWNTO 1); state_tras IF (clkbaud_tras = 1) THEN txd_reg = 1; txd_buf = 01010101; state_tras IF (clkbaud_tras = 1) THEN state_tras = state_tras + 0001; send_state = send

20、_state + 001; trasstart txd_buf txd_buf txd_buf txd_buf txd_buf txd_buf txd_buf IF (clkbaud_tras = 1) THEN state_tras = state_tras + 0001; trasstart = 1; END IF; END CASE; END IF; END IF; END IF; END PROCESS; PROCESS(clkbaud8x,rst) BEGIN IF (NOT rst = 1) THEN rxd_reg1 = 0; rxd_reg2 = 0; rxd_buf = 00

21、000000; state_rec = 0000; recstart = 0; recstart_tmp = 0; ELSE IF(clkbaud8xEVENT AND clkbaud8x = 1) THEN rxd_reg1 = rxd; rxd_reg2 = rxd_reg1; IF (state_rec = 0000) THEN IF (recstart_tmp = 1) THEN recstart = 1; recstart_tmp = 0; state_rec = state_rec + 0001; ELSE IF (NOT rxd_reg1 AND rxd_reg2) = 1) T

22、HEN recstart_tmp = 0001 AND state_rec=1000) THEN IF (clkbaud_rec = 1) THEN rxd_buf(7) = rxd_reg2; rxd_buf(6 DOWNTO 0) = rxd_buf(7 DOWNTO 1); state_rec = state_rec + 0001; END IF; ELSE IF (state_rec = 1001) THEN IF (clkbaud_rec = 1) THEN state_rec = 0000; recstart seg_data seg_data seg_data seg_data seg_data seg_data seg_data seg_data seg_data seg_data seg_data seg_data seg_data seg_data seg_data seg_data seg_data = 11111111; END CASE; END PROCESS;END arch;六：总结(zngji)在此次(c c)的RS-232串口通信(tng xn)控制器设计过程中，更进一步地熟悉有关数字电路的知识和具体应用。学会了利QuarterII软件进行原理图的绘制，硬件描述语言VHDL的编写，程序的仿真等工作。并能根据仿真