课件：数字电路第六章课件

1、Chapter6 Combinational Logic Design Practices组合逻辑电路Chapter OutlineDocumentation StandardsDigital Circuit Timing and Propagation delayCombinational Logic Design Structures :- Decoders - Encoders - Three-State Buffers- Multiplexers- EXCLUSIVE OR Gates and Parity Circuits- Comparators- Adders/ Subtract

2、ors- Arithmetic Logic Units ( ALUs)6.1 Documentation Standard(文档标准) Documentation of a digital system should provide the necessary information for building, testing ,operating , and maintaining the system.Specification: Description of Interface and Function (说明书：接口及功能描述)Block Diagram: Systems Major

3、Function Module and their Basic Interconnections (方框图 ：主要功能模块及其互联 P345图6-1)Schematic Diagram: showing all the components, their types, and all interconnections (原理图 （P360图6-17）)Block DiagramSchematic DiagramHierarchichal schematic structureDocumentation Standard(文档标准)Timing Diagram: showing the logi

4、c signals as a function of time (定时图 （P363图6-19）)Structure Logic Device Description: showing the operation of the structures (结构化逻辑器件描述)Circuit Description : Explains how the circuit works internally. (电路描述：解释电路内部如何工作)“Hierarchical Design”Gate Symbols (门的符号)&11DeMorgan equivalent symbols(等效门符号（摩根定理）

5、)Inverter (反相器)Buffer (缓冲器)Which symbol to use?depends on signal names and active levels.Signal Names and Active Levels (信号名和有效电平)Signal name: a descriptive alphanumeric label for each input/output signal.In real system, well-chosen names convey information to readersEach signal name should have an

6、active-level associated with it. (有效电平)Active High （高电平有效）Active Low （低电平有效）READYREQUESTGOREADY_LREQUEST_LGO_LSignal Name and Active Levels (信号名和有效电平)The signal is asserted when it is in its active level and negated ( or deasserted ) when its not in its active level.An Inversion Bubble to Indicate a

7、n Active-Low Pin (有反相圈的引脚 表示低电平有效)Active low signal has a suffix of _L as part of the variable name.Signal Name and Active Levels (信号名和有效电平)ENABLEDOMYTHINGENABLEDOMYTHING AND,OR,and a large-scale logic element have active-high inputs and outputsThe same elements with active-low inputs and outputs Gi

8、ven Logic Function as Occurring inside that symbolic outline. (给定逻辑功能只在符号框的内部发生)Bubble-to-Bubble Logic Design(“圈到圈”的逻辑设计)Purpose : To make it easy to understand the function of the Logic circuit by choosing appropriate logic symbols and signal names including active-level designators. ERRORFAIL_LOVE

9、RFLOW_L ERRORFAIL_LOVERFLOW_LBubble-to-Bubble Logic Design(“圈到圈”的逻辑设计)AASELBDATAAASELBADATA_LBDATA_LDATA6.2 Circuit Timing (电路定时)Propagation Delay (传播延迟) - A Signal Path as the Time that it takes for a Change at the Input to Produce a Change at the Output of the Path(信号通路输入端的变化引起输出端变化所需的时间)tpHL and

10、tpLH Maybe DifferentPropagation DelayTiming Analysis: Worst-Case Delay(定时分析：取最坏情况延迟)Maximum Delay(最大延迟)Typical Delay(典型延迟)Minimum Delay(最小延迟)080804323232P366 表6-2152022226.2 Circuit Timing (电路定时)Timing Diagram定时图（时序图）GOREADYDAT6.2 Circuit Timing (电路定时)Causality and Propagation Delay (因果性和传播延迟）GOREAD

11、YDATtDATtDATtRDYtRDYGOREADYDAT6.2 Circuit Timing (电路定时)Timing Diagram定时图（时序图）Minimum and Maximum Delay (最小和最大延迟）GOREADYDATtRDYmintRDYmax6.2 Circuit Timing (电路定时)Certain and Uncertain Transitions (确切的和不确切的转换）WRITE_LDATAOUTDATAINtOUTmaxtsetuptOUTminCommonly Used MSI Combinational Logic DeviceDecoders

12、(译码器)Encoders (编码器)Multiplexers (多路复用器)Parity Circuits (奇偶校验)Comparators (比较器)Adders (加法器)Decoder and Encoder(译码器和编码器)Multiple-Input, Multiple-Output Logic Circuit(多输入、多输出电路)Enable Inputs(使能输入)(输入编码)(输出编码)Map 映射Enable Inputs must be Asserted to perform Normal Mapping Function(使能输入有效才能实现正常映射功能)Input

13、Code WordOutput Code WordDecoder（译码器） Normally Output Code has More bits than its Input Code (一般来说，输出编码比输入编码位数多)Encoder（编码器） Output Code has Fewer bits than its Input Code called an Encoder(输出编码比输入编码位数少，则常称为编码器)Decoder and Encoder(译码器和编码器)Most Commonly Used Case使能输入编码输出编码Map 映射Decoder（译码器）Encoder（编码

14、器）N-Bit Binary Code(n位二进制码)2n 中取1码使能输入编码输出编码Map 映射2n中取1码n位二进制码( 1-out-of 2n )6.4 Decoder（译码器）Binary Decoder (二进制译码器)1. 2-to-4 Decoder2-to-4DecoderY0Y1Y2Y3I0I1EN 0 X X 0 0 0 0 1 0 0 0 0 0 1 1 0 1 0 0 1 0 1 1 0 0 1 0 0 1 1 1 1 0 0 0InputsEN I1 I2Outputs Y3 Y2 Y1 Y0( 2-4二进制译码器真值表 )Truth Table for a 2-t

15、o-4 Binary DecoderY0 = EN ( I1 I2 )Y1 = EN ( I1 I2 )Y2 = EN ( I1 I2 )Y3 = EN ( I1 I2 )Yi = EN miDecoder（译码器） 0 X X 0 0 0 0 1 0 0 0 0 0 1 1 0 1 0 0 1 0 1 1 0 0 1 0 0 1 1 1 1 0 0 0InputsEN I1 I2Outputs Y3 Y2 Y1 Y0( 2-4二进制译码器真值表 )Truth Table for a 2-to-4 Binary Decoder2-to-4 DecoderThe 74x139 Dual 2-to

16、-4 Decoder(双2-4译码器74x139) 1 X X 1 1 1 1 0 0 0 1 1 1 0 0 0 1 1 1 0 1 0 1 0 1 0 1 1 0 1 1 0 1 1 1InputsG B AOutputs Y3_L Y2_L Y1_L Y0_LTruth Table for One-half of a 74x139Dual 2-to-4 Decoder74x1391Y01Y11Y21Y31G1A1B2Y02Y12Y22Y32G2A2B1 2 315 14 1345671211109 Logic Symbols for Large-Scale ElementY0Y1Y2Y3

17、GAB1/2 74x139Y0Y1Y2Y3GAB1/2 74x139Y0Y1Y2Y3GAB1/2 74x139G_LABY0_LY1_LY2_LY3_L0 0 0 0 0 0 0 10 0 0 0 0 0 1 00 0 0 0 0 1 0 00 0 0 0 1 0 0 00 0 0 1 0 0 0 00 0 1 0 0 0 0 00 1 0 0 0 0 0 01 0 0 0 0 0 0 03-to-8DecoderI2I1I0Y0Y1Y7Yi = EN mi1 1 1 1 1 1 1 01 1 1 1 1 1 0 11 1 1 1 1 0 1 11 1 1 1 0 1 1 11 1 1 0 1

18、 1 1 11 1 0 1 1 1 1 11 0 1 1 1 1 1 10 1 1 1 1 1 1 1Decoder（译码器）0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1I2I1I0Y7Y1Y0Y2Y3Y4Y5Y6(3-8二进制译码器真值表)Truth Table for a 3-to- 8 Binary Decoder2. 3-to-8 DecoderThe 74x138 3-to-8 Decoder(3-8译码器74x138)低位高位Y0_LY1_LY7_LY2_LY3_LY4_LY5_LY6_LENG1G2A_LG2B_LENEN = G1 G2A G

19、2B = G1 G2A_L G2B_L Yi = EN miYi_L = Yi = ( EN mi )ABCG1G2AG2BY0Y1Y2Y3Y4Y5Y6Y774x138EnableY6_L=(CBA)=m6Logic diagram for the 74x138用74x138设计4-16译码器Cascading Binary Decoders N0N1N2N3EN_L+5VD0_LD7_LD8_LD15_L思路： 16个输出需要 片74x138？Y0Y7ABCG1G2AG2BY0Y7ABCG1G2AG2BU1U2 任何时刻只有一片在工作。 4个输入中，哪些位控制片选哪些位控制输入Conside

20、r: How to make a 5-to-32 Decoder with 3-to-8 Decoder?32个输出需要多少片74x138？控制任何时刻只有一片工作 利用使能端5个输入的低3位控制输入5个输入的高2位控制片选 利用 2-4 译码器P391 图6-37Use decoder and Gates to realize logic functionF = (X,Y,Z) (0,3,6,7) = (X,Y,Z) (1,2,4,5)Binary decoder：Yi = EN mi Enable inputs are asserted: Yi = mi Yi_L = Yi= mi = M

21、iABCG1G2AG2BY0Y1Y2Y3Y4Y5Y6Y774x138Use decoder and Gates to realize logic functionZYXABCG1G2AG2BY0Y1Y2Y3Y4Y5Y6Y774x138F+5VF = (X,Y,Z) (0,3,6,7)当使能端有效时Yi = miUse decoder and Gates to realize logic functionZYXABCG1G2AG2BY0Y1Y2Y3Y4Y5Y6Y774x138+5VFF = (X,Y,Z) (0,3,6,7)= M1 M2 M4 M5= m1 m2 m4 m5F = (X,Y,Z

22、) ( 1, 2, 4, 5 )ZYXABCG1G2AG2BY0Y1Y2Y3Y4Y5Y6Y774x138+5VFBCD Decoder (二十进制译码器)Inputs : 4-bit BCD codeOutputs :1-out-of 10 CodeY0Y9I0I1I2I3多余的6个状态如何处理？输出均无效：拒绝“翻译”作为任意项处理 电路内部结构简单二-十进制译码器0 0 0 0 0 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 00 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01 1 1 10

23、1 1 1 1 1 1 1 1 11 0 1 1 1 1 1 1 1 11 1 0 1 1 1 1 1 1 11 1 1 0 1 1 1 1 1 11 1 1 1 0 1 1 1 1 11 1 1 1 1 0 1 1 1 11 1 1 1 1 1 0 1 1 11 1 1 1 1 1 1 0 1 11 1 1 1 1 1 1 1 0 11 1 1 1 1 1 1 1 1 01 1 1 1 1 1 1 1 1 11 1 1 1 1 1 1 1 1 11 1 1 1 1 1 1 1 1 11 1 1 1 1 1 1 1 1 11 1 1 1 1 1 1 1 1 11 1 1 1 1 1 1 1 1

24、 1I3 I2 I1 I00123456789Y0_L Y9_L伪码Dont careSeven-Segment Decoders(七段显示译码器)abcdefgdpNormally use ：Light-Emitting Diodes（LED,半导体数码管）Liquid-Crystal Display（LCD,液晶数码管）LED显示器件LCD显示器件LEDabcdefgdp公共阴极abcdefgdp公共阳极点阵型显示器笔划段型显示器Seven-Segment DecodersInput code: 4-bit BCD 输入信号：BCD码（用A3A2A1A0表示）Output Code: Se

25、ven-Segment Code输出：七段码（的驱动信号）a g 1 - On，0 - Offabcdefg11111101101101001111174LS48显示字型与输入的对应关系0 0 0 0 0 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 00 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01 1 1 11 1 1 1 1 1 00 1 1 0 0 0 01 1 0 1 1 0 11 1 1 1 0 0 10 1 1 0 0 1 11 0 1 1 0 1 10 0 1 1 1 1 11 1

26、 1 0 0 0 01 1 1 1 1 1 11 1 1 0 0 1 10 0 0 1 1 0 10 0 1 1 0 0 10 1 0 0 0 1 11 0 0 1 0 1 10 0 0 1 1 1 10 0 0 0 0 0 0A3 A2 A1 A0a b c d e f g0123456789101112131415A3A2A1A000 01 11 10000111101001100011000111a七段显示译码器的真值表Ya = A3A2A1A0 + A3A1 + A2A0Yb = A3A1 + A2A1A0 + A2A1A0Karnaugh Maps for BCD-Seven-Seg

27、ment Decoder (BCD - 七段显示译码器的卡诺图)Yc = A3A2 + A2A1A0Yd = A2A1A0 + A2A1A0 + A2A1A0Karnaugh Maps for BCD-Seven-Segment Decoder (BCD - 七段显示译码器的卡诺图)Karnaugh Maps for BCD-Seven-Segment Decoder (BCD - 七段显示译码器的卡诺图)Ye = A2A1 + A0Yf = A3A2A0 + A1A0 + A2A1Karnaugh Maps for BCD-Seven-Segment Decoder (BCD - 七段显示译

28、码器的卡诺图)Yg = A3A2A1 + A2A1A0Design BCD-Seven-Segment Decoder逻辑抽象，得到真值表输入信号：BCD码（A3A2A1A0）输出：七段码（的驱动信号）a g 1 表示亮，0 表示灭选择器件类型采用基本门电路实现，利用卡诺图化简采用二进制译码器实现，变换为标准和形式电路处理，得到电路图abcdefg6.5 Encoder（编码器）Binary EncoderA0A1A2I0I1I71 0 0 0 0 0 0 0 0 0 00 1 0 0 0 0 0 0 0 0 10 0 1 0 0 0 0 0 0 1 00 0 0 1 0 0 0 0 0 1

29、10 0 0 0 1 0 0 0 1 0 00 0 0 0 0 1 0 0 1 0 10 0 0 0 0 0 1 0 1 1 00 0 0 0 0 0 0 1 1 1 1 2nInputsnOutputsI0 I1 I2 I3 I4 I5 I6 I7A2 A1 A0(3位二进制编码器的真值表)Truth Table for a 8-to-3 EncoderGuarantee: -one and only one input will be asserted at a time( 任何时刻只有一个输入端有效。)1 0 0 0 0 0 0 0 0 0 00 1 0 0 0 0 0 0 0 0 10

30、 0 1 0 0 0 0 0 0 1 00 0 0 1 0 0 0 0 0 1 10 0 0 0 1 0 0 0 1 0 00 0 0 0 0 1 0 0 1 0 10 0 0 0 0 0 1 0 1 1 00 0 0 0 0 0 0 1 1 1 1I0 I1 I2 I3 I4 I5 I6 I7A2 A1 A0(3位二进制编码器的真值表)Encoder（编码器）Truth Table for a 8-to-3 Encoderthis is the exact opposite of a decoderA0 = I1 + I3 + I5 + I7A1 = I2 + I3 + I6 + I7A2

31、= I4 + I5 + I6 + I7How to deal with multiple requests? -more than One Inputs are assertedPriority（优先级）1 0 0 0 0 0 0 0 0 0 00 1 0 0 0 0 0 0 0 0 10 0 1 0 0 0 0 0 0 1 00 0 0 1 0 0 0 0 0 1 10 0 0 0 1 0 0 0 1 0 00 0 0 0 0 1 0 0 1 0 10 0 0 0 0 0 1 0 1 1 00 0 0 0 0 0 0 1 1 1 1I0 I1 I2 I3 I4 I5 I6 I7A2 A1 A

32、0(3位二进制编码器的真值表)Encoder（编码器）Truth Table for a 8-to-3 EncoderA2A1A0IDLEI7I6I5I4I3I2I1I0In order to write logic equations for the priority encoders outputswe first define eight intermediate variables H0-H7Highest-Priority( 数大优先 )Priority Encoder (优先编码器)H7 = I7H6 = I6 I7H5 = I5 I6 I7H0 = I0 I1 I2 I6 I7A

33、2A1A0IDLEI7I6I5I4I3I2I1I0In order to write logic equations for the priority encoders outputswe first define eight intermediate variables H0-H7Highest-Priority( 数大优先 )Priority Encoder (优先编码器)A2 = H4 + H5 + H6 + H7A1 = H2 + H3 + H6 + H7A0 = H1 + H3 + H5 + H7 The IDLE Output is asserted if No Inputs ar

34、e asserted. IDLE = I0 I1 I6 I7输入输出EI_L有效没有输入请求EO_L有效Enable Input有输入请求EI_L有效GS_L有效A2A1A0EI74x148I7I6I5I4I3I2I1I0GSEO54321131211106791415使能输出，用于级联 EO选通输出GSThe 74x148 Priority EncoderA2A1A0GSEOEII7I0A2A1A0GSEOEII7I0Q15_LQ8_LQ7_LQ0_LY0Y1Y2Y3GS2个74x148级联为16-4优先编码器输入：由864，需8片74x148每片优先级不同（怎样实现？） 保证高位无输入时，

35、次高位才工作 高位芯片的EO端接次高位芯片的EI端用8-3优先编码器74x148级联为64-6优先编码器A2A1A0GSEOEII7I0片间优先级的编码 利用第9片74x148 每片的GS端接到第9片的输入端 第9片的输出作为高3位（RA5RA3）片内优先级片间优先级 输出：6位低3位高3位8片输出A2A0通过或门作为最终输出的低3位RA2RA0分析判定优先级电路：（利用74x148 ） 8个_电平有效输入I0_LI7_L，_的优先级最高 地址输出A2A0，_电平有效 若输出AVALID高电平有效，则表示_A2A1A0GSEOEI74x148I7I0I0_LI7_LA2A1A0AVALID低I

36、0_L至少有一个输入有效高P514 题6.53设计优先级电路：（利用74x148 ） 8个输入I0I7高电平有效，I7优先级最高 地址输出A2A0，高电平有效 如果没有输入有效，输出IDLE有效I7I0A2A1A0IDLEA2A1A0GSEOEII7I074x148P514 题6.526.6 Three-State Devices (三态器件)Three-State Buffer (Three-State Driver)三态缓冲器（三态驱动器）Three States: Active High(1) ，Active Low (0), Hi-Z Various three-state buffe

37、rsThree-State Devices Three-State Device allow Multiple Sources to Share a Single “Party Line” As long as Only One device “talk” on the Line at a time （三态器件允许多个信号源共享单个“同线”， 条件是每次只有一个器件工作） (Figure 6-52)Typical Three-State Devices are Designed So that they go into the Hi-Z state Faster than they come

38、out of the Hi-Z state.（对典型的三态器件，进入高阻态比离开高阻态的时间快）ABCG1G2AG2BY0Y1Y2Y3Y4Y5Y6Y774x138EN1EN2_LEN3_LSSRC0SSRC1SSRC2fighting（冲突）利用使能端进行时序控制三态器件允许信号共享单个“同线”（party line）典型的三态器件，进入高阻态比离开高阻态快P0P1P7SDATAEN1EN2_L, EN3_Lmax(tpLZmax, tpHZmax)min(tpZLmin, tpZHmin)SSRC2:001237SDATAP0P1P2P3P7Dead Time(截止时间)Standard S

39、SI and MSI Three-State Buffer (标准SSI和MSI三态缓冲器)The 74x541 Octal three-state bufferA1A2A3A4A5A6A7A8G1G2Y1Y2Y3Y4Y5Y6Y7Y874x541A1A8G1G2Y1Y874x541DB0:7A1A8G1G2Y1Y874x541Notation of Data Bus （数据总线的表示法）A1B1DIRTransfer Data in Either Directions By Using Three-State Transceiver(利用三态缓冲器实现数据双向传送)Bus Transceive

40、r (总线收发)DIRG_L6.7 Multiplexer（多路复用器）Digital Switch, Multi-Switch, Data Selector (又称数据开关、多路开关、数据选择器) （缩写：MUX）Under Select Controlling Signals, Select One of the Multi-Inputs to the Output (在选择控制信号的作用下， 从多个输入数据中选择其中一个作为输出。)MultiplexerENSELD0Dn-1YEnable 使能Select 选择n个1位数据源数据输出（1位）ENSELD0Dn-1YEnable(使能)S

41、elect(选择)N Data Sources(n个b位数据源)Data Output(数据输出)（b位）EN_L C B A Y Y_L1 X X X0 0 0 00 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 00 1 1 1 0 1D0 D0D1 D1D2 D2D3 D3D4 D4D5 D5D6 D6D7 D7(8输入1位多路复用器)Truth Table for a 74x1518-Input,1-bit MultiplexerENABCD0D1D2D3D4D5D6D7YY74x15143211514131211109756EN_L C B A Y Y

42、_L1 X X X0 0 0 00 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 00 1 1 1 0 1D0 D0D1 D1D2 D2D3 D3D4 D4D5 D5D6 D6D7 D7(8输入1位多路复用器)Truth Table for a 74x1518-Input,1-bit MultiplexerHow to get a logic equation for a MUX output?输入G_L S1 X0 00 1 0 0 0 01A 2A 3A 4A1B 2B 3B 4B(2输入4位多路复用器)Truth Table for a 74x157输出1

43、Y 2Y 3Y 4Y2-Input,4-bit MultiplexerGS1A1B2A2B3A3B4A4B1Y2Y3Y4Y74x157235611101413115479121G_L 2G_L B A 1Y 2Y1 1 X X0 0 0 00 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 00 1 1 11 0 0 01 0 0 11 0 1 01 0 1 1 0 01C0 2C01C1 2C11C2 2C21C3 2C31C0 01C1 01C2 01C3 0 0 2C0 0 2C1 0 2C2 0 2C3(4输入2位多路复用器74x153真值表)4-Inpu

44、t, 2-bit MultiplexerTruth Table for a 74x153 AB1C01C11C21C31Y7417101112132C02C12C22C32G152Y9双4选1Expanding Multiplexers(扩展多路复用器)Expanding Bit (扩展位)How to Realize 8-Input, 16-bit Multiplexer? From 8-Input, 1-bit to 8-Input, 16-bit (由8输入1位8输入16位)Need 16 74x151, Each Chip Process 1-bit (需要1

45、6片74x151，每片处理输入输出中的1位)Expanding Multiplexers(扩展多路复用器)Expanding Bit (扩展位)Select-Inputs Connect to C,B,A of Each Chip (选择端连接到每片的C,B,A)Note: The Fanout Ability of Select field (注意：选择端的扇出能力) （驱动16个负载）ENYYABCD0D7Expanding Multiplexers(扩展多路复用器)Expanding Inputs (扩展数据输入端的数目)How to realize 32-Input, 1-bit Mu

46、ltiplexer (如何实现32输入，1位多路复用器？)Inputs from 8 to 32, Need 4 chips ( 数据输入由832，需4片)How to control Select Inputs - By High bit plus Low bit. ( 如何控制选择输入端？ 分为：高位低位)ENYYABCD0D7Expanding Multiplexers(扩展多路复用器)Expanding Inputs (扩展数据输入端的数目)如何实现32输入，1位多路复用器？High Bits plus Decoder as Select ( 高位译码器进行片选)Low Bits Co

47、nnect to C,B,A of each Chip ( 低位接到每片的C,B,A)Output Using OR Gate ( 4片输出用或门得最终输出)ENYYABCD0D7Dual 4-to-1 Multiplexer to 8-to-1 MultiplexerD0D1D2D3D4D5D6D7A0A1A2YAB1C01C11C21C31Y7417101112132C02C12C22C32G152Y9Use MUX to design combinational circuitWhen enable input is asserted，Canonic sumEN

48、ABCD0D1D2D3D4D5D6D7YY74x151CBAVCCF实现逻辑函数 F = (A,B,C)(0,1,3,7)对比Ex：Use 4-to-1 MUX to realize:解：观察逻辑逻辑函数表达式，每个与项都包含了变量A和C，因此用A、C作数据选择器的选择输入端，变换逻辑函数表达式如下MUXD0D1D2D3A0A1ENY对比：四选一MUX表达式令A1=A，A0=C EN=0，D0=0，D1=D，D2=B， D3=BYZWX00 01 11 10000111101111111YWX00 01 11 100110ZZZZZ0Use 74x151 to realize the func

49、tion:F = (W,X,Y,Z)(0,1,3,7,9,13,14)降维：由4维3维ENABCD0D1D2D3D4D5D6D7YY74x151VCCYXWFZ利用74x151实现F = (W,X,Y,Z)(0,1,3,7,9,13,14)0 2 6 4 1 3 7 5 YWX00 01 11 100110ZZZZZ0说明：用具有n位地址输入端的多路复用器，可以产生任何形式的输入变量数不大于n+1的组合逻辑函数。Use MUX to realize logic function Karnugh maps1、将卡诺图画成与数据选择器相适应的形式。也就是说，所使用的数据选择器有几个地址选择输入端，

50、逻辑函数卡诺图的某一边就应有几个变量，且就将这几个变量作为数据选择器的地址选择码 2、将要实现的逻辑函数填入卡诺图并在卡诺图上画圈。顺着地址选择码的方向画圈 3、求输入数据端的逻辑函数表达式。 4、根据选择端和输入数据端的逻辑函数表达式，画出用数据选择器实现的电路。Ex. Use 4-to-1 MUX 74x153 and 8-to-1 MUX 74x151 to realize the function respectively.F(A,B,C,D)=m(0,1,5,6,7,9,10,13,15)+(4,8,11,12) Solution 1: 4-to-1 MUX 74x153AB0001

51、111000011110011110111011CD D0=C D1=1D2=1 D3=D EN 0 1 2 3 Y1 EN 0 1 2 3 Y2 C_L 1 1 D MUXB A 0 FA1A0Solution 2: 8-to-1 MUX 74x151EN0123Y456711A0MUXDC0B01A_L1FA0A1A2110111101100111011ABCD01000001011010110011Demultiplexer（多路分配器）Route the bus data to one of m destinations (把输入数据送到m个目的地之一)多路复用器SRCASRCBSRC

52、Z多路分配器BUSDSTADSTBDSTZSRCSELDSTSELDST : destinationSRC : sourceSEL : selectA binary decoder with an enable input can be used as a demultiplexer(利用带使能端的二进制译码器作为多路分配器)ABCG1G2AG2BY0Y1Y2Y3Y4Y5Y6Y774x138DST0_LDST7_LEN_LDSTSEL0DSTSEL1DSTSEL2地址选择 Enable input is connected to the data line (利用使能端作为数据输入端)数据输入

53、 SRCEN_LCan you tell the circuit function？6.8 Parity Circuit (奇偶校验电路)Odd-Parity Circuit（奇校验电路）Output is 1 if an odd number of its inputs are 1. (如果输入有奇数个1，则输出为1。)Even-Parity Circuit（偶校验电路）Output is 1 if an even number of its inputs are 1. (如果输入有偶数个1，则输出为1。)回顾：用什么可以判断1的个数？Parity CircuitA0 A1 An = 1 变

54、量为1的个数是奇数0 变量为1的个数是偶数Output of odd-parity circuit is inverted, we get an even-parity circuit.(奇校验电路的输出反相就得到偶校验电路)N XOR gates may be cascaded to form a circuit with n+1 inputs and a single output.(n个异或门级联，形成具有n+1个输入和单一输出的电路) Review of XOR AND XNOR AB=(AB) AB=AB AB=ABAny two signals( inputs or output)

55、 of an XOR or XNOR gate may be complemented without changing the resulting logic function. (Figure 6-69)(对于异或门、同或门的任何2个信号（输入或输出）都可以取反，而不改变结果的逻辑功能)F=ABABFABFABABFFF=ABF=(AB)F=(AB)I1I2I3I4INODDDaisy-Chain Connection (菊花链式连接)I1I2I3I4IMINODDTree Structure (树状连接)Cascading XOR Gates(Figure 6-70）9-bit Odd/

56、Even Parity Generator 74x280 (9位奇偶校验发生器74x280)ABCDEFGHIEVENODD74x280Figure 6-71Parity-Checking Applications用于检测代码在传输和存储过程中是否出现差错AEVENODD74x280HIAEVENODD74x280HI发端收端DB0:7DB0:7ERROR发端保证有偶数个1收端 ODD 有效表示出错奇数EVEN6.9 Comparator （比较器）Compare two Binary words and indicate whether they are equalComparator: C

57、heck if two Binary words are equal ( 等值比较器：检验数值是否相等 )Magnitude Comparator: Compare their magnitude (Greater than, Equal, Less than) (数值比较器：比较数值的大小（,=,B（A=1, B=0）则 AB=1 可作为输出信号 AB3)LT = EQ GT = ( EQ + GT )或 (A3 = B3) (A2 = B2) (A1B1)或 (A3 = B3)(A2 = B2)(A1 = B1) (A0B0)或 (A3 = B3) (A2B2)A3 B3A2 B2A1 B

58、1A0 B0+74x854-Bit Comparator 74x85 ( 4位比较器74x85)A0A1A2A3ALTBINAEQBINAGTBIN级联输入，用于扩展ALTBOUT = (AB高位A高位=B高位 & A低位B低位ABAEQBOUT = (A=B)AEQBINAGTBOUT = (AB) + (A=B)AGTBINSerial Expanding Comparators(比较器的串行扩展)XD11:0YD11:03:07:411:8XY+5VABIABOA0A3B0B374x85ABIABOA0A3B0B374x85ABIABOA0A3B0B374x853片74x85构成12位比较器低位高位P0P1P2P3P4P5P6P78-bit comparator 74x682问题1：怎样表示以下输出？ active-high：P DIFF Q active-high ：P EQ Q active-high ：P GE Q active-high ：P LT Q （P463 图6-81）GELT问题2：能否扩展？注意：没有级联输入端P464 Figure 6-823片74x682构