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1、The industrys fastest timing capture with deep memory in a portable logic analyzer with the best price / performanceBrad FriedenProduct ManagerOscilloscope and Protocol DivisionEmbargo: Sept 3, 2013Agilent ConfidentialIntroducing the 16850 Series Portable Logic Analyzers16850 Series Portable Logic A

2、nalyzersDigital Trends16850 Series - Benefits and CapabilitiesApplications and MeasurementsProduct Structure2Anticipate ChangeAccelerate the TransformationAchieve Competitive Advantage TrendsFPGA/SoCs larger and designs more advancedComms incorporating I/Q vector modulation Systems with larger numbe

3、r of serial and parallel buses interactingFast memory systems with careful timing requirements and protocol driving more debug3Digital Designs Complexity GrowingMobile Computing / CommunicationsEducation/ResearchIndustrial ControlsAerospace Defense4FPGAs used and speed increasingSlower speed embedde

4、d memoryDigital controlsRadar I/Q baseband digital signalsFPGAs used and speed increasingCOTSFPGA speeds increasing - up to 300 MHz internal; I/O at 1 Gbps Digital vector I/Q being usedSoCs / ASICs more complexGovernment researchA/D and D/A developmentFPGAs used and speed increasingLogic Analyzer Ma

5、rket and Key IndustriesPrime Data reports $127.5M logic analyzer business (2012)51980/90ongoingongoing2000spresentPast & Present Trends for General Purpose Logic DebugTechnology in Designs:Test Needs:Started off as processor centricInverse assembler focusComplex, elusive errorsComplex multi-sequence

6、 triggeringBus speeds increased Faster timing analysis, more memory, faster state analysisFPGAs became prevalentProbing evolved to look both “inside” and “outside” FPGAsFast buses requiring differential signalingDifferential probingAnticipate ChangeAccelerate the TransformationAchieve Competitive Ad

7、vantage Visualize and analyze complex digital design functionality to debug issuesLarge number of digital inputs gives access to a whole system view to see interactionsTiming mode gives the multi-bus view and highlights timing and logic issuesIntegration with scopes expands “system” viewHelps reduce

8、 the total test time - so faster to market6What is the Value of a Logic Analyzer Today?“My design wont boot correctly. I cant capture key digital signals over the boot time” - mobile device designer“I cant see multiple buses over a long time period to understand the operation of the whole system to

9、debug a critical issue”“I have a variety of digital buses, some 250 MHz, requiring both single-ended and differential signals and there is a lack of affordable measurement solutions”7It all boils down to time to marketCustomer Challenges16850 Series Portable Logic AnalyzersDigital Trends16850 Series

10、 - Benefits and CapabilitiesApplications and MeasurementsProduct Structure82.5 GHz timing capture with up to 128 M sample memory1.4 GHz trigger sequencer for state and timing captureWide range of single-ended and differential probing optionsFour models starting at $13.7k - offering the best price/pe

11、rformanceIndustrys fastest timing capture with deep memory in a portable logic analyzer - for fast digital system debug16850 Series Portable Logic Analyzer980 ps resolution (12.5 GHz) Timing Zoom with 256 K samples allows you to observe signal timing in proximity to the trigger pointPowerful, custom

12、izable triggering quickly isolates problemsGain signal integrity insight on all channels using exclusive eye scan Industrys fastest timing capture with deep memory in a portable logic analyzer - for fast digital system debugProven, easy to use interface speeds debugStandard 15-inch touch screen allo

13、ws viewing of multiple buses and signalsStandard 3-year warranty10Industrys fastest timing capture with deep memory in a portable logic analyzer - for fast digital system debugFour models with 34/68/102/136 channels provide measurement flexibilityGet to Market Faster 11 Find root cause of failure mo

14、re quickly with high speed timing in deep memory The 16850 Series provides 2.5 GHz timing capture with up to 128 M sample memory. Provide high resolution insight into conditions far from the trigger point.Ensure High Quality Products12Confidently validate a variety of sub-systems through easy-to-use

15、 high-speed trigger sequencer The 16850 Series provides a 1.4 GHz trigger sequencer and related state and timing capture.Track a wide range of system functional operations.Quickly find elusive errors.Example of a timeout trigger to analyze when a state machine fails to repeat a value of 00 within 10

16、 sec.Reduce Cost of Test13Probe differential circuits more affordablyThe 16850 Series provides single-ended and differential probing in a portable logic analyzer.New, affordable single-ended probe solutions reduce the cost of the overall test setup Performance Combined with Ease of Use Accelerates D

17、igital Debug 14Easy definition of bus and signal names, and assignment to input channelsSpecify timing acquisition mode, speed and memory depth15Easily Capture and Analyze Areas of Interest2.5 GHz timing with up to 128 M samples1.4 Gbps state data rateQuickly Set up Simple or Complex Trigger Conditi

18、ons16Set trigger directly from the waveform window or use trigger functions from the advanced trigger menu.16850 Series Portable Logic AnalyzersDigital Trends16850 Series - benefits and capabilitiesApplications and MeasurementsProduct Structure17Applications for the 16850 SeriesFaster FPGAs and ASIC

19、sXilinxAlteraUse FPGA Dynamic ProbeDDR3 1333 addr/ctr memoryDecoderCompliance testPerformance analysisD/A A/D CharacterizationDebugVector I/Q modulatorCapture digital I/QImport to the 89600 VSA18Debug for mid to high performance systemsSee the timing relationship between a state machine sequence and

20、 and the last Ack - far before the logic analyzer trigger point.Gain Deep Debug InsightWith 2.5 GHz, 400 ps resolution timing captureTiming Zoom provides 12.5 GHz, 80 ps sampling around the trigger point (256 K sa) 20START valid to clock rising edge = 2.08 nsState Speed and 1.4 GHz Trigger Sequencer

21、 to Meet Your Needs700 Mbps state data rate standard 1400 Mbps state data rate optional(350 MHz state clock)(700 MHz state clock)700 MHz trigger sequencer1.4 GHz trigger sequencerExample trace - 667 MHz clock, 1333 Mbps state captureQualitative comparison of eye diagrams relative to each otherQuickl

22、y identify abnormalitiesSynchronous-state mode onlyEye Scan Provides Bus-Level Signal Integrity Insight22In yellow23CHALLENGE : Finding the Root Cause of FailureNo matter what application area youre working in, you are most concerned with finding the root cause of failure.Step 1: You need to look fa

23、r back in time with high resolutionTime out flag trigger and with the 16850 Series you can Error: state machine lockedCause of failure not found around triggerStep 2: Get the big picture with deep memory and high speed timing captureAnd find the error of the state machine stoppingSee the error of Ac

24、ks stopping at 500 us before the triggerStep 3Step 3: And now see the interaction of Acks and failing state machineDrag a box around the area of interest and “Zoom In”Step 4: Zoom in even closer to see state machine timing2.5 GHz, 400 ps resolution timing capture in deep memory allows you to sort ou

25、t timing versus functional issuesStep 5: Identify failures as timing or functional issuesAnd when you want to see signals inside your FPGA29Use the FPGA dynamic probe to probe waveforms at various stages of FPGA implementationDigital IF/FPGA-BB Filter0 deg90 degFs/4 LOIQBB Filter I(t) * CosWc(t) Q(t

26、) * SinWc(t)Faster FPGAs and ASICsDigital IF/FPGA-BB Filter0 deg90 degFs/4 LOIQBB Filter I(t) * CosWc(t) Q(t) * SinWc(t)Use the FPGA dynamic probe to probe waveforms at various stages of FPGA implementationAnd when you want to see signals inside your FPGA30Faster FPGAs and ASICsDigital IF/FPGA-BB Fi

27、lter0 deg90 degFs/4 LOIQBB Filter I(t) * CosWc(t) Q(t) * SinWc(t)Use the FPGA dynamic probe to probe waveforms at various stages of FPGA implementationNo stopping the designNo block RAMNo changing design timing as probe points are moved aroundAutomatic FPGA pin mapping (for Xilinx)And when you want

28、to see signals inside your FPGA31Faster FPGAs and ASICsValidate DDR2/3 1333 (667 MHz clock) Memory Systems32Capture and decode DDR3 Addr/Cmd linesValidate DDR2/3 1333 (667 MHz clock) Memory Systems33Performance test analysis of DDR3 Addr/Cmd linesValidate DDR2/3 1333 (667 MHz clock) Memory Systems34

29、Compliance test analysis of DDR3 Addr/Cmd lines16850 Series Portable Logic AnalyzersDigital Trends16850 Series - Benefits and CapabilitiesApplications and MeasurementsProduct Structure3516850 Features/Characteristicsand Base Pricing3616851A16852A16853A16854ABase pricing$13.7k$17.5k$20.9k$24.6kConven

30、tional timing2.5 / 5 GHz (400ps / 200ps) full/half channelup to 128 M sample depth; 1.4 GHz sequencerHigh speed timing12.5 GHz (80ps) 256K deepMax state data rate700 Mb/s (standard); 700 MHz sequencer1400 Mb/s (optional); 1.4 GHz sequencerMemory depth2 M, 4 M, 8 M, 16 M, 32 M, 64 M, 128M(2x memory i

31、n half-ch timing)Signal supportSingle-ended, Differential, BGA, DIMMBus level signal integrity insightEye Scan16800 TLA 640016850Timing with deep memory0.5 / 1.0 GHz (up to 32 M samples)1.6 / 3.2 GHz (up to 64 M samples)2.5 / 5 GHz (up to 128 M samples)High speed timing around trigger point4 GHz (up

32、 to 128 k samples)25 GHz (up to 128 k samples)12.5 GHz (up to 256 k samples)Max state clock rate250 MHz base500 MHz option333 MHz base666 MHz option350 MHz base700 MHz optionMax state data rate250 Mbps base500 Mbps option666 Mbps base1333 Mbps option700 Mbps base1400 Mbps optionMax trigger sequencer

33、Up to 500 MHzUp to 800 MHzUp to 1.4 GHzProbingSingle-endedSingle-endedSingle-ended andDifferentialMemory depth1M to 32M2M to 64M2M to 128MBus level signal integrity insightEye ScaniCaptureEye ScanChannel count34/ 68/ 102/ 136/ 20434 / 68 / 102 / 13634 / 68 / 102 / 136ToolsGlitch trigger, FPGA dynami

34、c probe automationGlitch trigger, flag, S/H violation trigger, flagFPGA dynamic probe automation, memoryPrice$12.1k starting$11.8k starting$13.6k startingCurrent 16800 Series vs. Tek TLA 6400 vs. new 16850 Series* 5X FASTER TIMING than the 16800sProduct Options & Pricing ExampleFeatureBase productOp

35、tionOpt price ($)2.5 / 5 GHz deep timing (1.4 GHz sequencer)700 Mbps state data rate (700 MHz sequencer)1400 Mbps state data rate (1.4 GHz sequencer)$1.9k Differential and 90 pin header probing 2M Memory 4M, 8M, 16M, 32M, 64M, or 128M memory$7.2k to$29.2k 15 in touch screen3816852A (68 Channels) $17

36、.5k baseNew 16850 Series Probes U4203A SE flying lead direct connect 34ch - $2.2kU4204A SE Soft Touch Pro direct connect 34ch - $3.7k (est.)U4205A SE Mictor Direct Connect 34ch - $1.8k39Example Configuration4068 channel with standard 700 Mbps state data rate, 2 M base memory, flying lead probingModelBase specsPrice eachQtyPrice16852A68 ch, 2.5