EDA技术实用教程第四章深入学习VHDL课件

1、第四章 深入学习VHDL() VHDL 与图形化输入比较易于修改功能强大可移植性更强图形化输入 vs VHDL图形化更所见即所得VHDL 则是告诉系统要什麽功能，而编译器给出相应的硬件学习 VHDL 要学习组合逻辑 Combinatorial Logic时序逻辑 Sequential Logic并行语句 Concurrent Statement顺序语句 Process Statement组合逻辑Combinatorial LogicCombinatorial Logic if 输出是由输入决定的逻辑函数如译码器 decoders, 多路开关multiplexers和加法器 adders输出随输

2、入立即变换并行语句Concurrent Statement同时并发执行与书写前后无关并行语句是: 输出仅取决于输入Entity test1 IsPort ( a, b : in bit; c, d : out bit);end test1;architecture test1_body of test1 isbeginc = a and b;d = a or b;end test1_body;Entity test1 IsPort ( a, b : in bit; c, d : out bit);end test1;architecture test1_body of test1 isbegi

3、nd = a or b;c = a and b;end test1_body;并发执行与书写顺序无关输出取决于输入而没有任何条件限制相同C = A and BD = A OR Bc = a and b;d = a or b;d = a or b;c = a and b;Entity test1 isPort ( clk, d1, d2 : in bit; q1, q2 : out bit);end test1;architecture test1_body of test1 isbeginProcess (clk, d1)beginif (clkevent and clk = 1) thenq

4、1 = d1;end if;end process;Process (clk, d2)beginif (clkevent and clk= 1) thenq2 = d2;end if;end process;end test1_body;Entity test1 isPort ( clk, d1, d2 : in bit; q1, q2 : out bit);end test1;architecture test1_body of test1 isbeginProcess (clk, d2)beginif (clkevent and clk = 1) thenq2 = d2;end if;en

5、d process;Process (clk, d1)beginif (clkevent and clk= 1) thenq1 = d1;end if;end process;end test1_body;两个PROCESS并发执行在PROCESS中代码顺序执行在条件限制下输出取决于输入两个PROCESS并发执行How to . ?组合逻辑Combinational Logic能被下面语句实现 并行赋值语句Concurrent Signal Assigment Statements单纯描述组合逻辑的Process 语句，没有任何时钟边延的约束并行语句Concurrent Statements分

6、类(1)信号赋值语句Signal Assigments(2)条件赋值语句 Conditional Signal Assigments(3) 选择赋值语句Selected Signal Assigments(1)信号赋值语句Signal Assigment 并行运行Entity test1 isport ( a, b, e : in bit; c, d : out bit);end test1;architecture test1_body of test1 isbeginc = a and b;d = e;end test1_body;我要 5输入与门Entity test1 isport (

7、 a, b, c, d, e : in bit; f : out bit);end test1;architecture test1_body of test1 isbeginf = a and b and c and d and e;end test1_body;(2) 条件赋值语句Conditional Signal Assigments当条件成立时赋值例如选多路开关 2 to 1 multiplexerEntity test1 isport (in1, in2, sel : in bit; d : out bit);end test1;architecture test1_body of

8、 test1 isbegind = in1 when sel = 0 else in2;end test1_body;要更多 - 4 选1 多路开关Entity test1 isport (in1, in2, in3, in4 : in bit; sel1, sel2 : in bit; d : out bit);end test1;architecture test1_body of test1 isbegind = in1 when sel1 = 0 and sel2 = 0 else in2 when sel1 = 0 and sel2 = 1 else in3 when sel1 =

9、1 and sel2 = 0 else in4;end test1_body;(3) 选择信号赋值Select Signal Assignments输出随相应的选择条件被赋值Entity test1 isport (a, b: in bit; sel : in bit; c : out bit);end test1;architecture test1_body of test1 isbeginwith sel select c = a when 1, b when 0;end test1_body;想要更多If I want more choice -It is easyEntity tes

10、t1 isport (in1, in2, in3, in4 : in bit; sel : in integer; out1 : out bit);end test1;architecture test1_body of test1 isbeginwith sel select out1 = in1 when 0, in2 when 1, in3 when 2, in4 when 3;end test1_body;练习将图形转化为 VHDL示例Entity test1 isport (high, medium, low : in bit; highest_level3, highest_lev

11、el2 : out bit; highest_level1, highest_level0 : out bit);end test1;architecture test1_body of test1 isbeginhighest_level3 = 1 when high=1 and medium=0 and low=0 else 0;highest_level2 = 1 when high=0 and medium=1 and low=0 else 0;highest_level1 = 1 when high=0 and medium=0 and low=1 else 0; highest_l

12、evel0 = 0 when high=1 and medium=0 and low=0 else 0 when high=0 and medium=1 and low=0 else 0 when high=0 and medium=0 and low=1 else 1;end test1_body;仿真进程语句Process Statement规则Process中语句顺序执行所有 Process 必须有敏感信号表 SENITIVITY LIST一旦敏感信号变了，触发Process运行除非有Wait语句模板 Process Statement用敏感信号表 “SENSITIVITY LIST”n

13、ame : PROCESS (sensitivity_list)begin sequential statement #1 sequential statement #2 . sequential statement # NEND PROCESS name; 通用写法Process ( )begin.end process敏感信号表顺序执行语句名称可选举例Entity test1 isport (a, b, sel1, sel2 : in bit; result : out bit);end test1;architecture test1_body of test1 isbeginproce

14、ss (sel1, sel2,a, b)beginif (sel1 = 1) thenresult = a;elsif (sel2 = 1) thenresult = b;elseresult = 0;end if;end process;end test1_body;输出随 sel1, sel2, a 或 b 变化而变化等一下: 我可以用并行语句完成Entity test1 isport (a, b, sel1, sel2 : in bit; result : out bit);end test1;architecture test1_body of test1 isbeginresult

15、= a when sel1 = 1 else b when sel2 = 1 else 0;end test1_body;Entity test1 isport (a, b, sel1, sel2 : in bit; result : out bit);end test1;architecture test1_body of test1 isbeginprocess (sel1, sel2,a, b)beginif (sel1 = 1) thenresult = a;elsif (sel2 = 1) thenresult = b;elseresult = 0;end if;end proces

16、s;end test1_body;同样功能，不同实现方式Concurrent StatementProcess StatementQ : 两者区别 Concurrent and Process Statement？A : 对简单例子, Concurrent and Process 都可. 但一些复杂例子只有用Process Statement。How to . ?时序逻辑Sequential Logic可以这样实现：Process Statement 描述逻辑 ，附加时钟限制用Process 设计时序逻辑怎样做锁存器 LatchEntity test1 isport (clk, d , res

17、et : in bit; q : out bit);end test1;architecture test1_body of test1 isbeginprocess (clk, d, reset)begin if (reset = 1) then q = 0; elsif (clk = 1) then q = d; end if;end process;end test1_body;Reset 先取得控制权Clk后取得控制权在 process中语句顺序执行这是 LATCH如果我如下修改.Entity test1 isport (clk, d , reset : in bit; q : out

18、 bit);end test1;architecture test1_body of test1 isbeginprocess (clk)begin if (reset = 1) then q = 0; elsif (clk = 1) then q = d; end if;end process;end test1_body;注意 : 结果完全不同这是什麽？这是触发器 Flip-Flop 不是锁存器 LATCH为什麽我得到Flip-Flop 而不是 Latch锁存器的Sensitivity listprocess (clk, d, reset)触发器的 Sensitivity listproc

19、ess(clk)Q : Sensitivity list 用来干什麽 ?A : 输出随 Sensitivity list 变我们现在知道 VHDL 是强大的, 但如果你不知道自己作什麽, 你不会得到想要的结果你想要 latch 但事实上你得到了 Flip-Flopsequential statements 的顺序有何影响 ?ex1: PROCESS (a, b)BEGIN IF a=1 THEN c=0; - 若 a 、 b 都为 END IF; IF b=1 THEN c=1; - b 优先 END IF;- 故c = 1;END PROCESS ex1;ex2: PROCESS (a, b

20、)BEGIN IF b=1 THEN c=1; -若 a 、 b 都为 END IF; - IF a=1 THEN c=0; - a优先 END IF; -故c = 1;END PROCESS ex2;Processes中信号赋值的注意事项看下列的代码，那种电路是综合的结果？PROCESS (clock)BEGINIF rising_edge(clock) THENb = a; - 在 clock 上升延后, a 赋给 bc = b; -在 clock 上升延后, b赋给 c END IF;END PROCESS ;aclockcbacclock ORSignal Assignment in

21、Processes在进程中，信号不是被立即更新，而是在预定的时间被更新信号事实上直到执行到END PROCESS才被更新所以，前面综合出两个寄存器 (c = b 中的是原来的状态 b)在某些时候，外面用并行语句会解决此问题，但不是总有效。如何解决 ?Variables当并行信号赋值不能在process 外使用时, 可用 variable解决问题Variables 和 signals类似, 但只用在 PROCESS中. 不能在 processes间传输信息Variables 可以是VHDL中任何数据类型赋给 variable 的值立即生效用分号结束赋值 (:), 如下:c := a AND b;

22、cVariables vs. Signals用 variable 解决前面的问题:PROCESS (clock)VARIABLE b : std_logic ;BEGIN IF rising_edge(clock) THEN b := a ; - 立即赋值生效c = b ; - 按预定时间赋值生效 END IF;END PROCESS ;aclock另外一种编码LIBRARY IEEE;USE IEEE.std_logic_1164.all;ENTITY tdff ISPORT(clk, d: in std_logic; q : out std_logic);END tdff;ARCHITEC

23、TURE behaviour OF tdff ISBEGINPROCESSBEGINwait until clk = 1;q = d;END PROCESS;END behaviour;IF-THEN-ELSE vs WATI UNTILLIBRARY IEEE;USE IEEE.std_logic_1164.all;ENTITY tdff ISPORT(clk, d: in std_logic; q : out std_logic);END tdff;architecture behaviour OF tdff ISBEGINPROCESSBEGINwait until clk = 1;q

24、= d;END PROCESS;END behaviour;Entity test1 isport (clk, d : in bit; q : out bit);end test1;architecture test1_body of test1 isbeginprocess (clk)begin if (clk = 1) then q = d; end if;end process;end test1_body;Entity test1 isport (clk, d : in bit; q : out bit);end test1;architecture test1_body of tes

25、t1 isbeginprocess (clk,d)begin if (clk = 1 and clkevent) then q = d; end if;end process;end test1_body;They are all the sameDFFReviewConcurrent Statement 用来设计组合逻辑combinational logic (无触发器)如译码器 decoders, 多路开关multiplexers和加法器 addersProcess Statement 用来设计组合逻辑combinational logic (无触发器)时序逻辑Sequential log

26、ic (触发器)如状态机. State Machine，计数器 Counters, 移位寄存器Shift Register， 控制器ControllersCombinational CircuitSequential CircuitProcess StatementConcurrent StatementENTITY test1 ISPORT( clk, a,b,c : in bit; d: out bit);END test1;architecture test1_body of test1 isbegind = (a and b) xor c);end test1_body;Is this

27、 OK ?Combinational CircuitENTITY test1 ISPORT( clk, a,b,c : in bit; d, e : out bit);END test1;architecture test1_body of test1 isbegind = (a and b) xor c);e = (a or b) nand c);Is this OK ?Concurrent Statement for Combinational Circuitend test1_body;ENTITY test1 ISPORT( clk, a,b,c : in bit; d : out b

28、it);END test1;architecture test1_body of test1 isbeginprocess(a,b,c)begind = (a and b) xor c);end process;end test1_body;Is this OK ?Process Statement for Combinational CircuitENTITY test1 ISPORT( clk, a,b,c : in bit; d,e : out bit);END test1;architecture test1_body of test1 isbeginprocess(a,b,c)beg

29、ind = (a and b) xor c);e = (a or b) nand c);end process;end test1_body;Is this OK ?Process Statement for Combinational CircuitENTITY test1 ISPORT( clk, a,b,c : in bit; d, e : out bit);END test1;architecture test1_body of test1 isbeginif (clkevent and clk=1) thend = (a or b) and c);end test1_body;Is

30、this OK ?No ! Sequential Statement must be within Process StatementENTITY test1 ISPORT( clk, a,b,c : in bit; d : out bit);END test1;architecture test1_body of test1 isbeginprocess(clk)beginif (clkevent and clk=1) thend = (a or b) and c);end if;end process;end test1_body;Is this OK ?Process Statement for Sequential CircuitENTITY test1 ISPORT( clk, a,b,c : in bit; d,e : out bit);END test1;architecture test1_body of test1 isbeginprocess(clk,a,b,c)beginif