参考-纳米时代集成电路

Integrated

Circuits

Golden

Moore

&

VonannNano-Electronics

EraGenerality

is

KingIntegrated

Circuits

and

ICTOutlines2A

Game

of

Calculation?230.67

=

1?,708,401,590What

does

this

number

mean?Why

do

we

need

to

know

this

number?If

we

say

that

some

industry

grows

with

a

year

to

year

rate

of

2n,

n=year,

is

this

true?The

number

of

transistors

on

a

singlesilicon

chip

doubled

every

18

months.

Ifonly

1

transistor

existed

on

a

chip

in

1965,today

a

single

chip

may

contain

more

than1.7

billion

transistors,

as

(20111965)

×12

÷

18

=30.67.We

are

certainly

shocked

by

this

amazing

law.We

are

curiously

to

know

why

the

law

has

been

valid

for

so

longtime.We

are

also

eagerly

to

know

if

and

how

long

this

law

will

last

inthe

future.3Binary

and

Digital

SystemDecimal<->Binary0<->00001<->00012<->00103<->00114<->01005<->01016<->01107<->01118<->10009<->1001Elements

of

decimal

and

binary

systemDecimal

System:

0,

1,

2,

3,

4,

5,

6,

7,

8,

9Binary

System:

0,

1Real

world

isogA

component

dealing

withdecimal

has

very

high

cost数模字拟世世界界是是虚真拟实的的4Amplifier

and

Binary

CodeAmplifier开到最大：“1”完全关闭：“0”注：假设水流时恒定的大坝大坝电劢机发电机5Vacuum

Tube飞乐266-TH型6电子管3波段收音机阳极6栅极阴极通电后阴极向阳极发射电子阳极收集电子通过在栅极施加一个电位可以控制仍阴极到阳极通过的电子量要想使阴极能够发射电子就要将阴极加热到数百摄氏度高温阴极丌发射电子时为“0”阴极发射的电子全部被阳极接收时为“1”ENIAC：

1sectronics

Computer7TransistorW.

Shockley,

J.Bardeen

and

W.

Brattain1947年，第一支晶体管在贝尔实验室诞生，巴丁、肖兊利和布莱坦获得1956年物理学奖8Principle

of

Semiconductor

Transistor栅G源S漏D多晶硅金属层金属氧化物半导体晶体管（MOS晶体管）结构图GSD+

+

+

+

+

+

+

+氧化层

扩散区硅衬底9Integrated

Circuits1958年，J.

Kilby发明了集成电路的理论模型1959年，R.Noyce发明了今天的集成电路PentiumIIIPentiumIV2000年，J.

Kilby获得物理学奖10Evolution

of

Computer11Integrated

Circuits

Exist

Everywhere12Integrated

Circuits

Golden

Moore

&

VonannNano-Electronics

EraGenerality

is

KingIntegrated

Circuits

and

ICTOutlines13IntroductionMoore

&

VonannVonannGolden

MooreScaling-downVon

annArchitectureSemiconductorComputer14Golden

Moore15With

unit

cost

falling

as

thenumber

of

components

percircuit

rise,

by

1975economics

may

dictatesqueezing

as

many

as65,000

components

on

asingle

silicon

chip.Moore’s

Law16Robert

Dennard

and

Dennard’s

Law17Scaling-down等比例缩小的技术代等比例缩小技术是年复一年地将一组(通常多于20个)支配硅器件的技术参数同步缩小摩尔定律讲的是技术密度倍增的趋势迪纳德定律讲的是实现密度倍增的方法两者统称为“摩尔定律”等比列缩小是实现摩尔定律的方法18GateWiringn+sourcen+drainL/tox/W/xd/Voltage

V/P

substrate,

do*NASCALING:Voltage:Oxide:Wire

width:Gate

width:Diffusion:Substrate:V/

tox/

W/

L/

xd/*NARESULT:Higher

density:

~2Higher

speed:

~

Power/ckt:

~1/2Power

Density:

~ConstantPower

Density

=

Constant?190.111010010000.011Classic

Scalingtox(A)Vdd(V)0.1Ga ength

Lgate(m)DramaticallyIncreasing

ofPower

DensityPower

Density

≠

ConstantReasons

of

the

shiftUnacceptable

leakagecurrentHigher

voltage

implieshigher

performanceResult

of

the

shift2010110210310410510610710070

75

80

85

90

95

00

05

10

15

20

25UnscaledPower

Density1%DeviationAir

CoolingLimit“Perfect”

PowerDensity

ScalingLogic

Power

Density

(Watts/cm2)Why

Power

Density

Is

Important21Power

Consumption

is

key2224681012900010Module

Heat

Flux

(Watts/cm2)IBM360IBM370

IBM3033IBM4381IBM3081Fujisu

M380IBM3090CDC

Cyber

205Fujisu

M780NTTIBM3090SFujisu

VP2000IBMS9000BipolarCMOSApacheMercedPentium

IIIBM

RY4PulsarIBM

RY6IBM

RY7PentiumIVIBMRY5IBMGP?电熨斗的功率密度:5W/cm2Materials

and

Device23Signal

Integrity频率越高，波长越短。当天线的尺寸不波长处在同一量级的时候，天线将辐射和接受电磁波。今天的集成电路运行在GHz，信号完整性是个严峻的。24ENIAC:

Application

Specific

ComputerENIAC是一台与为 军方计算火

弹道轨迹设计的与用计算机。虽然具备一定的编程能力，但程序是事先预置好的。改变程序就要求改变硬件的连线结构。严格意义上讲，ENIAC丌是一台通用计算机。ENIAC运行时，安排了一批年轻的女性

按照计算要求插拔众多的接头，以实现丌同的运算。工作十分繁琐，出错概率很大，效率很低。硬件的准备时间大大超过实际的计算所需的时间。25The

Von ann

architecture

is

a

designmodel

for

a

stored-program

digital

computerthat

uses

a

central

processingunit

(CPU)

and

asingle

separate

storage

structure

(memory)

tohold

both

instructions

and

data.of

the

Von

ann’sCharacteristicsarchitecture:a)

memory;control

unit;arithmetic

logic

unit;input

/

output

interface.The

disadvantage

of

Von

annarchitecture:

shared

memory

for

instructionsand

data

with

one

data

bus

and

one

addressbus

between

processor

and

memory.Instructions

and

data

have

to

be

fetched

insequential

order

(known

as

the

Vonann

Bottleneck),

limiting

the

operationbandwidth.Von ann

Architecture26Instruction

=

Low

Efficiency取指运算结果指令地址有效读使能数据有效写入指令寄存器数据地址有效读使能取操作数二数据有效写入寄存器指令译码数据地址有效读使能取操作数一数据有效写入累加寄存器数据地址有效写使能数据有效写入

器完成一个运算需要大量的准备工作想加快运算速度要就加快所有环节涉及大量对外部

器的操作信号传辒需要涉及全局性的互连“性能墙”“

墙”“功耗墙”2+3=527Various

ArchitectureHarvardVLIWMulti-CoresMany-CoresDual-CoresMulti-threadsOut-of-orderExecutionMulti-IssuesPipeline2860年前，硬件很贵复用资源是必须的Hardware

=

Expensive29Integrated

Circuits

Golden

Moore

&

VonannNano-Electronics

EraGenerality

is

KingIntegrated

Circuits

and

ICTOutlines30Performance,

Cost

and

Power提升性能是永恒的保证性能的前提下降低成本保证性能的前提下降低功耗保证性能和成本的前提下降低功耗保证性能和功耗的前提下降低成本导提致升功性耗能上必升然致增提成加升本资性上源能升，要导求致减降性少低能资成下源本降，要导求要降求低降成低本性通能常31Economy:

Heavy

InvestmentHuge

Investment

Stops

Investor16nm～12-15B

$22nm～8-10B

$32nm～5-7B

$45nm～3.5-5B$65nm～2.5-3B

$32Cost

Per

Transistor

Reduction(US

Dollar)Source：Industry

Restructuring,

IBS

Report,

2007Scaling-down

≠

Cost-down130nm2,45090nm2,81065nm3,

106降45nm4,024，32nm4,817要22nm6,63822nm之后，成本下已经不是主要任务而提升性能成为主目标。Economy:

Cost

Reduction33Source：Industry

Restructuring,

IBS

Report,

2007Lower

UtilizationEconomy:

R&D

Expense3435Only

a

few

high-end

chip

makers

todaycan

even

afford

the

exorbitant

cost

ofNEXT-GENERATION

RESEARCH

AND

DESIGN,

muchless

the

fabs

to

build

them.

将来

数高端设计公司可以负担昂贵的研发费用，而更少的公司有能力制造新一代的产品。R.

Colin

Johnson,“IBM

Fellow:

Moore’s

Law

Defunct,”

EE

Times,

4/07/09Integrated

Circuit:

Game

of

Ri

anWally

Rhines,

Chairman

&

CEO,

Mentraphics,

August

2010Scaling-down

&

Vonn

ISAPerformance,

Cost

and

Power16nm22nm32nm45nm65nm12nm90nm130nmScaling-down

&

Vonann

ArchitecturePer

ChipScaling-down

&

Vonann

Architecture

&

PowerPer

Chip通用准则：高性能、低功耗、低成本36More

Moore

and

More

Than

MooreSource：2007

ITRS37Physical

Limits:ParameterITRS

22nm

node

(2016)Physical

LimitMinimum

dimension9

nanometers1.5

nanometersFastest

switching

time150

femto-seconds40

femto-secondsPower

dissipation

limits:

“Device-at-the-physical-limit”

will

dissipateseveral

thousand

Watts/square-cmTechnological

Limits:

Pushing

CMOS

to

its

ultimaimits

requiresrevolutionary

materials

and

deviceinnovations

that

havesignificantscientific

and

engineering

barriersEconomic

Limits:

Implementing

all

the

technology

innovations

mayraise

manufacturing

and

development

costs

to

being

beyond

thereach

of

all

but

a

few

global

entities.Source:

G.

Scalise,

WSC2007Limits

of

CMOS

Technology38ASICSingle-ProcessorSoCDual-ProcessorSoCSoC

EraMPSoC

EraIPLogic1IPLogic1IPLogic1µPMemµPMemµPMemµPMemµPMemµPMemMemMemMemµPMemoryIP

Logic1IP

Logic2IP

Logic3IP

Logic4DSPµPMemoryIPLogic1IPLogic2IPLogic3IPLogic4IPLogicASIPASIPASIPIPLogic1MemMemMemDSPDSPDSP

ASIC

Era

198519952005Multiple-ProcessorSoC来源：

，CIC’2008

苏州System

on

Programmable

Chip39Shared

MemorycacheprivateprivateprivateprivateMEMPeripheryChip

BussoftwarehardwareApplicationArchitecturePEDriversOperating

SystemRTOS-APIApplicationsArchitecture

DesigntimertimerBusCtrlI/O

INTCORE40全球大约有超出20万名患者植入人工耳蜗，长时间持续供电是使用中遇到的最大问题。随着3G服务的普及，规频逐渐成为时尚一族的新宠，功耗成为最受关心的问题之一。Low

Power

Technology41头盔安装显示器携带式电池组手指触摸操作装置平板显示器/键盘Extreme

Low

Power

Design42器市场觃模约占IC总市场的22％，其中以DRAM和Flash为代表的容性

技术是当前应用的主流

技术。面向高性能计算的DRAM2010年发展到44nm/4Gb采用ZrO2-HfO2

MIM叠层电容单元面积6F22016年将发展到22nm/4F2面向高密度数据

的Flash2010年发展到32nm/32Gb采用2-3值浮栅

技术单元面积4F2/1.3F2(每位）2016年将发展到

18nm/4bMLCDRAMNAND-FlashSemiconductor

Memory43Top

ElectrodeAmorphousContactPCMaterialHeaterGSTFeRAM铁电材料极性翻转导致电容变化非电荷型容性器采用2T2C/1T1C结构单元尺寸22-16

F2优点:低压、耐疲劳缺点:单元尺寸大、破坏性MRAM

磁性材料自旋极化翻转导致巨磁电阻或磁隧穿结电流变化阻性

器采用1T1R/1D1R结构单元尺寸45-20

F2优点:低压、耐疲劳缺点:尺寸、电流大PCRAM/RRAM热（电压）作用下材料结晶相（导电）变化阻性

器采用1T1R/1D1R结构单元尺寸4-5

F2优点:低压、多值操作缺点:尺寸缩小后材料可靠性及耐疲劳性差New

Memory

Technology44Memory

TechnologyFilament机制的实验证明:TEM

观察到了TiO2

薄膜中Ti4O7Filament的“连通”不“断裂”D.K.Kwon,

Nature

Nanotech,

5,

148,

201045RRAM在速度、功耗、低压操作等方面均优于PCM，其擦写次数也达到了109（Flash是106）,目前制约其

产品化的问题是集成觃模。仍结构和热耗散的角度看，RRAM是最适于Scaling-down的一种结构。目前制约其集成度提高的主要是TMO变阻单元的

“重复性”和“一致性”问题。RRAM的结构50nm线宽的TiO2

Memristor（HP公司）Challenges

ofMemory46Comparison

of

Different

Memories技术DRAMFG-NORFG-NANDCTMFeRAMMRAMSTT-MRAMPRAMRRAM技术节点(nm)44-1845-2532-2225-10180-130130-6565-3245-18NA非挥发性NoYesYesYesYesYesYesYesYes单元尺寸(F2)6-49-115-4/1.34/1.022-164520-105-45/1.2位数122-42-411122-4读速度(ns)~1010-30~50~50<20<20<20<50<20写/擦速度(ns)~10104-103106-105105-10410-2010-2010-2050-120<100耐疲劳次数>1016105106-104106-104109-1015>3×1016>1012106-109NA功耗LowHighMedMedLowHighMedMedLow可缩小性MedNoMedYesNNMedYesYes1

主要参考ITRS-2009及近年来一些相关研究

；部分数据为理论值或

值，而非实际

的数据；主要针对独立式器进行对比，上表未包括各种及特殊应用；47电荷操作容性器的物理极限及统计学限制电容随工艺缩小丌断变小，

电荷下降，可靠性变差电容间耦合效应急剧加剧，导致操作可控性下降器件漏电增加，信号完整性下降操作电压受各种

介质及绝缘介质厚度限制难以降低22-16nm

DRAM技术4F2单元结构技术及低功耗设计技术高介电材料及MIM电容技术及低漏电

晶体管技术工艺制造技术：光刻、金属栅、良率控制等目前无可替代技术：STT-MRAM可缩小性尚达丌到要求22-16nm

NAND-Flash技术25nm以下（2012年）将必须改用电荷俘获

技术（预计可到10-16nm）耐疲劳次数将下降到10K以下，要求研发12-32位纠错技术可替代技术：4b-CTM+3DNOR-Flash在32-25nm将可能被CTM、PCRAM及RRAM等新型技术取代Challenges

of

Memory

Technology48Integrated

Circuits

Golden

Moore

&

VonannNano-Electronics

EraGenerality

is

KingIntegrated

Circuits

and

ICTOutlines49General

Purpose

Integrated

Circuits50From

Single-core

to

Multi-coreSingle

core

processorPerformance

–

Clock

rate51Dual-core

processorPerformance

–

ResourcesFrom

Multi-core

to

Many-coreMulti-core

processorPerformance

–

Multi-task52Many-core

processorPerformance

–

ParallelizationHomogeneous

and

HeterogeneousSeungjin

Lee,

etc."A

345mWHeterogeneousMany-CoreProcessor

withanIn

ligentInference

Enginefor

Robust

ObjectRecognition",

ISSCC2010,

February

10,2010,

pp.

332-333Jinuk

Luke

Shin,

etc."A

40nm

16-Core128-Thread

CMTSPARC

SoCProcessor",

ISSCC2010,

February

8,2010,

pp.98-9953GranularityD.

Rossi,etc.

"A

Heterogeneous

Digital

Signal

Processor

Implementation

forDynamicallyReconfigurable

Computing",

CICC

2009,

pp.641

-

64432-bit54Inter-ConnectionsBus-connectCross-barNoCSegmentedhierarchical1-D2-D(mesh)55FPGA:

From

Simple

to

ComplexLogic: Field

Programmable

Gate

ArrayI/O

BlocksCLBsPIsDRAMDSPCPUBuffers…56I/O

BlocksCLBsPIsFPGA:

From

Logic

to

ProcessingLogic: Field

Programmable

Gate

ArrayProgrammable

LogicLogic

FunctionProgrammableFunctional

BlocksSignal

ProcessingComputing57Logic: Field

Programmable

Gate

ArrayHomogeneous

and

HeterogeneousCombination

of

differentFunctional

blocks58Combination

of

sameFunctional

blocksMany-Cores

vs.

FPGAConvergence: A

General

Trend?Many-core

Processor59High

PerformanceComplex

FPGA?Dynamic

Reconfigurable,Reprogrammable,Computing/Logic

ArrayDemand

to

RCPPerformance,

Cost,

Power

and

Flexibility名称性能成本功耗灵活性ASIC极高低小差FPGA高较高较大较好CPU中高大极好RCP极高较低较小好ASIC:

Application

Specific

Integrated

CircuitFPGA:

Field

Programmable

Gate

ArrayCPU:

Central

Processing

UnitRCP:

Re-Configurable

Processor计算性能单位面积性能（MOPS/mm2）能耗效率（nJ/Operation）灵活性RISC一般<100~1极好DSP一般<100~1极好RISC多核高<100~1好DSP多核高<100~1好ASIC极高>1000~0.01差RCP极高~1000~0.03好6061Computation/Control

IntensiveReconfigurable

Computing:

DatapathIF

(condition

=

1)THENr1

=b

*b;r2=

a

*

c;r2

=r2

*4;r1

=r1

-

r2;IF

(r1

<

0)

THENstate

=

‘1’;ELSEstate

=

‘0’;

r3=

r1*

4;r3=

r3+

1;r3=

r3*

0.2;FOR

i

=

1

to

3LOOPr4

=

r1

/

r3;r3

=

r3

+

r4;r3

=r3

/

2;END

LOOP;r1

=

0

-

b;r2

=

a

+

a;r4=

r1+

r3;x1

=r4

/

r2;r5=

r1-

r3;x2

=

r5

/

r2;END

IF;END

IF;IF

(condition

=

1)THENCOMPUTATION

1;IF

(r1

<

0)

THENCOMPUTATION

2;ELSECOMPUTATION

3;FOR

i

=

1

to

3LOOPCOMPUTATION

4;ENDLOOP;COMPUTATION

5;END

IF;END

IF;COMPUTATION

1r1

=

b

*

b;r2

=

a

*

c;r2

=

r2

*

4;r1

=

r1

-

r2;COMPUTATION

2state

=

‘1’;COMPUTATION

3state

=

‘0’;

r3

=

r1

*

4;r3

=

r3

+

1;r3

=

r3

*

0.2;COMPUTATION

4r4

=

r1

/

r3;r3

=

r3

+

r4;r3

=

r3

/2;COMPUTATION

5

r1

=

0

-

b;r2

=

a

+

a;r4

=

r1

+

r3;x1

=

r4/r2;r5

=

r1

-

r3;x2

=

r5/r2;ComputationControlVon

annArchitectureArchitecture

Evolution62Universal

ArchitectureVon

annArchitectureInputOutputClockControlVectorsTest

DataDatapathMemoryControllerMemoryControl

Codes

ProgramThis

universal

architectureleads

to

different

structuresfor

ASIC

and

general

purposeprocessor.63ASP:

Datapath

and

ControllerDatapath

consists

in

resources,memories

and

interconnectionsDatapath

performs

functionalcalculation

according

toinputs.Datapath

operates

according

tocontrol-vectors

from

controller.Datapath

is

not

directly

controlledby

system

clock.Datapath

provides

necessary

test-data

tocontroller.Controller

consists

in

state

generatorand

control-vect

enerator.Controller

generates

control-vectorsaccording

to

test-data

and

data-flow.Controller

operates

according

tosystem

clock.ASP:

Application

SpecificProcessor

→

AISCAny

digital

system

can

becomposed

of

Datapath

andControllerASIC

Design:

High-Level

SynthesisInputOutputClockControlVectorsTest

DataDatapathMemoryControllerMemoryControl

Codes64ASIC

Design:

High-Level

SynthesisHardware:

High-Level

SynthesisHardwareDescriptionsOperation

SchedulingRegister

OptimizationResource

AllocationInterconnection

GenerationControl-Codes

GenerationState

GenerationFSM

DesignApplication

specified

architectureScheduling/allocation

during

designDepends

on

hardware

descriptionComponents

do

not

fully

connectedControl-Codes

cannot

be

changedState-Machine

is

not

programmed65InputOutputClockControlVectorsTest

DataDatapathMemoryControllerMemoryControl

Codes

ProgramGPP:

Datapath

and

ControllerGPP:

General

PurposeProcessor

→

MPUAny

processor

c

so

becomposed

of

Datapath

andControllerVon

annArchitectureDatapath

consists

in

resources,memories

and

interconnectionsDatapath

performs

functionalcalculation

according

toinputs.Datapath

operates

according

tocontrol-vectors

from

controller.Datapath

is

not

directly

controlledby

system

clock.Datapath

provides

necessary

test-data

tocontroller.Controller

consists

in

state

generatorand

control-vect

enerator.Controller

generates

control-vectorsaccording

to

test-data

and

program.Controller

operates

according

tosystem

clock.66General

Purpose

Processor

DesignSoftware:

High-Level

SynthesisApplicationProgramOperation

SchedulingRegister

OptimizationResource

AllocationInterconnection

GenerationControl-Codes

GenerationState

GenerationState

Machine

ProgrammingGeneral

purpose

architectureScheduling/allocation

during

compileinterconnection,

control-codes

andstate

are

generated

during

compileComponents

are

fully

connectedControl-Codes

can

be

changedState-Machineis

programmable67Datapath:

Uniform

ArchitectureReconfigurable

Computing+zx

yOperation

Operatorz=

x

+yVariableVariableVariableRegisterRegisterRegisterALU68RTL

StructureInput

BusOutput

BusALURegistersRegistersInput

BusOutput

BusRegistersALURegisters691-Dimension

Data-pathRegisterRegisterRegisterRegisterRegisterRegisterRegisterRegisterRegisterRegisterRegisterRegisterRegisterRegisterRegisterRegisterRTL

Architecture1-Dimension

Expansionx70Two-dimension

Expansion2-Dimension

Data-pathxy713-Dimension

Data-pathThree-dimension

Expansionxyz72Task-Flow

Map12367124567e

=

a

+

b;f

=

c

*

d;h

=

e

–

f;h

=

e

+

f;i=e

/

f;o1

=

g

*

h;o2

=

h

–

I;ab

cdefg4h5i3

73Memories

Map123671234567ab

cdefg4habcdef5ighie

=

a

+

b;f

=

c

*

d;h

=

e

–

f;h

=

e

+

f;i=e

/

f;o1

=g

*

h;o2

=

h

–

I;74Connections

ConfigurationInterconnections

among

operation

1,

operation

2and

operations

3,

operation

4,

operation

5

areconfigured

according

to

the

data

dependency.75abcdefghi1234567Power-GatingProcessors,

memories

andinterconnectionsthatarenot

used

will

bepowergated

in

order

to

decreasepower

consumption.7677ALU:

Multi-Function

UnitX-BusY-BusINPUTBUFFEROUTPUTBUFFERIN

InterfaceOUT

InterfaceContextStatusControllerContext

InterfaceIRQsController:

Programmable-FSMIF

(condition

=

1)

THENCOMPUTATION

1;IF

(r1

<

0)

THENCOMPUTATION

2;ELSECOMPUTATION3;FOR

i=1

to

3LOOPCOMPUTATION

4;ENDLOOP;COMPUTATION

5;END

IF;END

IF;43152i

≤3r1

≥0Computation

1Computation

2Computation

3Computation

4Computation

5i

>3r1

<0FSM:

Finite

State

MachineProgrammable78RISC

BasedProgrammable-FSMRB-PFSM:

1.

Read

current

state

from

State-MemoryDecide

next

state

and

generate

address

according

totest

data,

that

address

theData-Memory

andConfiguring-ContextOutput

the

data

and

configuring-contextRISCMemoryCompilerDatapathCompilerRISCState-MemoryData-MemoryConfiguring-ContextDatapathTest-DataTest-Data79Control-Flow

&

Configuring

ContextRegisterALURegisterRISCState

ControlState/Address

MemoryTest

DataGlobal

DataRegisterEn/DisableALU

Config.Connection

Config.Controller

DatapathGlobal-Data

MemoryConfiguring-ContextRegisterEnable/DisableALU-ContextConnection-ContextPower-ContextPower

Config.80Power

Consumption

ReductionOnly

one

row

works

each

timewhen

datapath

performscalculation.

Thus,

the

powerconsumption

of

datapath

isgreatly

reduced.81Multi-Task

Pipeline

ExecutionTask

1Task

2Task

3Task

4Tasks

areindependentNumber

oftasks

is

limitedby

the

size

ofdatapath82Basic

RequirementReconfigurable

ComputingNo

InstructionC

Language

ProgrammingDynamic

ReconfigurableLocalizing

CommunicationsLocalizing

MemoriesScalable

&

ExtendableNo

IPRIssuesExistingSoftwarePortingReducingMemoryWallImprovingFlexibilityHardwareFlexibilityReducingGlobalWires83Programming

LanguageHigh-Level

Programming

Language(Such

as:

ANSI

C)Int

main(void)func(…,

…){{…………func(…,

…)}……dct(…,

,,,)dct(…,…)……{…………}}ChallengesAvailable

softwareC

languagePointersLoopsRecursive

callVectormatrix….CompilerSyntax

CheckCode

ProfilingCode

TransformationCode

OptimizationData-Flow

GenerationTask

PartitioningTask

SchedulingAllocationConnection

SchemeMap

sEvaluationsContext

Generation84Dimension

Limited:

Task

MapTask

Partitioning

Task

Flow

GenerationTask

DependencyTask

SchedulingDatapath

AllocationMap

Scheme8586Partitioning

and

Deadlocka1a3a4a5a2inp

sv2sv13sv26sv33

sv39m6m7c1c2a8a9a12a11a15m13c3

a10m14c4a16a19a25a27inp

m21a18c5a22sv38m24a29c7a28sv18sv2_o

sv13_o

sv18_oa17a20m31a34a32c6a23sv18a26c8m30sv38a33sv26_o

sv33_o

sv38_o

sv39_o

out_psv39Task

Graph

Partitioning

(No

Deadlock)a1a3a4a5a2inp

sv2sv13sv26sv33

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sv13_o

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sv38_o

sv39_o

out_psv39Task

Graph

Partitioning

(Deadlock)RequirementsLess

interconnections(communication

cost)

between

sub-parts;Avoid

deadlock.Task

Graph

PartitioningGlobal

Datsinga1a3a4a5a2inp

sv2sv13sv26sv33sv39m6m7c1c2a8a9a12a11a15m13c3

a10m14c4a16a19a25a27inp

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out_psv39lobal

Data

MemoryCacheCacheGlobalDataMemoryCache87Operating

SystemMulti-Task

managementResource

managementTime

sharing

and

resource

sharingMulti-ControllerDynamic

Resource

allocationQueue-up88Integrated

Circuits

Golden

Moore

&

VonannNano-Electronics

EraGenerality

is

KingIntegrated

Circuits

and

ICTOutlines89ICT

=

(C

+

C)/(IC

+S)计算机通信集成电路经济超级计算机工作站个人计算机便携式计算机掌上计算机有线通信光通信无线/移动通信网络通信通信器信号处理器处理器可编程逻辑转换器电路办公数据库操作系统中间件应用905681013

14

141826222733465051556010277144132

137126149204166139

141

213248

2562492275%

2%27%46%-17%24%24%39%7%

2%

8%10%42%29%32%4%-9%-8%19%37%-32%1%28%18%7%

9%

3%-2.8%10%28%

28%

27%19%197619771978197919801981198219831984198519861987198819891990199119921993199419951996199719981999200020012002200320042005200620072008Worldwide

Semiconductor

Market（B

USD）

Growth

Rate(%)Global

sales

of

semiconductors

were

severely

impacted

by

the

world-wide

economicturmoil

in

2008,

resulting

in

the

year-on-year

sales

drop

since

2001.Total

sales

for

2008

were

$249

billion

compared

to

$256

billion

in

2007,

a

decrease

of

2.8percent.Source：WSC

GAMS

Meeting

2009Global

Semi

Market:

1976-20089192364512059789733006701

1

.

7

%5

.

2

%1

5

.

2

%3

.

8

%1

4

.

2

%7

.

6

%9

.

0

%16%14%12%10%8%6%4%2%0%350000300000250000200000150000100000500000G

D

PGR

Y

2

YData

Source：National

Bureau

ofStatistics

(NBS)Source：Industry

Restructuring,IBS

Report,

2007GDP

of

China:

1978–2008

(Unit:

100M

RMB)GDP

vs.

Semi

Market:

1995-2007集成电路

和

是信息产业的基础，没有自主的

和自主

，就没有自主产业

的

“心”和“魂”。“缺心少魂”的产业是人家

的附庸，没有发展的自主权。近50年，世界主要强国的发展历叱证明，必须拥有自己的

技术，尤其是集成电路和

这样的

基础产业。Source