高速串行接口技术详解课件

Deog-KyoonJeongSeoulNationalUniversityHigh-SpeedSerialLink1Deog-KyoonJeongHigh-SpeedSerIntroductionHigh-speedI/OoverviewHotdesignissuesDesignexamplesSummaryOutline2IntroductionOutline2IntroductionMoore’slawPerformance&densityimprovementindigitalsystem1001011021031041051061071081980198419881992199620002004Gatesdensity1001011021031041980198419881992199620002004CPUperformance3IntroductionMoore’slaw1001011IntroductionMoore’slaw1001011021031041980198419881992199620002004CPUperformanceMemoryaccess1001011021031041051061071081980198419881992199620002004GatesdensitySignalpinsGrowinggaplimitssystemperformance!!4IntroductionMoore’slaw1001011DigitalSystemPerformanceCommunication-boundComputation-boundPerformancebottleneckThecostofarithmeticoperationischeapnow“PentiumPro”10~20cycles/Arithmeticoperation70cycles/DRAMaccess“Pentium4”20~30cycles/Arithmeticoperation500~600cycles/DRAMaccess5DigitalSystemPerformanceCommComputingSystemHigh-speedI/OisneededeverywhereNorthBridgeCPUSouthBridgeMemoryGraphicDiskLANDisplaySwitchLocalI/OLongdistanceSAN6ComputingSystemHigh-speedI/OParallelBus&SerialLinkGroupdata(Bus)SourcesynchronousMatchedtraceParallelBusCoreI/OClockDataCoreI/OSerialLinkCoreI/OSerialDataCoreI/OSingletracePlesiochronousClockembeddedindataClock&datarecovery7ParallelBus&SerialLinkGrouParallelvs.SerialParallelBusSerialLinkHardwareComplexityLowHighLatencyShortLongSpeed~200Mbps/pin~10Gbps/pinormoreManufacturingCostHighLowWorldismovingtoward“seriallink”or“serial-link-likeparallelbus”!!8Parallelvs.SerialParallelBuSerialLinkArchitectureReceiverTransmitterPLLFramerPCSSerializerDeframerClockrecoveryChannelPCSDeserializerTransmitter+Receiver=Transceiver9SerialLinkArchitectureReceivLinkComponentPhaseDetectorLoop-FilterVoltage-ControlledOscillatorMCKi(fin)VctrerrorCKo(fout)Phase-lockedLoop(PLL)Frequencymultiplication:fout=M·finJitterfilterZero-delaybuffer10LinkComponentPhaseLoop-VoltagLinkComponentHigh-speed,lowvoltageswinginterfaceUsually,differentialSmallswing-~severalhundredsmVZ0Z0ChannelDCblockTermination(R=Z0)VTTVRRToCDRDriverLimitingamp11LinkComponentHigh-speed,lowLinkComponentClock&datarecovery(CDR)circuitsNRZPhaseDetectorLoop-FilterVoltage-ControlledOscillatorDiVctrerrorDoCKrDecisioncircuitDiDoCKr0110100100012LinkComponentClock&datarecLinkPerformanceMetricEyediagram&jitterRandombitsequenceTbitEyediagramTbitTiminguncertainty:JitterJitterhistogramIdealRealistic13LinkPerformanceMetricEyediaLinkPerformanceMetricEyediagramexample–Nearend&farendPLLFramerDeframerClockrecoveryChannel14LinkPerformanceMetricEyediaLinkPerformanceMetricBit-errorrate(BER)Inmostseriallinkstandards,BER<10-12isspecifiedEyediagramJitterhistogramRecoveredclockBiterror!!JitterPDF=

f(x)15LinkPerformanceMetricBit-errHigh-SpeedLinkStandardsNorthBridgeCPUSouthBridgeMemoryGraphicDiskLANDisplaySwitchLocalI/OSANDVILVDSEthernetSATASONET/SDHFibreChannelInfiniBandPCIExpressHyperTransportRDRAMXDR16High-SpeedLinkStandardsNorthIndustryRoadmaps0.1G1G10G100GData-rateEthernetSONET/SDHFastEthernetGigabitEthernet10GEthernetOC-48OC-192OC-768SATAOC-12XAUIGen1Gen2Gen3PCIExpressPCIe1.0PCIe2.0(?)FibreChannelFC-PI-1FC-PI-210GFCDVIVGAUXGASXGAYear2005,worldishere!!17IndustryRoadmaps0.1G1G10G100GDigitalVisualInterface(DVI)PCdisplay–CRT(analog)LCD(digital)DVI–DigitalVisualInterfaceAnalogDigital18DigitalVisualInterface(DVI)DigitalVisualInterface(DVI)TMDSTransitionminimizeddifferentialsignalingEMIreductionTMDSencoderPLLGraphiccontrollerTMDSdecoderPLLDisplaycontroller19DigitalVisualInterface(DVI)HighDefinitionMultimediaInterface(HDMI)HDMIHigh-definitionmulti-mediainterfaceDigitalvideo+multi-channelaudiointerfaceforconsumerelectronicsCompatiblewithDVI20HighDefinitionMultimediaIntSerialATA(SATA)NextgenerationATAbuswithinPCboxEliminatesfatATAcablesPoint-to-pointconnection–1.5G/3G/6GParallelATAcablingSerialATAcabling21SerialATA(SATA)NextgeneratiTransceiverChipDesignTechnologyCMOS,InP,GaAs,SiGe,BiCMOS…CMOSwillbetheeventualwinner–Lowcost,high-integritySpeedPowerconsumptionAreaLevelofintegrationMixed-signalSoC–Seriallinkinterface+digitalcircuitryTrade-off!!22TransceiverChipDesignTechnolHotDesignIssuesPLLFramerDeframerClockrecoveryCMOSseriallinktransceiver23HotDesignIssuesPLLFramerDefrHotDesignIssuesPLLFramerDeframerClockrecoveryCMOSseriallinktransceiverPrecise-timinggeneration-High-frequency,lowjitterPLLHigh-performanceCDR-High-speedNRZPD-VariousCDRarchitecturesHigh-speedCMOScircuits-Logicgates,analogbufferChannellosscompensation-Equalizer24HotDesignIssuesPLLFramerDefrPreciseTiminggenerationVCOnoisePLLjitterDataeyejitterLownoise,high-frequencyVCOisrequiredPhaseDetectorLoop-FilterVoltage-ControlledOscillatorMCKi(fin)VctrerrorCKo(fout)25PreciseTiminggenerationVCOnVoltage-ControlledOscillatorPoorNoiseGoodLowFrequencyHighWideTuningrangeNarrowLowCostHighRingoscillatorMstagesdMTf21=Td=C·V/ILCtankoscillatorParasiticresistanceNegativegmOn-chipspiralLOn-chipvaractorvarLCfp21=26Voltage-ControlledOscillatorPHigh-SpeedCMOSCircuitsCurrent-modelogic(CML)ZLNMOSLogicRR+LR+T-coilCMOSlogicNMOSPull-downPMOSPull-upComplementaryIntermediateSpeedFastSmallAreaLargeSmallPowerconsumptionLargeHigh-speedlogicgates27High-SpeedCMOSCircuitsCurrenHigh-SpeedCMOSCircuitsHigh-speedbufferwithon-chipinductorShuntpeaking–InsertsazeroathighfrequencySeriespeaking–IsolatesthebufferoutputnodefromloadcapacitanceNormalShuntpeakingShuntpeakingShuntseriespeakingSeriespeakingShuntdouble-seriespeakingSeriespeaking28High-SpeedCMOSCircuitsHigh-sHigh-SpeedCDR–NRZPDHoggephase-detector–LinearPDFull-rateoperationMatchedup/downwhenlocked–LessnoisyDQDQDNUPCKDABDCKABUPDNAreadifferencePhaseerrorVeryshortpulse!!Phaseerror–Clockearly29High-SpeedCDR–NRZPDHoggepHigh-SpeedCDR–NRZPDAlexanderphase-detector–BinaryPDWithmulti-phaseclock–TimeinterleavingBang-bangcontrol–NoisyD0D1ABTClockearlyD0D1ABTClocklateUPDNDQDQDQDQBADNUPTCKD30High-SpeedCDR–NRZPDAlexandHigh-SpeedCDR–ArchitecturesPLL-basedCDR1PLL/channel–PrecisephasecontrolSuitableforhigh-speed,high-performancesystemNRZPhaseDetectorLoop-FilterVoltage-ControlledOscillatorDiVctrerrorDoCKrDecisioncircuitEitherlinearorbinary31High-SpeedCDR–ArchitecturesChannelLossBand-limitedchannelBondingwire,PCBtrace,connector,cable…SkineffectDielectricloss32ChannelLossBand-limitedchannChannelLossEffectInter-symbolinterference(ISI)00010111Time-4TB-3TB-2TB-TBTB2TB3TB4TB0Amplitude33ChannelLossEffectInter-symboChannelLossCompensationTX–Pre-emphasisWithpre-emphasisWithoutpre-emphasis34ChannelLossCompensationTX–ChannelLossCompensationRX–EqualizationContinuoustimeequalizergDinDoutHigh-passfilterCapacitivedegeneration35ChannelLossCompensationRX–DesignExamples40GbpstransmitterProcess–0.13CMOSPower–2.8WArea–2.53.6mm2Features20Gstanding-waveVCOShunt-doubleseriespeakingat10/20/40GbuffersActivefeedbackat20Gdivider410on-chipspiralinductors36DesignExamples40GbpstransmitDesignExamples40Gtransmitter–StandingwaveVCOVaractors37DesignExamples40GtransmitterDesignExamples40Gtransmitter–testresultsTestchip25ps38DesignExamples40GtransmitterDesignExamplesFeatures10GLC-tankVCOPLL-based10GCDRDLL-basedquad3.125GCDR(XAUI)Integratedwithdigitalcontrolcore10GEthernetPHYwithXAUIinterfaceProcess–0.13CMOSPower–900mWArea–55mm239DesignExamplesFeatures10GEthDesignExamples3.5GcontinuoustimeadaptiveequalizerProcess–0.18CMOSArea–0.480.73mm2Power–80mW@3.5GCableinputCableoutputEqualizeroutputFeatures~3.5G–Adaptivemode~5G–Manualmode40DesignExamples3.5GcontinuousSummaryNow,digitalsystemperformanceisboundedbysystemI/ObandwidthInindustry,seriallinkI/OisgoingmainstreamTowardlow-cost,high-bandwidthsystemI/O,weshouldovercomeseveralphysicallimitationssuchasJitter&noiseChannellossDevicespeed41SummaryNow,digitalsystemperDeog-KyoonJeongSeoulNationalUniversityHigh-SpeedSerialLink42Deog-KyoonJeongHigh-SpeedSerIntroductionHigh-speedI/OoverviewHotdesignissuesDesignexamplesSummaryOutline43IntroductionOutline2IntroductionMoore’slawPerformance&densityimprovementindigitalsystem1001011021031041051061071081980198419881992199620002004Gatesdensity1001011021031041980198419881992199620002004CPUperformance44IntroductionMoore’slaw1001011IntroductionMoore’slaw1001011021031041980198419881992199620002004CPUperformanceMemoryaccess1001011021031041051061071081980198419881992199620002004GatesdensitySignalpinsGrowinggaplimitssystemperformance!!45IntroductionMoore’slaw1001011DigitalSystemPerformanceCommunication-boundComputation-boundPerformancebottleneckThecostofarithmeticoperationischeapnow“PentiumPro”10~20cycles/Arithmeticoperation70cycles/DRAMaccess“Pentium4”20~30cycles/Arithmeticoperation500~600cycles/DRAMaccess46DigitalSystemPerformanceCommComputingSystemHigh-speedI/OisneededeverywhereNorthBridgeCPUSouthBridgeMemoryGraphicDiskLANDisplaySwitchLocalI/OLongdistanceSAN47ComputingSystemHigh-speedI/OParallelBus&SerialLinkGroupdata(Bus)SourcesynchronousMatchedtraceParallelBusCoreI/OClockDataCoreI/OSerialLinkCoreI/OSerialDataCoreI/OSingletracePlesiochronousClockembeddedindataClock&datarecovery48ParallelBus&SerialLinkGrouParallelvs.SerialParallelBusSerialLinkHardwareComplexityLowHighLatencyShortLongSpeed~200Mbps/pin~10Gbps/pinormoreManufacturingCostHighLowWorldismovingtoward“seriallink”or“serial-link-likeparallelbus”!!49Parallelvs.SerialParallelBuSerialLinkArchitectureReceiverTransmitterPLLFramerPCSSerializerDeframerClockrecoveryChannelPCSDeserializerTransmitter+Receiver=Transceiver50SerialLinkArchitectureReceivLinkComponentPhaseDetectorLoop-FilterVoltage-ControlledOscillatorMCKi(fin)VctrerrorCKo(fout)Phase-lockedLoop(PLL)Frequencymultiplication:fout=M·finJitterfilterZero-delaybuffer51LinkComponentPhaseLoop-VoltagLinkComponentHigh-speed,lowvoltageswinginterfaceUsually,differentialSmallswing-~severalhundredsmVZ0Z0ChannelDCblockTermination(R=Z0)VTTVRRToCDRDriverLimitingamp52LinkComponentHigh-speed,lowLinkComponentClock&datarecovery(CDR)circuitsNRZPhaseDetectorLoop-FilterVoltage-ControlledOscillatorDiVctrerrorDoCKrDecisioncircuitDiDoCKr0110100100053LinkComponentClock&datarecLinkPerformanceMetricEyediagram&jitterRandombitsequenceTbitEyediagramTbitTiminguncertainty:JitterJitterhistogramIdealRealistic54LinkPerformanceMetricEyediaLinkPerformanceMetricEyediagramexample–Nearend&farendPLLFramerDeframerClockrecoveryChannel55LinkPerformanceMetricEyediaLinkPerformanceMetricBit-errorrate(BER)Inmostseriallinkstandards,BER<10-12isspecifiedEyediagramJitterhistogramRecoveredclockBiterror!!JitterPDF=

f(x)56LinkPerformanceMetricBit-errHigh-SpeedLinkStandardsNorthBridgeCPUSouthBridgeMemoryGraphicDiskLANDisplaySwitchLocalI/OSANDVILVDSEthernetSATASONET/SDHFibreChannelInfiniBandPCIExpressHyperTransportRDRAMXDR57High-SpeedLinkStandardsNorthIndustryRoadmaps0.1G1G10G100GData-rateEthernetSONET/SDHFastEthernetGigabitEthernet10GEthernetOC-48OC-192OC-768SATAOC-12XAUIGen1Gen2Gen3PCIExpressPCIe1.0PCIe2.0(?)FibreChannelFC-PI-1FC-PI-210GFCDVIVGAUXGASXGAYear2005,worldishere!!58IndustryRoadmaps0.1G1G10G100GDigitalVisualInterface(DVI)PCdisplay–CRT(analog)LCD(digital)DVI–DigitalVisualInterfaceAnalogDigital59DigitalVisualInterface(DVI)DigitalVisualInterface(DVI)TMDSTransitionminimizeddifferentialsignalingEMIreductionTMDSencoderPLLGraphiccontrollerTMDSdecoderPLLDisplaycontroller60DigitalVisualInterface(DVI)HighDefinitionMultimediaInterface(HDMI)HDMIHigh-definitionmulti-mediainterfaceDigitalvideo+multi-channelaudiointerfaceforconsumerelectronicsCompatiblewithDVI61HighDefinitionMultimediaIntSerialATA(SATA)NextgenerationATAbuswithinPCboxEliminatesfatATAcablesPoint-to-pointconnection–1.5G/3G/6GParallelATAcablingSerialATAcabling62SerialATA(SATA)NextgeneratiTransceiverChipDesignTechnologyCMOS,InP,GaAs,SiGe,BiCMOS…CMOSwillbetheeventualwinner–Lowcost,high-integritySpeedPowerconsumptionAreaLevelofintegrationMixed-signalSoC–Seriallinkinterface+digitalcircuitryTrade-off!!63TransceiverChipDesignTechnolHotDesignIssuesPLLFramerDeframerClockrecoveryCMOSseriallinktransceiver64HotDesignIssuesPLLFramerDefrHotDesignIssuesPLLFramerDeframerClockrecoveryCMOSseriallinktransceiverPrecise-timinggeneration-High-frequency,lowjitterPLLHigh-performanceCDR-High-speedNRZPD-VariousCDRarchitecturesHigh-speedCMOScircuits-Logicgates,analogbufferChannellosscompensation-Equalizer65HotDesignIssuesPLLFramerDefrPreciseTiminggenerationVCOnoisePLLjitterDataeyejitterLownoise,high-frequencyVCOisrequiredPhaseDetectorLoop-FilterVoltage-ControlledOscillatorMCKi(fin)VctrerrorCKo(fout)66PreciseTiminggenerationVCOnVoltage-ControlledOscillatorPoorNoiseGoodLowFrequencyHighWideTuningrangeNarrowLowCostHighRingoscillatorMstagesdMTf21=Td=C·V/ILCtankoscillatorParasiticresistanceNegativegmOn-chipspiralLOn-chipvaractorvarLCfp21=67Voltage-ControlledOscillatorPHigh-SpeedCMOSCircuitsCurrent-modelogic(CML)ZLNMOSLogicRR+LR+T-coilCMOSlogicNMOSPull-downPMOSPull-upComplementaryIntermediateSpeedFastSmallAreaLargeSmallPowerconsumptionLargeHigh-speedlogicgates68High-SpeedCMOSCircuitsCurrenHigh-SpeedCMOSCircuitsHigh-speedbufferwithon-chipinductorShuntpeaking–InsertsazeroathighfrequencySeriespeaking–IsolatesthebufferoutputnodefromloadcapacitanceNormalShuntpeakingShuntpeakingShuntseriespeakingSeriespeakingShuntdouble-seriespeakingSeriespeaking69High-SpeedCMOSCircuitsHigh-sHigh-SpeedCDR–NRZPDHoggephase-detector–LinearPDFull-rateoperationMatchedup/downwhenlocked–LessnoisyDQDQDNUPCKDABDCKABUPDNAreadifferencePhaseerrorVeryshortpulse!!Phaseerror–Clockearly70High-SpeedCDR–NRZPDHoggepHigh-SpeedCDR–NRZPDAlexanderphase-detector–BinaryPDWithmulti-phaseclock–TimeinterleavingBang-bangcontrol–NoisyD0D1ABTClockearlyD0D1ABTClocklateUPDNDQDQDQDQBADNUPTCKD71High-SpeedCDR–NRZPDAlexandHigh-SpeedCDR–ArchitecturesPLL-basedCDR1PLL/channel–PrecisephasecontrolSuitableforhigh-speed,high-performancesystemNRZPhaseDetectorLoop-FilterVoltage-ControlledOscillatorDiVctrerrorDoCKrDecisioncircuitEitherlinearorbinary72High-SpeedCDR–ArchitecturesChann