3,4,5分频电路设计并仿真

1,使用原理图文件设计三分频电路:仿真需要设置function功能，然后生成网表(processing)^HieiaiEhj.1@|Filf±|rf?DesignIooIefzinxiwUd.p£cTi«r-itcFiin■:tiflDi-ilSinraldtao®Wtllist祖PnDjertNa','iaatnrSluil「MEiilMi口dl-uuiSjffliilitiwiChl+jbjft+Ji囱UWi^HieiaiEhj.1@|Filf±|rf?DesignIooIefzinxiwUd.p£cTi«r-itcFiin■:tiflDi-ilSinraldtao®Wtllist祖PnDjertNa','iaatnrSluil「MEiilMi口dl-uuiSjffliilitiwiChl+jbjft+Ji囱UWiII：EFKWTIOTSHo%-.|Tt]11Iiftsip.Cwj-i1-irlaalS^rvnlitarTa-alF'习口“Ha:liaiufAatl^-£«rToni0Tdvk-FIF-3H«rAnil^tHrTddIttrl4：LMrCHI工£]MTjteCurr.aiPil.眈Stnar•:Sii'il-iti-jciSlrinl-itidCLH«bii4SlrmL-itianBl^partCtrl和Ctfl+SbJfHEM-snar^-IillLLbIixataanFa!■Ce«^i1LLiaa.I;Ctrl+：BQuastasII-P±/Pomloa(i/FP*&&/e：onEc/0i8S®：Vfsiniii- -[SisiiLlationReport\□g舄n峡。cm©gtojPffl■:«3in4 Ctrl+5bifHC|尊t业6fvErC-jiCt仿真结果:1Ejmla.lL仿真结果:1Ejmla.lLSeVLL&csaliVivi-fcaHi.J:ilHOl航i.«nCi™<iCQ2,使用Verilog程序设计三分频，四分频，五分频设计三分频：modulesanfp(clkin,clkout);inputclkin;outputclkout;reg[1:0]step1,step;always@(posedgeclkin)begincase(step)2'b00:step<=2'b01;2'b01:step<=2'b10;2'b10:step<=2'b00;default:step<=2'b00;endcaseendalways@(negedgeclkin)begincase(step1)2'b00:step1<=2'b01;2'b01:step1<=2'b10;2'b10:step1<=2'b00;default:step1<=2'b00;endcaseendassignclkout=~(step1[1]|step[1]);endmodule5hM«ld41*k.■•TtTHmSettincsSljr<il4,Usn.HfiiSimliliinCivir■£«curUem-5hM«ld41*k.■•TtTHmSettincsSljr<il4,Usn.HfiiSimliliinCivir■£«curUem-SlriOl^UibtideFiuwU£<1*1厚MwJffTneBu: U.5Sits*|fe|Pania: 153.73niHsi由|-3ftZ1ra EE:snGrvrwk^B2nztMr/jiircici- -[siiMiAii«n-5iaMlh1i«k► 选出氏导S土u|妙SkiktaUAtMIt岬oil•SliinhUlonWwd谢it惜S1JFK114.USDEiJ'SirtL«E<-?taciPit*Sumktj?Fit/^etUl^S四分频:modulesifenp(clkin,clkout);inputclkin;outputclkout;reg[1:0]countl;always@(posedgeclkin)begincase(count1)2'b00:count1<=2'b01;2'b01:count1<=2'b10;2'b10:count1<=2'b11;2'b11:count1<=2'b00;defaultcount1<=2'b00;endcaseendassignclkout=count1[1];endmodule五分频:modulefivefp(clkin,clkout,clkout1,clkout2);inputclkin;outputclkout,clkout1,clkout2;reg[2:0]cntl,cnt2;always@(posedgeclkin)begincase(cnt1)3'b000:cnt1<=3'b001;3'b001:cnt1<=3'b010;3'b010:cnt1<=3'b100;3'b100:cnt1<=3'b101;3'b101:cnt1<=3'b000;defaultcnt1<=3'b000;endcaseendalways@(negedgeclkin)begincase(cnt2)3'b000:cnt2<=3'b001;3'b001:cnt2<=3'b010;3'b010:cnt2<=3'b100;3'b100:cnt2<=3'b101;3'b101:cnt2<=3'b000;defaultcnt2<=3'b000;endcaseendassignclkout=cnt1[2]|cnt2[2];assignclkout1=cnt1[2];assignclkout2=cnt2[2];endmodule采用2个计数器cnt1和cnt2Cnt1需要在第3个clk上升沿时翻转，而且计数最高位要为1,即100.而后面计数需要保持2个周期的高，这样总共五个周期，只是占空比不为50%。Cnt2在第4个clk下降沿)时翻转，相对于cnt1延迟半个周期翻转。仿真图如下图免•”.SSHuiE母国Ucw5nmrr点ji畦]jlovd饥山中E1SiBula-lrr邕耳5«*-wym齐.；*ianoSiwtJ