EDA-制作16位乘法器

实验一LIBRARYieee;USEieee.std_logic_1164.all;USEieee.std_logic_unsigned.all;entityadderisport(a,b:instd_logic_vector(15downto0);sum:outstd_logic_vector(15downto0));endadder;architecturezhenofadderisbeginsum<=a+b;endzhen;实验二libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entitymux4isport(sel:instd_logic;a,b:instd_logic_vector(3downto0);y:outstd_logic_vector(3downto0));endmux4;architecturezhenofmux4isbeginprocess(sel,a,b)beginifsel='0'theny<=a;elsey<=b;endif;endprocess;endzhen;实验三libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entitysevenisport(input:std_logic_vector(2downto0);a,b,c,d,e,f,g:outstd_logic);endseven;architecturezhenofsevenisbeginprocess(input)begincaseinputiswhen"000"=>a<='1';b<='1';c<='1';d<='1';e<='1';f<='1';g<='0';when"001"=>a<='0';b<='1';c<='1';d<='0';e<='0';f<='0';g<='0';when"010"=>a<='1';b<='1';c<='0';d<='1';e<='1';f<='0';g<='1';when"011"=>a<='1';b<='1';c<='1';d<='1';e<='0';f<='0';g<='1';whenothers=>a<='1';b<='0';c<='0';d<='1';e<='1';f<='1';g<='1';endcase;endprocess;endzhen;libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entityshifterisport(input:instd_logic_vector(7downto0);cnt:instd_logic_vector(1downto0);result:outstd_logic_vector(15downto0));endshifter;architecturezhenofshifterisbeginprocess(cnt,input)variablem:std_logic_vector(15downto0);beginm:="00000000"&input;ifcnt="01"thenforiin7downto0loopm(i+4):=m(i);endloop;m(3downto0):="0000";elsifcnt="10"thenforjin7downto0loopm(j+8):=m(j);endloop;m(7downto0):="00000000";elsenull;endif;result<=m;endprocess;endzhen;实验五alibraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entityregisport(clk,clr,clken:instd_logic;in_reg:instd_logic_vector(15downto0);out_reg:outstd_logic_vector(15downto0));endreg;architecturezhen_aofregisbeginprocess(clk,clr,clken,in_reg)beginif(clk'eventandclk='1')thenif(clr='1'andclken='0')thenout_reg<=in_reg;elsifclr='0'thenout_reg<="0000000000000000";endif;endif;endprocess;endzhen_a;实验五libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entitycounter2isport(clk,clr:instd_logic;sum:outstd_logic_vector(1downto0));endcounter2;architecturezhen_bofcounter2isbeginprocess(clk,clr)variablem:std_logic_vector(1downto0);beginifclr='0'thenm:="00";elsifclr='1'thenif(clk'eventandclk='1')thenm:=m+1;endif;endif;sum<=m;endprocess;endzhen_b;libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entitycontrolisport(clk,rst,start:instd_logic;count:instd_logic_vector(1downto0);done,clken,regclr:outstd_logic;in_sel,shift:outstd_logic_vector(1downto0);state_out:outstd_logic_vector(2downto0));endcontrol;architecturezhen_aofcontrolistypestatesis(idle,lsb,mid,msb,err);signalcurrent_state,next_state:states;beginprocess(clk,rst,start)beginifrst='1'thencurrent_state<=idle;elsif(clk'eventandclk='1')thencurrent_state<=next_state;endif;endprocess;process(current_state,start,count)begincasecurrent_stateiswhenidle=>state_out<="000";ifstart='0'thendone<='0';clken<='1';regclr<='1';elsifstart='1'thendone<='0';clken<='1';regclr<='0';next_state<=lsb;endif;whenlsb=>state_out<="001";if(start='0'andcount="00")thenin_sel<="00";shift<="00";done<='0';clken<='1';regclr<='1';next_state<=mid;elsedone<='0';clken<='1';regclr<='1';next_state<=err;endif;whenmid=>state_out<="010";if(start='0'andcount="01")thenin_sel<="01";shift<="01";done<='0';

clken<='0';regclr<='1';next_state<=mid;elsif(start='0'andcount="10")thenin_sel<="10";shift<="01";done<='0';clken<='0';regclr<='1';next_state<=msb;elsedone<='0';clken<='1';regclr<='1';next_state<=err;endif;whenmsb=>state_out<="011";if(start='0'andcount="11")thenin_sel<="11";shift<="10";done<='1';clken<='0';regclr<='1';next_state<=idle;elsedone<='0';clken<='1';regclr<='1';next_state<=err;endif;whenerr=>state_out<="100";ifstart='1'thendone<='0';clken<='1';regclr<='0';next_state<=lsb;elsedone<='0';clken<='1';regclr<='1';next_state<=err;endif;whenothers=>null;endcase;endprocess;endzhen_a;SimulationWaveformsSimulationmode：FunctionalPointer:Interval:20.0he50.0nsclkenmhi士t--1E0]...1[1]CCiUTlt实验六bLIBRARYieee;USEieee.std_logic_1164.all;LIBRARYlpm;USElpm.all;ENTITYmult4x4ISPORT(dataa :INSTD_LOGIC_VECTOR(3DOWNTO0);datab :INSTD_LOGIC_VECTOR(3DOWNTO0);result :OUTSTD_LOGIC_VECTOR(7DOWNTO0));ENDmult4x4;ARCHITECTUREzhenOFmult4x4ISSIGNALsub_wire0:STD_LOGIC_VECTOR(7DOWNTO0);COMPONENTlpm_multGENERIC(lpm_hint :STRING;lpm_representation:STRING;lpm_type :STRING;lpm_widtha :NATURAL;lpm_widthb :NATURAL;lpm_widthp :NATURAL);PORT(dataa:INSTD_LOGIC_VECTOR(3DOWNTO0);datab:INSTD_LOGIC_VECTOR(3DOWNTO0);result:OUTSTD_LOGIC_VECTOR(7DOWNTO0));ENDCOMPONENT;BEGINresult<=sub_wire0(7DOWNTO0);lpm_mult_component:lpm_multGENERICMAP(lpm_hint=>"MAXIMIZE_SPEED=5",lpm_representation=>"UNSIGNED",lpm_type=>"LPM_MULT",lpm_widtha=>4,lpm_widthb=>4,lpm_widthp=>8)PORTMAP(dataa=>