《微机原理及应用实践(英文版)》Chapter 7 　THE PROGRAMMABLE INTERFACE AND APPLICATION

Chapter7THEPROGRAMMABLEINTERFACEANDAPPLICATION7.1The8255ParallelDataTransferInterface7.2The8251SerialDataTransferInterface7.3The8259ProgrammableInterruptController7.4The8254ProgrammableIntervalTimerOBJECTIVES

Uponfinishingthischapter,youwillbeable:

Tounderstandthefeatureofprogrammablechips,internal

structureandthefunctionofpins

Todesignapplicationcircuitwiththesechips

TomastertheinterruptsanddeeplyunderstandtheI/Ointerface

7.1The8255ParallelDataTransferInterface

Intheprevioussection,weinterfacedswitches,lights,andadigital-to-analogconvertertoanI/Oport.Intheseapplications,wefoundthattheyallhaveatleastonethingincommon:theyalluseparallelI/O.InparallelI/O,alldatabitsaresentorreceivedatthesametime,asagroup.Thisisverypopularinmostapplications!

Asweknow,mostapplicationsrequiremorethanoneI/Oporttogetonejobdone.PeripheraldesignersrealizedtheseyearsagoandcameupwithaparallelI/OperipheralcontainingthreeseparateI/Oports,allofwhichareprogrammable.Thisdeviceisthe8255programmableparallelinterface(PPI),showninFigure7.1.Inthissection,wewillseehowthe8255isinterfacedtothe8086/8088andhowitisprogrammed.7.1.1Interfacingthe8255

Figure7.2showsusadiagramofthe8255anditsI/Oandcontrolsignals.8255has40pinsandamongthem24pinsarededicatedtothethreeprogrammableportsA,B,andC.Thesethreeports,andafourthonecalledacontrolport,areaccessedvia

,

,

,andaddresslinesA0andA1.ARESETinputisincludedtoinitializethe8255whenpowerisfirstapplied.

Figure7.2alsoshowshowan8-inputNANDgateisusedtodecodeportaddressesA0HthroughA3H.WhentheaddressbuscontainsoneofthesefourportaddressesduringanI/Oaccess

,willbepulledlow.The8255willinternallydecodethestatesofA0andA1anddeterminewhichporttoaccess.Inthisexample,portAhasportaddressA0H.PortsBandCareaccessedthroughportsaddressA1HandA2H,respectively.AndthecontrolportisatA3H.Itisveryeasytodeterminethefourportaddressesbyadding0,1,2,and3tothebaseportaddressA0H,whichisfoundbysettingtheuppersixaddresslines(A2throughA7)tobewhatyouneedandassuming0forA1andA0.Figure7.2Interfacingthe8255PPI

Thenicestfeatureofthe8255isthatdifferenthardwarecircuitscanbeconnectedtoportA,B,andC,withthedirection(inputoroutput)ofeachportconfiguredwithinitialprogramming.Thisallowsan8088-basedsystemwithan8255inittobeusedformanydifferentpurposes.7.1.2Programmingthe8255

The8255hasthreemodesofoperation,mode0,mode1,andmode2,whicharedescribedasbelow:

Mode0:basicinput/output.

Inthismode,portsA,B,andCcanbeindividuallyprogrammedasinputoroutputports.

PortCisdividedintotwo4-bithalves,directionallyindependentfromeachother.So,therearesixteencombinationsofinputandoutputconfigurationsavailablewiththismode.

ARESETautomaticallycausesthe8255toentermode0withallportsprogrammedforinput.

Inputdataisnotlatched.Datamustbepresentwhentheportisbeingreadbytheprocessor.Outputdataislatched,aswewouldnormallyexpecttheminanoutputport.

Toprogramthe8255formode0operationandsetthedirectionofeachport,amodewordmustbeoutputtothecontrolport.ThedefinitionofthemodewordisshowninFigure7.3.

TheMSBisthemode-setflag,whichmustbea1toprogramthe8255.Bits5and6areusedtoselectthe8255’smode.00selectsmode0,01selectsmode1,andmode2isselectedwhenbit6ishigh.Bit2isalsousedasaselectbitformodes0and1.Theother4bitssetthedirectionofportsAandBandbothhalvesofC.A0indicatesanoutputportanda1indicatesaninputport.

Ifconfigurethe8255formode0,andallportsprogrammedforinput,thenthemodewordmustbe10011011(9BH).Thisbytemustbeoutputtothecontrolporttoconfigurethe8255.Thefollowingtwoinstructionswillinitializethe8255afterareset:

MOV AL,9BH

OUT 0A3H,ALFigure7.38255modewordformat

Oncethe8255isprogrammed,theportscanbeaccessedwiththeappropriateINinstruction,suchasINAL,0A0H(whichreadsportA).WhatmodewordisneededtoprogramportAforinput,portBforoutput,andbothhalvesofportCforinput?Youshouldget99HwhenusingthemodewordformatofFigure7.3.

Assumethatthe8255hasaDIPswitchwiredtoportAandasetofLEDswiredtoportB.ThefollowingcodecanbeusedtorepeatedlyreadtheswitchesandsendtheirstatestotheLEDs.

READEM: MOV AL,99H ;configure8255forAin,Bout,mode0

OUT 0A3H,AL

GETSW: IN AL,0A0H ;readswitches

OUT 0A1H,AL;senddatato

lights

JMP GETSW

Inthiscase,aclosedswitchturnsanLEDoff.

Mode1:Strobeforinput/output.

8255usesportCasahandshakingport.Handshakingsignalsarecommonlyusedinprinterstosensethestatusofthepaper-outsensorandtheprinter’sreadinesstoacceptnewdata.

PortAandBcanbeprogrammedforinputoroutput.

Dataarelatchedinbothdirections.

IfportAisprogrammedforinput,astrobesignalisneededonPC4towritedataintoportA.The8255willacknowledgethenewinputdatabyoutputtinga1onPC5.ThesetwosignalsonportCaredefinedasshowninFigure7.4(a).PC5isIBFA,thatmeanstheinputbufferAfull.IBFisclearedwhentheprocessorreadsportA.PortBoperatesinthesameway,usingPC2andPC1ashandshakingsignals.Bothportshavethecapabilityofcausinganinterruptwhendataisstrobeintothem.Figure7.4Mode1portdefinitions

TheINTRoutputwillgohighwhenIBFgoeshighandtheinternalinterrupt-enablebitisset.PC4andPC2makeuptheinterrupt-enablebitsforportsAandB.SettingPC4willcauseINTRtogohighwhendataisstrobeintoportA.Readingtheinputportwillcleartheinterruptrequest.Thisinterruptmechanismisausefulalternativetousingsoftwaretoconstantlypolltheinputport.Pollingwastesalotoftimewaitingforinputdatathatmaynotbethere.Interruptingtheprocessoronlywhennewdatahasarrived,willresultinmoreefficientprogramexecution.Thisisoneoftheadvantagesofmode1.

YoumaynoticethattheportCbitsareassigneddifferentlyintheoutputconfiguration.Forexample,PC4andPC5arenowusedforgeneralpurposeI/O.Thetypeofhardwareconfigurationmustbedecidedon,andthenconnectedtotheappropriatebitsinportC.

Mode2:StrobeforbidirectionalI/O.

ThismodeallowsportAtooperateasan8-bitbidirectionalbus.Thisisneededtoallowthe8255tobe

interfacedwith8-bitperipheralssuchasUARTS,whichrequireabidirectionaldatabus.

BitsinportCareagainusedforhandshakingandgeneralpurposeI/O,asindicatedbyFigure7.5.

PortBcanoperateasaninputportoroutputportinmode0ormode1.WhenoperatingportBinmode0(withportAinmode2),PC0throughPC2areavailableforgeneralpurposeI/O.ThedefinitionsforPC0throughPC2inmode1applywhenportBisoperatedinmode1withportAinmode2.Figure7.5Mode2operationFigure7.68-bitanalog-to-digitalconverter

Thedatareadfromthe0804issentouttotheLEDsonportB.Thisgivesavisualindicationthateverythingisworkingproperly.BeingabletosplitupportCmakestheinterfacewiththe0804easytoaccomplish.

The8255isconfiguredandinitializedinthisway:

MOV AL,91H ;mode0,Ain,Bout,CLin,CHout

OUT 43H,AL ;sendtocontrolport

MOV AL,90H ;RDandWRbothhigh

OUT 42H,AL ;sendtoportC

AroutinetodigitizeawaveformpresentedtotheanaloginputwouldrequiresuccessiveCALLstoVCON,storingAHinadatatableeachtimeVCONreturns.Oncethewaveformhasbeendigitized,thedatabytesthatrepresentitcanbealteredandthenoutputtoadigital-to-analogconverterforplayback.

2. Thecentronicsparallelprinterinterface

Anotherapplicationinvolvingparalleldatatransferistheuseofaparallelprinter.Aparallelprinterconnection,suchastheCentronicsTMstandard,providesforcommunicationbetweenthecomputerandtheparallelprinter.ASCIIcodesareoutputtotheprinter,andprinterstatusismonitoredbythecomputerthroughsignalstoaDB25connector,asshowninFigure7.7.OnthePC,threeportsareusedtointerfacewiththeprinter.Adataport(address378H)outputs8-bitASCIIinformationtotheprinter.

Acontrolport(address37AH)suppliesanumberofcontrolsignals(suchasstrobeandinitializeprinter),andastatusport(address379H)monitorsprinterstatus.Ingeneral,toprintacharacter,thefollowingsequencemusttakeplace:

OutputASCIIcodetodataport

Outputalow-goingstrobepulse

Waitforalow-goingacknowledgepulseFigure7.7Centronicsparallelprinterconnections(CourtesyofCentronicsDataComputerCo.)

Thissequence,illustratedinFigure7.8,performshandshakingbetweentheprinterandthecomputerandguaranteesthatthecomputerdoesnotsenddatatotheprinterfasterthanwhichtheprintercanacceptit.Figure7.8Pinter/computerhandshaking

7.2The8251SerialDataTransferInterface

SerialI/Oofferstheconvenienceofrunningasmallnumberofwiresbetweentwopoints(threewilldothejobinmostcases),whileatthesametimebeingveryreliable.Althoughwemustwaitlongertoreceiveourdatabecauseitistransmittedonly1bitatatime,weareabletoplaceoutcommunicationdevices(computers,terminals),farawayfromeachother.

Worldwidenetworksnowexist,connectedviasatellites,basedonserialdatatransmission.Theperipheralcoveredinthissection,the8251UART,implementsserialdatatransmissioninavarietyofformats.Figure7.9showstheoutlookof8251chip.Figure7.9theviewofInterC8251(CourtesyofIntelCo.)

[ReadingMaterial]

ThestandardserialdatatransmissionwaveformforanyUARTisdepictedinFigure7.10.

Figure7.10StandardTTLserialdatawaveform

Thenormalstateofthelineisalogic1.Thislevelindicatesthatnoactivityispresent(thatis,nodataisbeingtransmitted).Whenthelinelevelfallstoalogic0(thestartbit),thereceivingUARTknowsthatanewcharacterisbeingtransmitted.Thedatabitsrepresentingthecharacter(ordata)beingtransmittedareclockedoutintheordershown,leastsignificanttomostsignificant.

Followingthedatabitsistheparitybit,whichwillbeusedbythereceivingUARTtodeterminetheaccuracyofthedataitreceived.TheparitybitinFigure7.8showsthatthedatahasevenparity.Thelastbitsinanytransmissionarethestopbits,whicharealwayshigh.Thisgetsthelinebackintoitsinactivestate.Weareabletosetthenumberofdatabits,thetypeofparityused,thenumberofstopbits,andotherparameterthroughsoftware.

7.2.1Interfacingthe8251

The8251wasoriginallydesignedtobeusedwiththe8080and8085microprocessors,8-bitmachinesthatprecededthe8088.The8088interfaceswiththe8251easily,requiringtheusualaddressdecoderandafewcontrolsignals.Figure7.11showsacompleteserialdatacircuitforthe8088.Figure7.118251to8088interface

[ReadingMaterial]ThefrequencyoftheTTLsignalattheseinputsdeterminesthebitrateandtimeofthetransmitterandreceiver.ItiscommontoruntheUARTataclockspeedsixteentimesgreaterthanthebaudrate.So,a2,400baudtransmissionraterequiresa38.4kHzclock(multiply2,400by16).Thisfrequencyandotherstandardbaudratefrequenciesaregeneratedautomaticallybythe14,411baud-rategenerator.Allthatisneededisa1.8432MHzcrystal.

Attemptingtotransmitadigital(0-5V)signaloveralonglengthofwirecausesdistortioninthesignalshapeduetothelinecapacitance.Itwasdiscoveredthatmakingthesignalswitchfromapositivevoltagetoanegativevoltagehelpstoeliminatethedistortion.Higherbaudratesarepossibleusingthe+/-swingingsignal.Astandardwasdevelopedforthistypeofsignal,calledtheRS232standard.TakeanotherlookatthewaveforminFigure7.8.ThisistheTTLwaveformthatcomesoutoftheUART’stransmitter.TheRS232waveformthatgetstransmittedoverthewiresisinvertedandswingsplusandminus.

So,ahighlevelontheTTLwaveformcreatesalow(negative)levelontheRS232Cwaveform.AnintegratedcircuitcapableofperformingtheRS232C-to-TTLconversionsistheMAX232CPE.Thischipisespeciallyusefulbecause,byaddingfour22µFelectrolyticcapacitors,theMAX232generatesitsown+/-10Vsupplywhileneedingonlythestandard5V.Olderchips,suchasthe1488linedriverand1489linereceiver,requiredadditionalexternalpowersupplies.TheMAX232hastwoseparateRS232Cdrivers/receiversforsystemsrequiringtwoserialdatachannels.7.2.2Programmingthe8251

Becausethe8251isconnectedtoRESET,weareassuredthatthe8251isfunctionalafterapower-on.Itisstillnecessarytoprogramthe8251toensurethatthecorrectnumberofdatabitswillbeused,thattheparitywillbegeneratedasexpected,andsoon.Toprogramthe8251,aseriesofbytesareoutputtothecontrolport(79Hforexample).

Thefirstbyteiscalledthemodeinstruction.TheformatofthisbyteisshowninFigure7.12.The8251canoperateinasynchronousmodeorsynchronousmode.Inasynchronousmode,thebaudrateisdeterminedbythelower2bitsinthemodeinstruction.Ifthese2bitsarelow,synchronousmodeisselected.

Thenumberofdatabitsusedinatransmissionisselectedbybits2and3.Toenablegenerationofaparitybit,bit4mustbeset.Oddorevenparityischosenbythesettingofbit5.Finally,thenumberofstopbitsischosenbytheupper2bitsinthemodeinstruction.ThewaveformofFigure7.10contained7databits,anevenparitybit,and2stopbits;therefore,therequiredmodeinstructionbyteis0FAH.Toprogramthe8251,wecanuse:

MOV AL,0FAH

OUT 79H,ALFigure7.128251modeinstructionformat

BecauseanX16clockwasselected,the8251willoperateinasynchronousmode.Synchronousmodeisusedforhigh-speeddatatransmission(notusuallyneededforcommunicationwithaserialdisplayterminal).Synchronousmodeisselectedbymakingthelowertwomodeinstructionbits0.Inthiscase,theuppertwomodeinstructionbitsdonotsetthenumberofstopbits,butratherthenumberofsynccharacterstransmittedandthefunctionoftheSYNDETpin.

Asecondbytemustbeoutputtothecontrolporttocompletetheinitializationofthe8251.Thisbyteiscalledthecommand

instruction.ThebitsareassignedasshowninFigure7.13;theyhavethefollowingmeanings:

Bit0:transmitenable.Enabletransmitterwhenthisbitisset.

Bit1:dataterminalready.Settingthisbitwillforcetheoutputlow.

Bit2:receiveenable.Enablereceiverwhenthisbitisset.

Bit3:sendbreakcharacter.SettingthisbitforcesTxDlow.

Bit4:errorreset.SettingthisbitclearsthePE,OE,andFEerrorflags.

Bit5:requesttosend.Settingthisbitforcestheoutputlow.

Bit6:internalreset.Toresetthe8251andprepareforanewmodeinstruction,thisbitmustbeset.

Bit7:enterhuntmode.SettingthisbitenablesasearchforSYNCcharacters(insynchronousmodeonly).Figure7.138251commandinstructionformat

Thecommandinstructionneededtoenablethetransmitterandreceiverandignoreallotherfunctionsis05H.Thisbytemustbeoutputtothecontrolportafterthemodeinstruction.So,tototallyinitializethe8251foroperationinthecircuitofFigure7.11,weneedtheseinstructions:

MOV AL,0FAH ;modeinstruction

OUT 79H,AL

MOV AL,5 ;commandinstruction

OUT 79H,AL

OncetheUARThasbeenprogrammed,wehavenoneedforthecontrolport.Instead,weusethe8251’sstatusporttohelpcontrolthewaybywhichdataaretransmittedandreceived.Figure7.14showsthebitassignmentsinthe8251’sstatusport.ParticularlyimportantaretheTxRDY(transmitterready)andRxRDY(receiverready)flags.Theytelluswhenthetransmitterisreadytotransmitanewcharacterandwhenthereceiverhasreceivedacompletecharacter.

Anumberoferrorbitsareincludedtoshowwhatmayhavegonewrongwiththelastreception.PEisparityerrorandwillgohighiftheparityofthereceivedcharacteriswrong.OEisoverrunerrorandwillbesetifanewcharacterisreceivedbeforetheprocessorreadthelastone.FEstandsforframingerrorandgoeshighwhenstopbitsarenotdetected.SYNDET(synccharacterdetected)willgohighwhenasyncbyteisreceivedinsynchronousmode.DSR(datasetready)willgohighwhenever

islow.Figure7.148251statusbyte

Theprogrammermustusethe8251’sstatusbitstoensureproperserialdatacommunication.Figure7.15showshowthefirsttwobitsareusedtoimplementasimpleserialinput/outputprocedure.Figure7.15I/Oflowcharts

[ReadingMaterial]BothflowchartsindicatethatrepeatedtestingoftheRxRDY/TxRDYbitsmaybenecessary.Forexample,toshowtheimportanceofthisrepeatedtesting,considerthefollowingcase.Supposethatan8251isconfiguredtotransmitandreceivedataat1,200baud,with7databits,oddparity,and1stopbit.Howlongdoesittaketofullytransmitorreceiveacharacter?At1,200baud,thebittimeisjustover833µs,andtheselectedwordlengthof10bitsmakesthetotaltimetoreceiveortransmitasinglecharacterroughly8.3ms.

Itisnotdifficulttoimaginehowmanyinstructionsthe8088mightbeabletoexecutein8.3ms.Wouldafewthousandbeunreasonable?Probablynot.Therefore,weusethestatusbitstoactuallyslowdownthe8088,sothatitdoesnottrytosendorreceivedatafromthe8251fasterthanthe8251canhandle.

Thetwoshortroutinesasfollowsshowhowacharacterinputandacharacteroutputroutinemightbewrittenin8088code.7.2.38251Applications

1. Videotypewriter

OncetheroutinestocommunicatewiththeUARTareinplace,wecanbeginusingtheminapplications.AvideotypewriterrequiresthataserialdisplayterminalbeconnectedtotheUARTthatiscontrolledbyCHARINandCHAROUT.Thesimpleprogrammingloopthatfollowsisusedtoechoeverycharacterreceived(presumablyfromthekeyboard)tothescreen.Line-feedcharactersareinsertedwhenacarriagereturnisseen.

Thissimpleroutinecanbemodifiedtoalloweditingandotherfeaturesandisleftforyoutothinkaboutonyourown.

2. Readcom1:aserialI/Oapplicationforthepersonalcomputer

ThepersonalcomputerprovidesserialI/OthroughitsCOM1connector.AmouseormodemcommonlyusesCOM1tocommunicate.Portaddresses3F8Hthrough3FFHarenormallyreservedforusewithCOM1(withCOM2throughCOM4usingotherranges).OnlytwooftheseaddressesareneededtoperformsimpleserialI/OthroughCOM1onceitsUARThasbeeninitialized.Theseare

3F8H:Dataport(receiver/transmitterdataregisters)

3FDH:Statusport(receiver/transmitterreadyflags)

CharactersreceivedbyCOM1canbereadbyinputtingfromport3F8H.Outputtingtoport3F8Htransmitsacharacter.

Twostatusbitsonport3FDHmustbeusedtosynchronizetheI/Ooperations:

Bit0:receiverreadywhenhigh

Bit5:transmitterreadywhenhigh

ThesestatusbitsaretestedinamannersimilartothatusedintheCHARINandCHAROUTroutines.

TheREADCOM1programthatfollowsreadscharactersreceivedbyCOM1anddisplaystheir8-bitbinaryequivalentsonthedisplay.IfacharacterisaprintableASCIIcharactercode,theactualcharacterisoutputaswell.Thereceiver-readybit(bit0ofport3FDH)isexaminedthroughtheuseoftheTESTinstruction.OncetheUARTstatushasbeenplacedinregisterAL,theinstruction“TESTAL,1” isusedtocheckthestateofbit0.Heregivesoneprogram.

READCOM1executesuntilanykeyonthekeyboardispressed.ItmightbeinterestingtowatchthevaluesreturnedbyamouseconnectedtoCOM1.Whatpatternsarereceivedwhenthemousemovesleft,right,up,anddown?Whathappenswhenamousebuttonispressed?

BesuretoinitializeCOM1totheproperbaudratebeforeusingREADCOM1.ThisiseasilyaccomplishedwiththeuseoftheMODEcommand.Forexample,toinitializeCOM1for2,400baud,noparity,8databits,and1stopbit,usethiscommand:

C>MODECOM1:2400,N,8,1

ThisisespeciallyimportantwhenusingCOM1tocommunicatewiththesingle-boardcomputerofaworking8088system.

7.3The8259ProgrammableInterruptController

InterruptsareparticularlyusefulwheninterfacingI/Odevicesthatprovideorinquiredataatrelativelylowrate.Unlikethepollingtechnique,forinstanceinsection7.1,interruptprocessingallowsthemicroprocessortoexecuteanytypeofsubroutineswhenfinishingthehandshakingofoutsidedevices’interruptrequest,whichisalsocalledinterrupt-processedI/Otechnique.

Theinterruptsofthe8086and8088areidentical.Bothmicroprocessorshavetwohardwareinterruptinputs(INTRandNMI)andoneinterruptoutput(),twointerruptrelatedflags(IandT)intheflagregister,andfourtypesofsoftwareInstructions:INT,INTO,INT3,andIRET,whicharediscussedinChapter4.Inthissection,wewilldiscussthehardwareinterruptandthe8259programmableinterruptcontroller.

Hardwareinterruptsaregeneratedbychangingthelogiclevelsoneitheroftheprocessor’shardwareinterruptsinputs.The8086/8088hastwohardwareinterruptinputs:nonmaskableinterrupt(NMI)andinterruptrequest(INTR).BecausetheNMIisinternallydecoded,atype-2interruptisexecutedwheneverthispinisactivated.TheINTRinputmustbeexternallydecodedtoselectavector.AnyvectorisallowedforINTR,butinmostcasesitischosenabovethereservedinterruptvectors.The

outputprovidesavectornumberinresponsetoanINTR.

NMIisanedge-triggeredinputthatrequestsaninterruptonthepositiveedge(0→1)transition.Thisinputmustgolowforatleasttwoclockingperiodsbeforethepositiveedgeisrecognizedbythe8086/8088.NMIisoftenusedforparityerrororothermajorsysteminterruptrequirementslikepowerfailures,wheretheprocessorwillstorethecontentsoftheinternalregistersinabattery-backed-upmemory.

INTRinputislevel-sensitive.Itmustbeheldatlogic1leveluntilitisrecognizedandmustbereturnedtologic0levelbeforetheendoftheinterruptserviceprocedure.Thisinputisautomaticallydisabledatitsacceptancebythemicroprocessorandautomaticallyre-enabledattheendoftheinterruptserviceprocedurebytheIRETinstruction.

INTRcanalsobeenabledanddisabledbythestateoftheinterrupt-enableflag(IF).TheCLI(clearinterrupt-enableflag)instructionclearsIF,whichdisablesINTR.TheSTI(setinterrupt-enableflag)instructionsetsIF,allowingINTRtorespondtorequests.ThismeansthatINTRcanbemasked(disabled).NMIgetsitsnamefromthefactthatitsoperationcannotbedisabled.NMIalwayscausesaninterruptsequencewhenitisactivated.

putsaninterrupttypenumberontothedatabusinresponsetotheINTRinputwhenthe8086/8088microprocessormakesaresponse.Therearemanymethodstocompletethistask,suchasusingathree-statebufferoraresistorcircuit.

Whathappenswhenasoftwareandhardwareinterruptoccuratthesametime?Theprocessorhasatechniqueforhandlingthissituation;itrequiresthattheinterruptsbeprioritized.InterruptswiththehighestpriorityareDivide-error,INT,andINTO.

NMIandINTRhavelowerpriorities,withSingle-stephavingthelowest.Ifbothhardwareinterruptsareactivatedsimultaneously,NMIwillbeservicedfirst,withINTRpendinguntilitgetsitschancetoberecognizedbytheprocessor.Ifadivide-errorandNMIoccursimultaneously,divide-errorwillberecognizedfirst,followedbyNMI.

[ReadingMaterial]

WesawinthepreviouschapterthatamicroprocessormustbeinterfacedwithanI/Odevicetocommunicatewiththeoutsideworld.SoftwaresupportisrequiredforeachI/Odevicetoensureitsproperoperation.Forexample,thereceiverstatusofaUARTmustbefrequentlyexaminedtoensurethatnoreceivedcharactersarelost.

Ifaloopisusedtotestthereceiverstatus,theprocessormayendupspendingagreatdealoftimewaitingforthechancetosendthenextcharacter.Whileitisdoingthis,itcannotdoanythingelse!Anefficientsolutiontothissituationisaccomplishedbyaddinganinterruptsignaltotheprocessor.WheneveracharacterisreceivedbytheUART,theUARTwillinterrupttheprocessor.AspecialinterruptserviceroutinewillbeusedtoreadtheUARTandprocessthenewcharacter.

WhentheUARTisinterfacedinthisway,theprocessorisfreetoexecuteothercodesduringthetimeswhentheUARThasnotyetreceivedacharacter.Inthisinterrupt-drivenI/Oscheme,theprocessoraccessestheUARTonlywhenithasto.ThisexampleillustratesthebasicdifferencesbetweenpolledI/Oandinterrupt-drivenI/O.

Forsomesystems,pollingisagoodsolution.Thisisespeciallytruewhenthesystemisdedicatedtodoingonetaskoverandoveragain.Whenasystemisusedinamoregeneralway,theprocessorcannotaffordtospenditstimeconstantlypollingeachI/Odevice.Inthiscase,interruptsprovideasimplewaytoserviceallperipheralsonlywhentheyneedtheprocessor’sattention.7.3.2The8259anditsinterfacing

About8259

Ifweexpandtheideaofinterrupt-drivenI/Otoanentiresystem,thenumberofinterruptsrequiredquicklyaddsup.Separateinterruptsmaybeusedforreal-timeclock/calendars,floppyandharddiskdrives,thecomputer’skeyboard,serialandparallelinterfaces,videodisplays,andmanyotherdevices.Ea