VHDL及数字集成电路设计VHDL3-1

第三章时序逻辑的设计优化VHDL与数字集成电路设计2storagemechanisms•positivefeedback•charge-based锁存器：电平敏感时序逻辑电路类型寄存器：边沿敏感DClkQClkDQDClkQClkDQ锁存器类型基于锁存器的设计Nlatchistransparent

whenf=0Platchistransparent

whenf=1NLatchLogicLogicPLatchf时间约束tCLKtDtc2qtholdtsutQDATASTABLEDATASTABLERegisterCLKDQ正反馈与双稳态Vi1ACBVo2Vi1=Vo2Vo1Vi2Vi2=Vo1双稳态Gainshouldbelargerthan1inthetransitionregion基本锁存器电路DCLKCLKDConvertingintoaMUXForcingthestate(canimplementasNMOS-only)多路选择器锁存器Negativelatch(transparentwhenCLK=0)Positivelatch(transparentwhenCLK=1)CLK10DQ0CLK1DQ具体电路主从寄存器TwooppositelatchestriggeronedgeAlsocalledmaster-slavelatchpair具体电路Multiplexer-basedlatchpair建立时间降低时钟负载的主从寄存器RS触发器带有时钟控制的RS触发器Cross-coupledNANDsAddedclock不同的状态储存机制DCLKCLKQDynamic(charge-based)StaticC2MOS寄存器施密特触发器VTCwithhysteresisRestoressignalslopes

CMOS施密特触发器MovesswitchingthresholdofthefirstinverterCMOS施密特触发器2数据寄存器及相关电路最快数据传递：时钟周期数据寄存器及相关电路最快数据传递时间：时钟周期在输入端添加控制电路，构成其他类型的触发器D触发器的控制与扩展数据寄存器及相关电路数据寄存器及相关电路D触发器的控制与扩展并行寄存与移位寄存数据寄存器及相关电路多功能移位寄存器数据寄存器及相关电路第四章算数逻辑单元4.1加法器4.2乘法器VHDL与数字集成电路设计加法器设计加法运算从最低位开始，逐步向高位进行；每一位相加时，产生1位结果（s），同时产生1位进位（c）；最低位相加时，只需要考虑2个数据的相加：半加；其余位相加时，需要考虑3个数据的相加：全加。4.1加法器、算数逻辑单元加法器设计半加器4.1加法器、算数逻辑单元加法器设计全加器4.2加法器、算数逻辑单元利用半加单元设计全加器4.2加法器、算数逻辑单元可扩展的串行加法器：采用全加器级联构成4.2加法器、算数逻辑单元4位串行加法器：ASIC设计第1级采用半加；最高级取消进位。4.2加法器、算数逻辑单元36Full-Adder37TheBinaryAdder38ExpressSumandCarryasafunctionofP,G,DDefine3newvariablewhichONLYdependonA,BGenerate(G)=ABPropagate(P)=AÅBDelete=A

BCanalsoderiveexpressionsforSandCobasedonDandP

Propagate(P)=A+BNotethatwewillbesometimesusinganalternatedefinitionfor39TheRipple-CarryAdderWorstcasedelaylinearwiththenumberofbitsGoal:Makethefastestpossiblecarrypathcircuittd=O(N)tadder=(N-1)tcarry+tsum40ComplimentaryStaticCMOSFullAdder28Transistors41InversionProperty42MinimizeCriticalPathbyReducingInvertingStagesExploitInversionProperty43ABetterStructure:TheMirrorAdder44TransmissionGateFullAdder45ManchesterCarryChain46ManchesterCarryChain47Carry-BypassAdderAlsocalled

Carry-Skip48Carry-BypassAdder(cont.)tadder=tsetup+Mtcarry+(N/M-1)tbypass+(M-1)tcarry+tsum49CarryRippleversusCarryBypass50Carry-SelectAdder51CarrySelectAdder:CriticalPath52LinearCarrySelect53SquareRootCarrySelect54LookAhead-BasicIdea

55Look-Ahead:TopologyExpandingLookaheadequations:Alltheway:56LogarithmicLook-AheadAdder57CarryLookaheadTreesCancontinuebuildingthetreehierarchically.58TreeAdders16-bitradix-2Kogge-Stonetree59Example:DominoAdderPropagateGenerate60Example:DominoAdderPropagateGenerate第四章算数逻辑单元4.1加法器4.2乘法器VHDL与数字集成电路设计8位乘法器设计：基于基本单元的扩展设计2位乘法器：由1位乘法结果相加而成成本：4+4+4门时间：1+34.3数据累加与乘法器设计8位乘法器设计：基于基本单元的扩展设计4位乘法器：由2位乘法结果相加而成4个2位乘法器并行运算，产生4组数据，然后进行相加。4.3数据累加与乘法器设计65TheBinaryMultiplication66TheArrayMultiplier67TheMxNArrayMultiplier

—CriticalPathCriticalPath1&268Carry-SaveMultiplier69MultiplierFloorplan70Wallace-TreeMultiplier71Wallace-TreeMultiplier72TheBinaryShifter7