数字逻辑第四章课后答案

数字逻辑第四章课后答案盛建伦：《数字逻辑与VHDL逻辑设计》习题解答习题4解答4-1试用与非门设计实现函数F(A,B,C,D)=Σm(0,2,5,8,11,13,15)的组合逻辑电路。解：首先用卡诺图对函数进行化简，然后变换成与非-与非表达式。化简后的函数4-2CDAB00010010010111100110111000111000A&&BC&&&&&F&FBCDABDBCDACDBCDABDBCDACDBCDABDBCDACDD&试用逻辑门设10。解：本题的函数不能化简，但可以变换成异或表达式，使电路实现最简。真值表：逻辑函数表达式：ABC000001010011100101110111Y01101001=1ABC逻辑图=1YYABCABCABCABC(AB)C4-1盛建伦：《数字逻辑与VHDL逻辑设计》习题解答4-3用与非门设计四变量多数表决电路。当输入变量A、B、C、D有三个或三个以上为1时输出为1，输入为其他状态时输出为0。解：真值表：先用卡诺图化简，然后变换成与非-与非表达式：ABCD00000010001101000101011001111000101010111100110111101111YABDABCBCDACDABDABCBCDACDABDABCBCDACDY00000010010111C&00010AB00011110CD00010000001011100111001010010逻辑图A&B&&Y逻辑函数表达式：D4-4&44解：首先根据所给问题列出真值表，然后用卡诺图化简逻辑函数，按照化简后的逻辑函数画逻辑图。4-2盛建伦：《数字逻辑与VHDL逻辑设计》习题解答真值表：卡诺图化简：ABCDY1Y2Y3Y400000000000100010010001100110010010001100101011101100101011101001000110010011101101011111011111011001010110110111110100111111000ABCD00011110000011011100111100100011Y3的卡诺图化简后的逻辑函数：Y1AY2ABABABY3BCBCBCY4CDCDCD4-3ABCD00011110000000010000111111101111Y1的卡诺图ABCD00011110000000011111110000101111Y2ABCD00011110000101010101110101100101Y4逻辑图Y1Y2Y3Y4=1=1=1ABCD盛建伦：《数字逻辑与VHDL逻辑设计》习题解答4-5图4.48所示是一个由两台水泵向水池供水的系统。水池中安置了A、B、C三个水位传感器。当水池水位低于C点时，两台水泵同时供水。当水池水位低于B点且高于C点时，由水泵M1单独供水。当水池水位低于A点且高于B点时，由水泵M2单独供水。当水池水位高于A点时，两台水泵都停止供水。试设计一个水泵控制电路。要求电路尽可能简单。M1ABCM24.484-510。首先根据所给问题列出真值表。其中有几种情况是不可能出现的，用约束项表示。ABC000001010011100101110111如果利用约束项化简如果不利用约束项化简M1M200A01BC000111100011A01BC000111100110011011M1M2M1BM1ABM2CABM1M2≥1M2ABCABCA(BC)M1&M2&=&1BACABC(a)用约束项化简(b)不用约束项化简4-4盛建伦：《数字逻辑与VHDL逻辑设计》习题解答习题4-5的逻辑图4-63-874HC138画出逻辑图。Y1ABCA(BC)Y2ACABY3(AB)(AC)Y4ABCABC解：先将逻辑函数变换成最小项之和的形式Y1ABCABACABCABCABCABCY2ABCABCABCABCYABACABCABCABCABC374HC138&&Y4YABCABCABCABC2m7m4m3m2Y3ABCABCABCABCm7m5m3m2Y4ABCABCm7m0ABCY0Y1S3Y2Y374HC138Y4Y5A2Y6A1Y7A0S1S2Y1&Y2&Y3令74HC138的A2=A，A1=B，A0=C，4-73-874HC138Y32≤某<7Y=某－2某<2,Y=1=7,Y=6211Y7S3Y6S2Y5S1Y4A2A1A074HC138&&Y2Y1Y024-510Y3Y2Y1Y0&盛建伦：《数字逻辑与VHDL逻辑设计》习题解答4-144.503874HC13881构成的电路。试分析①当数据C2C1C0=D2D1D0时，输出F=②当数据C2C1C0≠D2D1D0输出F=解：C2C1C0=D2D1D0F=0②C2C1C0≠D2D1D0F=1C2C1C0D2D1D04-153状态都能控制电灯由亮变灭或者由灭变亮。用数据选择器实现。1Y7Y6Y5Y474HC138Y3Y2Y1A2A1A0Y0C2C1C0S1S2S3D7D6D581择器D4D3YFD2D1D0A2A1A0D2D1D04.504-14解：用A、B、C3Z=0ABC=000时的状态Z=0。（比较容易得真值表，初始状态也很重要）真值表：逻辑函数表达式：ABC000001010011100101110111Z01101001ZABCABCABCABC4-11盛建伦：《数字逻辑与VHDL逻辑设计》习题解答C341AB址，CAB1A1A0D3D2D1D0即A1=A，A0=B，D0=D3=C，D1=D2=C4-16逻辑图41YZ/=1=0A、B/减的两个数。做加法运算时，S//SS=A+BS=A－BAB000001010011100101110111SCO0011100000101001逻辑函数不能化简，但是可以变换成异或表达式。S某ABAB某AB某AB(AB)某(AB)S=1CO&ABCOABAB=(某A)B按照变换后的逻辑函数画逻辑图。AB4-173-874HC1381的借位信号。解：全减器的功能是Si=Ai－Bi－Ci。首先根据所给问题列出真值表。真值表：逻辑函数：AiBiCiSiCOSAiBiCAiBCiABiCiABCiiiiiii4-12盛建伦：《数字逻辑与VHDL逻辑设计》习题解答0000010100111001011101110011110110000011COAiBiCiAiBiCiAiBiCiAiBiCi74HC138SiAiBiCiAiBiCiAiBiCiAiBiCim1m2m4m71247mmmm4-181COAiBiCiAiBiCiAiBiCiAiBiCim1m2m3m7m1m2m3m7AiBiCiY73SY6S2Y5S1Y4A2A1A074HC138&SiY3Y2Y1Y0&CO4CC14585D3D2D1D0>100110。解：从CC14585的一个端口输入数据D3D2D1D0，另一个端口输入1001。CC14585的扩展输入端IA>B和IA=B必须接高电平，IA1001逻辑图D0D1D2D31A0A1A2CC14585A3IABYABIABYABIABYABB0B1B2B3F4-19试根4.24er）A1、A0、W2W1、W0从N4.514.244-194-13盛建伦：《数字逻辑与VHDL逻辑设计》习题解答A1A0D000001010011100101110111DW3W2W1W000000001000000100000010000001000W3W2W1W0DeMU某A1A04.51解：表4.24的功能表可以简化为A1A0W3W2W1W000000D0100D0100D0011D000逻辑函数W0A1A0D逻辑图W3&W2&W1&W0&W1A1A0DW2A1A0DW3A1A0DA1A011D4-20试比较图4.52所示两个逻辑电路的功能。F1&101DCBAA0D0D1D2D3D4D5D6D7A181A3A2A1A0AF24-14BCDVHDL4.524-204.5281D6=D7=D，D1=0，D2=1，D5=D4=D3=D0=D，A2=A，A1=B，A0=C，所以，F2ABCD7ABCD6ABCD5ABCD4ABCD3ABC1ABCD0ABCDABCDABCDABCDABCDABCABCDABCDABCDABCDABCDABCDABCDABCDABCDF1m15m13m10m8m6m5m4m0ABCDABCDABCDABCDABCDABCDABCDABCDABCDABCDABCDABCDABCDABCDABCDABCD比较FI和F24-21用VHDL44进制代码。解：首先画出代码转换电路的系统框图，如根据所给问题列出真值表。G3G2G1G000000001001100100110011101010100B3B2B1B000000001001000110100010101100111G3B3代码转换电路… G0B04-15盛建伦：《数字逻辑与VHDL逻辑设计》习题解答1100110111111110101010111001100010001001101010111100110111101111根据系统框图写VHDL程序的Entity表写VHDLArchitecture。VHDL程序如下：--GraycodetoBinarycodelibraryieee;ueieee.td_logic_1164.all;entitygray2binaryiport(grayin:intd_logic_vector(3downto0);binaryout:outtd_logic_vector(3downto0));endgray2binary;architecturebehaveofgray2binaryibeginwithgrayinelectbinaryout<=\\\\\\\\\\\\\\\\endbehave;4-16盛建伦：《数字逻辑与VHDL逻辑设计》习题解答4-22用VHDL470~9A，b，C，d，E，F。47D3~D0号名，用Ya~Yga、b、c、d、efg7系统框图……列出代码转换逻辑的真值表。4.12D3D2D1D0YaYbYcYdYeYfYg0000000100100011010001010110011110001001101010111100110111101111根据系统框图设计VHDL程序的entity，用行为描述的方法，根据真值表设4-17YaYbYcYdYeYfYg代码转换电路D3D2D1D0…显示字符0123456789AbCdEF字形1111110011000011011011111001011001110110111011111111000011111111110011111011100111111001110011110110011111000111盛建伦：《数字逻辑与VHDL逻辑设计》习题解答计VHDL程序的architecture。libraryieee;ueieee.td_logic_1164.all;entitybcd2eg7iport(bcdin:intd_logic_vector(3downto0);egout:outtd_logic_vector(6downto0));endbcd2eg7;architecturebehavofbcd2eg7ibeginwithbcdinelectegout<=\--diplay\\\\\\\\--diplay\\\--diplay\\--diplay\\--diplay\\--diplay\\--diplay\\--diplay\\--diplay\\endbehave;用VHDL7位的ASCII70~9，字母A，b，C，d，E，F，H，L，o，P，U，等。解：ASCII7Yg0盛建伦：《数字逻辑与VHDL逻辑设计》习题解答123456789AbCdEFHLoPU00000000011111111111111111111010100001001111111110000000001100000001100000011100000111100000111011010110011000110010010010101010110101000101011011111101011000101111001111001001001110111111111010010101011011010011110011010100010101111111111100011101111101111011011111011110111101104-23用VHDL设计一个16位全加器。解：4-24用VHDL8用VHDL4-19盛建伦：《数字逻辑与VHDL逻辑设计》习题解答--4-Bitcarry-look-aheadFullAdderlibraryieee;ueieee.td_logic_1164.all;entityFULL_ADDER1iport(A,B:inbit_vector(3downto0);Cin:inbit;S:outbit_vector(3downto0);Cout:outBIT);endFULL_ADDER1;--architectureFULL_ADDERpofFULL_ADDER1iignalA,B,S:bit_vector(3downto0);ignalCin,Cout:bit;ignalC:bit_vector(3downto0);ignalT:bit_vector(3downto0);ignalG:bit_vector(3downto0);beginA<=A;B<=B;Cin<=Cin;T(0)<=A(0orB(0);--P0G(0)<=A(0)andB(0);--G0T(1)<=A(1)orB(1);--P1G(1)<=A(