集成电路ESD防护课件3

集成电路ESD防护课件3第一页，共44页。课程提纲集成电路封装PackagingCMOS电路的ESD保护ESD介绍集成电路的ESD保护ESD保护在高速及RF电路的应用I/OBuffer设计2第二页，共44页。集成电路的ESD保护3第三页，共44页。ESD对电路的影响4第四页，共44页。TheseprotectioncircuitsshouldbeabletodischargetheESDenergyHaveminimalimpactonnormalcircuitbehavior对ESD保护器件的期望5第五页，共44页。ESD的外部特性triggeringvoltage(Vt1)，holdingvoltage(Vh)ahigh-ohmicregimechangestoalow-ohmicbehaviorbeyondthebreakdownvoltage(Vbd)ortheholdingvoltage(Vh)Postsnapback“on”resistance(Ron)6第六页，共44页。对ESD保护器件的期望Verylowon-resistanceTriggeringvoltageshouldbeabovetheworstcaseoperatingsupplyvoltage(VDD+10%)Almostinstantaneousturn-ontimeVeryhighenergyhandlingcapabilityOnlytriggerduringESDevents,notduringnormaloperationVerylowparasiticstominimizeperformancedegradationofI/OcircuitConsumessmallarea7第七页，共44页。放电模式ZappingModeESDdischargingpathfromI/OpadstobothVSSandVDDOnemoreESDprotectionisbetweenVDDandVSSlines(DSmode)ESDfailurethresholdofapinisdefinedasthelowestESD-sustainingvoltageofthefour-modeESDstresses8第八页，共44页。InverterBuffer9第九页，共44页。InverterBufferZappingMode10第十页，共44页。BufferZappingNSmodeDiodeisforwardbiased=>theparasiticresistanceisverysmall=>itcancarryalargecurrentNoadditionalprotectionisneeded11第十一页，共44页。BufferZappingPDmodeDiodeisforwardbiased=>theparasiticresistanceisverysmall=>itcancarryalargecurrentNoadditionalprotectionisneeded12第十二页，共44页。BufferZappingPSmodeDiodeisreversebiased=>theparasiticresistanceisverylarge=>itcannotcarryalargecurrentAdditionalProtectionisneeded13第十三页，共44页。BufferZappingNDmodeDiodeisreversebiased=>theparasiticresistanceisverylarge=>itcannotcarryalargecurrentAdditionalProtectionisneeded14第十四页，共44页。PSmodeProtection:Method1AddaPSprotectioncircuitbetweenpadandVSS.CarryalargecurrentunderESDconditionsMinimumimpactonnormalbehaviorofthecircuit15第十五页，共44页。PSmodeProtection:Method2TransfertheESDchargetotheVDDnodeusingtheforward-biasedp+-diodeThen,dischargetoVSSthroughESDclamp16第十六页，共44页。InCMOS,diode,MOSFETandSiliconControlledRectifier(SCR)arethemostcommondevicesinESDprotectionESDDevices17第十七页，共44页。ESDDevicesNON-SNAPBACKDEVICESthecurrentstartstoincreaserapidlywhilethevoltageacrossthemremainsconstantp-njunctiondiode,zenerdiodeSNAPBACKDEVICESAfterbreakdown,duetoaninternalpositivefeedbackmechanism,thevoltageacrossthedevicedropsandthedevicemovesfrombreakdownregiontotheholdingregion.GGNMOS,SCR18第十八页，共44页。P-NJunctionDiode20–50mA/um19第十九页，共44页。PNJunctionDioden+diode:AnodeconnectedtoGND,soisforNSmodeprotectionp+forPDmodeprotection20第二十页，共44页。GGNMOSESDDeviceGGNMOS(GateGroundedNMOS)forPSmodepnjunctionreverse-biaseduntilavalanchebreakdownTheholesdrifttowardsthesubstratecontact(Isub)untilVbase-emitter≈0.7V,theparasiticbipolarturnson.Vt1isfirstbreakdownvoltageSecondbreakdownregioniswhenthermaldamageisoccurring,It2ismaximumallowedcurrent.21第二十一页，共44页。GGNMOSThedrainisconnectedtotheI/Opad.Fornormaloperating,theNMOStransistoris“off”ForESDwhenthepadvoltageexceedsVt1,thetransistorgoesintosnapbackmodeandESDcurrentisdischargedthroughGGNMOS.ThemaximumESDcurrentisusuallyintheorderof3-10mA/μm.22第二十二页，共44页。GGNMOSWidthVHBM=(RON(ESD)+RHBM)It2

RON(ESD)<<RHBM=1.5

kΩ⇒It2=1.33A⇒W=1333/4=333μmTheprotectionlevel2–4kV23第二十三页，共44页。SCR:SiliconControlledRectrifierThep+diffusioninthen-wellformstheanodeThen+diffusioninthep-subformsthecathodeThen-wellisconnectedtotheanode,andthep-subisconnectedtothecathodeTheanodeisconnectedtotheI/Opad,andthecathodeisconnectedtotheground,forPSmode24第二十四页，共44页。Theanodevoltageincreasesuntilthewell-substratejunctiongoesintoavalanchebreakdown.ThegeneratedcurrentcanturnonthenpntransistoranditscurrentgeneratesavoltagedropacrossRn-wellandturnsonthepnptransistor.ThepnpcurrentcreatesavoltagedropacrossRp-subandkeepsthenpntransistoron.NoneedfortheanodetoprovidethebiasofthenpntransistorandtheanodevoltageisreducedtoVh.SCR:SiliconControlledRectrifier25第二十五页，共44页。Comparingdiode,GGNMOSandSCRSCRandreversebiaseddiodehaveveryhighfirstbreakdownvoltagesForwardbiaseddiodehasthelowestbreakdownvoltage26第二十六页，共44页。栅极氧化层击穿趋势27第二十七页，共44页。HowtoreducethetriggeringvoltageofGGNMOSandSCRGatecouplingtechniqueAsmallvoltagetothegatelowersthefirstbreakdownvoltageofanNMOStransistorDuetothecurrentgeneratedinthechannel,whichtriggerstheparasiticbipolartransistor28第二十八页，共44页。GateCouplingTechnique

29第二十九页，共44页。HowtoreducethetriggeringvoltageofGGNMOSandSCRSubstratecouplingtechniqueAsmallvoltagetothesubstratelowersthefirstbreakdownvoltageofanNMOStransistorDuetotheincreasedbasevoltageoftheparasiticbipolartransistor30第三十页，共44页。SubstrateCouplingTechnique

31第三十一页，共44页。PSmodeProtection:Method1AddaPSprotectioncircuitbetweenpadandVSS.CarryalargecurrentunderESDconditionsMinimumimpactonnormalbehaviorofthecircuit32第三十二页，共44页。PSmodeProtection:Method2TransfertheESDchargetotheVDDnodeusingtheforward-biasedp+-diodeThen,dischargetoVSSthroughESDclamp33第三十三页，共44页。Inverter-BasedESDClampSuddenincreaseinVDDnodeistransferredtonode1Passingthrough4inverters,thevoltageofnode5increasesTurnsonthetransistorM0Canbesimulatedbycircuitsimulators,e.g.CadenceorADSM0carriestheESDcurrentwithoutgoingintobreakdownregion34第三十四页，共44页。Inverter-BasedClampThepeakESDcurrentisfewamperesduringanHBMstress=>M0shouldbeuptoafewmillimeterswide4invertersareusedtodrivethebigM0ThetriggercircuitofsimpleRCdistinguishesESDeventfrompower-upeventThepower-upofanIChasarisetimeinthemillisecondrangeTherisetimeofanESDeventisbetween100psand60nsandlastsforlessthan1μsAsimpleRCnetworkwithtimeconstantof1μscandistinguishthesetwoeventsItrequiresahugeon-chipresistorandcapacitor35第三十五页，共44页。OnlyoneclampisrequiredforthewholechipandtherestofthepadsareconnectedtoVDDandVSSthroughdiodesComparedtothetotalareaofachip,theareaoftheclampisnegligibleTheparas