基于dsp-builder的fir滤波器设计与仿真教学课件

基于dspbuilder的fir滤波器设计与仿真51、山气日夕佳，飞鸟相与还。52、木欣欣以向荣，泉涓涓而始流。53、富贵非吾愿，帝乡不可期。54、雄发指危冠，猛气冲长缨。55、土地平旷，屋舍俨然，有良田美池桑竹之属，阡陌交通，鸡犬相闻。基于dspbuilder的fir滤波器设计与仿真基于dspbuilder的fir滤波器设计与仿真51、山气日夕佳，飞鸟相与还。52、木欣欣以向荣，泉涓涓而始流。53、富贵非吾愿，帝乡不可期。54、雄发指危冠，猛气冲长缨。55、土地平旷，屋舍俨然，有良田美池桑竹之属，阡陌交通，鸡犬相闻。DesignforthefirfilterbasedondspbuilderDspbuilderprofileandbasicdesignprocessFirdesignprocessandsomethingneedtopayattentionDspbuilderprofiledspbuilderisasystem-level(oralgorithm-level)designtools,itisonthetopofmultiplesoftware,itconnectssystemlevel(algorithmsimulationmodeling)andRTL-level(hardware)twodesigntoolstogetherandplacesthemintheMatlab/simulinkgraphicdesignplatform，theQuartusIIastheunderlyingdesigntoolsissetbackground，toplaythegreatestadvantageofvarietytools.FirdesignprocessThemostbasicfirfiltercanbeexpressedas:Inwhichx(n)istheinputsamplesequence,h(n)isthefiltercoefficient,Listheorderofthefilter,y(n)isthefilter'soutputsequence.FirdesignprocessForthefourthorderfirfiltercanbeexpressedasy(n)=Cq[h(0)x(n)+h(1)x(n-1)+h(2)x(n-2)+h(3)x(n-3)+h(4)x(n-4)]Cqisquantizationfactor.ForthedirectItypefirfiltercanbecascaded,sowedesignafourthorderFirfilterfirst,thengeneratethe16orderfirfilterwewantbycascading.FirdesignprocessCreatingtheFIRModel

1.StarttheMATLABsoftware.2.OntheFilemenu,pointtoNewandclickModeltocreateanewmodelwindow.3.ClickSaveontheFilemenuinthenewmodelwindow.CreatingtheFIRModelOpensimulinkLibraryBrowserbyenteringsimulinkincommandwindow.youcanalsoopensimulinkLibraryBrowserbyusingthetoolbaricon.AddtheDspbuilderBlockaddtheDspbuilderBlockthatyouneedintoyourmodelanddouble-clicktheblockinyourmodeltosetthebolckparameters.(NOTE:inordertogenerateVHDLyoumustusetheblockinDspbuilderBlock)Connecteveryblockinthemodelconnecteveryblockinthemodelasshownabove.

(NOTE：asthisblockisusedassubsysterm,youneeduseAltbusBlockastheinputBlock.)Createsubsystermselecteveryblockandclicktherightmousebuttonandclickcreatesubsystermtocreatesubsystermandrenametheinputblock.RenametheinputblockofthesubsystermCreatesubsystermandrenametheinputblockinordertocreateVHDL,youalsoneedtoSetthesubsystermblock:selectthesubsystermblockandclickEdit-MaskSubsysterm-DocumentationandsetMasktypeasSubSystermAlteraBlockSetBuild16-orderFirfilter

16-orderfirfilterisshownbelowGeneratetheFirfilterparameteruseFDATooltogeneratethefirfilterparameter:enterFDAToolintheMatlabcommandwindowtoopenitandsettheparameterofthefiltergeneratethefirfilterparameteritissignedfractionalthatFDAToolcalculate,inordertogeneratesignedintegerthatneededinfirfiltermodlewhtchisbuildedinDspBuilder,signedinteger,Signedfractionneedtoquantifyandnormalize.clicktoquantify.generatethefirfilterparameterExportfiltercoefficientsandconvertthedataintointeger.clickfile-exporttoexportthem.generatethefirfilterparameterentercoeff=round(Num*2^9)intheMatlabcommandwindowtoviewtheparameterexported.addsinwaveblock（sin1=7.8Khzsin2=125Khz）AclockblockisrequiredtosetaSimulinksampletimethatmatchesthesampletimespecifiedontheSineWaveandIncrementDecrement.addsinwaveandclockblockAddthescopeblockaddthescopeblocktoviewthewave.thefinalmodelisshownbelow.

SimulateYourModelinSimulink

ClickConfigurationParametersontheSimulationmenutodisplaytheConfigurationParametersdialogboxandselecttheSolverpageViewthewavethefirstoneistheresultoftwosinewaveoverlay.ThesecondisthefilteredwaveformThethirdisthelow-frequencysinewavebeforefiltered.TocreateandcompileaQuartusIIprojectforyourDSPBuilderdesign,andtoprogramthedesignontoanAlteraFPGA,youneedtoaddtheSignalCompilerblock.CompilingtheDesignPerformRTLsimulationToperformRTLsimulationwiththeModelSimsoftware,youneedtoaddaTestBenchblock.ClickGenerateHDLtogenerateaVDHL-basedtestbenchfromyourmodel.ClickRunSimulinktogenerateSimulinksimulationresultsforthetestbench.ClickRunModelSimtoloadthedesigninModelSim.performRTLsimulationselectingthesignalnameintheWavewindowandright-clickingon

Format-Anolog(automatic)ClickZoomFullontherightbuttonpop-upmenuintheModelSimWavewindow.ThesimulationresultsdisplayasananalogwaveformsimilartothatshowninTimingsimulationinQuartusIIopentheQuartusIIprojectcreatedbytheSignalCompilerblockinMatlab/simulinkselectfir1129.mdlandsetitasthetop-levelEntitytosimulinkselectfir1129_GN.vhdinDesignUnitsandcreatesymbolfile