数字逻辑设计-标准加译码器剖析课件

classexersise

F=A,B,C,D(1,3,4,5,6,7,12,14,15)Usetheduality,findaminimalproduct-of-sumsexpression(和之积)forthefollowinglogicfunctionF.

1、先将F转为或与表达式，

F=∏A,B,C,D（0，2，8，9，10，11，13）2、直接卡诺图圈零化简。

F=（B+D）·（A’+B）·（A’+C+D’）F=A,B,C,D(1,3,4,5,6,7,12,14,15)CDAB00

01

11

1000011110000000011、先将F转为或与表达式，得F=∏A,B,C,D（0，2，8，9，10，11，13）2、求F的对偶式。

FD=A,B,C,D(2,4,5,6,7,13,15)3、FD的最简与或式为：

FD=BD+A’B+A’CD’4、FD的对偶式（FD）D=F。

F=（B+D）·（A’+B）·（A’+C+D’）CDAB00

01

11

10000111101111111F=A,B,C,D(1,3,4,5,6,7,12,14,15)21、先将F转为或与表达式，得F=∏A,B,C,D（0，2，8，9，10，11，13）2、求F的反演式。

F’=A,B,C,D(0，2,8,9,10,11,13)3、F’的最简与或式为：

F’=B’D’+AB’+AC’D4、F’的反演式（F’）‘=F。

F=（B+D）·（A’+B）·（A’+C+D’）CDAB00

01

11

10000111101111111F=A,B,C,D(1,3,4,5,6,7,12,14,15)3

Chapter6

CombinationalLogicDesignPractices

组合逻辑设计实践Wewillstuday…….6.16.26.46.56.66.76.86.96.10CombinationalLogicDesign

6.1DocumentationStandards

Documentation(文档)：(P343)1、ciruitspecification：线路的详细说明。2、blockdiagram：方框图.系统的主要功能模块及其基本互连的非正式图示说明。3、schematicdiagram：原理图.4.billofmaterials(BOM)：材料清单。5、timingdiagram：定时图(波形图)，输入、输出等波形的时间关系，包括其延时.CombinationalLogicDesign6.programmablelogicdevice(PLD)：可编程逻辑器件。

field-programmablegatearray(FPGA)：现场可编程门阵列。

application-specificintegratedcircuit(ASIC)：专用集成电路。7、circuitdescription：电路描述.8.bus：总线.在框图中总线用双线或黑线表示。总线的位数用斜杠加数字说明或总线名加方括号(例inbus[31..0]，inbus[31:0])。6.1.1blockdiagram(方框图)：(P345)

显示系统的输入、输出、功能模块内部数据通路和重要控制信号.

BUS:(总线)(P344)busisacollectionoftwoormorerelatedsignallines.Inablockdiagram,busesaredrawnwithadoubleorheavyline.sizedenotedinthebusnameINBUS[31..0]orINBUS[31:0]).

blockdiagramTheflowofcontrolanddata(控制流和数据流)inablockdiagramshouldbeclearlyindicated.

schematicdiagram原理图6.1.2GateSymbols

逻辑门的符号Asmallcircle,calledaninversionbubble6.1.3SignalNamesandActiveLevels

(信号名与有效电平)(P347)Eachsignalnameshouldhaveanactivelevel

(有效电平)associatedwithit.Asignalis

activehigh(高电平有效)ifitperformsthenamedactionordenotesthenamedconditionwhenitisHIGHor1.

Asignalisactivelow(低电平有效)ifitperformsthenamedactionordenotesthenamedconditionwhenitisLOWor0.Asserted(有效),deassertedornagated(无效).6.1.3SignalNamesandActiveLevelsActivelowActivehighREADY-READY+ERROR.LERROR.HADDR15(L)ADDR15(H)RESET*RESETENABLE~ENABLE~GOGO/RECEIVERECEIVETRANSMIT_LTRANSMIT

Distinguish(区别)(P348)signalnamesexpressionsequationsREADY’READY,READY-LREADY-L=READY’

6.1.4ActiveLevelsforPins

引脚的有效电平(P349)(a)ANDgate(74X08)(b)NANDgate(74X00)(c)NORgate(74X02)(d)ORgate(74X32)ActiveLevelsforPins6.1.5Bubble-to-BubbleLogicDesign

“圈到圈”的逻辑设计(P351)6.1.6DrawingLayout(布局图)Acompleteschematicpageshouldbedrawnwithsysteminputsontheleftandoutputsontheright,andthegeneralflowofsignalsshouldbefromlefttoright.

手工画图计算机绘图6.1.6DrawingLayout(布局图)1.Amultipleschematicusuallyhasa“flat”structure(平面结构).2.Muchlikeprograms,schematicscanalsobeconstructedhierarchically,the“top-level”schematic."层次"展开(自顶向下)6.1.9AdditionalSchematicInformationICtypestype(IC型号)referencedesignators(参考标志符)pinnumbers(引脚).

(P360-361)anopen-drainoropen-collectoroutput.

(漏极开路或集电极开路输出)hysteresis.(滞后)6.2CircuitTiming(电路定时)“Timingiseverything”—ininvesting,incomedy,andyes,indigitaldesign.6.2.1TimingDiagrams(定时图)(P363)causality

6.2.2PropagationDelaythepropagationdelay

ofasignalpathasthetimethatittakesforachangeattheinputofthepathtoproduceachangeattheoutputofthepath.fromLOWtoHIGH(tpLH)

fromHIGHtoLOW(tpHL)

6.2.3TimingSpecifications

定时规格说明

Maximum.最大延迟Typical典型延迟Minimum最小延迟worst-casedelay最坏情况延迟Tsetup建立时间Thold保持时间SETUPTIMEANDHOLDTIMESETUPTIME：是指在时钟沿到来之前数据从不稳定到稳定所需的时间，如果建立的时间不满足要求那么数据将不能在这个时钟上升沿被稳定的打入触发器；

SETUPTIMEANDHOLDTIMEHOLDTIME：HOLDTIME（Th：holdtime）

是指数据稳定后保持的时间，如果保持时间不满足要求那么数据同样也不能被稳定的打入触发器。

StandardMSIfunctions

中规模集成电路Decoder译码器Encoder编码器Multiplexer多路复用器paritycircuit奇偶校验Comparator比较器Addersubtractor加法器\减法器使能输入编码输出编码映射6.4decoder

译码器6.4decoder(P384)

Adecoderisamultiple-input(多输入),multiple-output(多输出)logiccircuitthatconvertscodedinputsintocodedoutputs,wheretheinputandoutputcodesaredifferent.Theinputcodegenerallyhasfewerbitsthantheoutputcode,andthereisaone-to-onemapping(一对一映射)frominputcodewordsintooutputcodewords.Inaone-to-onemapping,eachinputcodewordproducesadifferentoutputcodeword.Themostcommonlyusedinputcodeisann-bitbinarycode,whereann-bitwordrepresentsoneof2ndifferentcodedvalues.

Themostcommonlyusedoutputcodeisa1-out-of-mcode,whichcontainsmbits,whereonebitisassertedatanytime.使能输入编码输出编码映射6.4Decoder（译码器）P3846.4.1BinaryDecoder(二进制译码器)n-to-2n

decoderThemostcommondecodercircuitisann-to-2n

decoderorbinarydecoder.Suchadecoderhasann-bitbinaryinputcodeanda1-out-of-2n

outputcode.

6.4.1BinaryDecoder(二进制译码器)n-to-2n

decoder2-to-4decoderY0Y1Y2Y3I0I1EN使能输入编码输出编码映射n位二进制码2n中取1码

0XX00001000001101001011001001111000inputsENI1I0outputsY3Y2Y1Y0

Thetruthtablefora2-to-4binarydecoder6.4.1BinaryDecoder(二进制译码器)n-to-2n

decoder2-to-4decoderY0Y1Y2Y3I0I1ENYi=

EN

·mi使能输入编码输出编码映射n位二进制码2n中取1码0

XX

00001000001101001011001001111000inputsENI1I0outputsY3Y2Y1Y0

Thetruthtablefora2-to-4binarydecoder当输入使能端(EN)有效时Yi=miDon’tcarenotation(无关符号)使能输入编码输出编码映射n位二进制码2n中取1码

0XX00001000001101001011001001111000inputsENI1I0outputsY3Y2Y1Y0

Thetruthtablefora2-to-4binarydecoderDesignit!Y3=EN.I1.I0Y2=EN.I1.I0’Y1=EN.I1’.I0Y0=EN.I1’.I0’2-to-4decoder

logicdiagram.

Example1:Positiondecodingfora3-bitmechanicalencodingdisk

Example2:

WhatistheBCDdecoder’sstructrure?I3I2I1I0ENY0Y9THEIMPORTANCEOF

74-SERIESLOGIC(P342)we’lllookatcommonlyused74-seriesICsthatperformwellstructuredlogicfunctions.Thesepartsareimportantbuildingblocksinadigitaldesigner’stoolbox.EvenwhenyoudesignforPLDs,FPGAs,orASICs,understanding74-seriesMSIfunctionsisimportant.InPLD-baseddesign,standardMSIfunctionscanbeusedasastartingpointfordevelopinglogicequationsformorespecializedfunctions.AndinFPGAandASICdesign,thebasicbuildingblocks(or“standardcells”or“macros”)providedbytheFPGAorASICmanufacturermayactuallybedefinedas74-seriesMSIfunctions,eventotheextentofhavingsimilardescriptivenumbers.6.4.2LogicSymbolsforLarger-ScaleElementsWithrespecttoactivelevels,it’simportanttouseaconsistentconventiontonamingtheinternalsignalsandexternalpins.G1G2A-LG2B-LY0-LBCY7-LA5.4.4The74x1383-to-8DecoderThe74x138isacommerciallyavailableMSI3-to-8decoder.

the74x138hasactive-lowoutputs.(P387)m5M5Logicdiagramforthe74x138低位高位Yi=EN·miG1G2A_LG2B_LENYi_L=Yi’=(EN·mi)’EN=G1·G2A·G2B=G1·G2A_L’·G2B_L’Y0_LY1_LY7_LY2_LY3_LY4_LY5_LY6_LENm574x139Truthtable?

The74x139Dual2-to-4DecoderWhatistheequationfortheexternaloutputsignal1Y0-L?74x139TruthtableThe74x139Dual2-to-4Decoder1Y0-L=1G’·(1B’·1A’)’74x139ENF=(X,Y,Z)(0,3,6,7)=(X,Y,Z)(1,2,4,5)Fordecorder：Yi=EN·mi

Ifenabled，Yi=miForActivelow：Yi_L=Yi’so:Yi_L=mi’=MiABCG1G2AG2BY0Y1Y2Y3Y4Y5Y6Y774x138UseDecoderandlogicgatestoimplementlogicfunctionUseDecoderandlogicgatestoimplementlogicfunctionZYXABCG1G2AG2BY0Y1Y2Y3Y4Y5Y6Y774x138F+5VF=(X,Y,Z)(0,3,6,7)Yi=miActiveLow：Yi_L=Yi’=mi’UseDecoderandlogicgatestoimplementlogicfunctionZYXABCG1G2AG2BY0Y1Y2Y3Y4Y5Y6Y774x138+5VFF=(X,Y,Z)(0,3,6,7)=M1·M2·M4·M5=m1’

·m2’

·m4’

·m5’F=(X,Y,Z)(1,2,4,5)ZYXABCG1G2AG2BY0Y1Y2Y3Y4Y5Y6Y774x138+5VF74x139Truthtable?Example3:The74x139Dual2-to-4DecoderWhatistheequationfortheexternaloutputsignal1Y0-L?74x139Truthtable

Example3:The74x139Dual2-to-4Decoder1Y0-L=1G’·(1B’·1A’)’74x139ENClassexercise

realizethelogicfunctionFwith

3-to-8decoderandlogicgates.1.F=(X,Y,Z)(1,2,4,5)2.G=(W,X,Y,Z)(0,6,8,10)ABCG1G2AG2BY0Y1Y2Y3Y4Y5Y6Y774x138Howtodesignthe4-to-16decoder?6.4.4CascadingBinaryDecoders(级联二进制译码器）(P390)N0N1N2N3EN_L+5VD0_LD7_LD8_LD15_LThinking：

16outputs!

74x138？Y0Y7ABCG1G2AG2BY0Y7ABCG1G2AG2BU1U2onlyonechipisenabled。

4inputs，WhichoneisusedasCS(ChipSelection)Example4:

designthe4-to-16decoderConsider:Howtomakea5-to-32Decoderwith3-to-8Decoder?

(思考：用74x138设计5-32译码器)Consider:Howtomakea5-to-32Decoderwith3-to-8Decoder?

(思考：用74x138设计5-32译码器)Controlinputsofthreelow-orderbitsofa5-bitcodeword(5个输入的低3位控制输入)Controlchipsoftwohigh-orderbitsofa5-bitcodeword(5个输入的高2位控制片选)Example5:

designthe5-to-32decoderN4N3N2N1N0DEC0-7DEC8-15DEC16-23DEC24-310001101174x139(P391)BCDDecoder(二－十进制译码器)Inputs:4-bitBCDcodeOutputs:1-out-of10CodeY0Y9I0I1I2I3多余的6个状态如何处理？输出均无效：拒绝“翻译”作为任意项处理

——电路内部结构简单二-十进制译码器00000001001000110100010101100111100010011010101111001101111011110111111111101111111111011111111110111111111101111111111011111111110111111111101111111111011111111110111111111111111111111111111111111111111111111111111111111111I3

I2

I1

I00123456789Y0_L

Y9_L伪码任意项6.4.8Seven-SegmentDecoders

(七段显示译码器)(P408)abcdefgdp公共阴极abcdefgdpNormallyuse(常用的有)：Light-EmittingDiodes（LED,半导体数码管）Liquid-CrystalDisplay（LCD,液晶数码管）abcdefgdp公共阳极Inputcode:4-bitBCD[输入信号：BCD码（用A3A2A1A0表示）]OutputCode:Seven-SegmentCode[输出：七段码（的驱动信号）a~g]1表示亮(On)，0表示灭(Off)abcdefg111111011011010011111Seven-SegmentDecoders

(七段显示译码器)七段显示译码器的真值表00000001001000110100010101100111100010011010101111001101111011111111110011000011011011111001011001110110110011111111000011111111110011000110100110010100011100101100011110000000A3

A2

A1

A0abcdefg01234567891011121314156.5Encoder

ENCODER

(P408)Ifthedevice’soutputcodehasfewerbitsthantheinputcode,thedeviceisusuallycalledanencoder.

Probablythesimplestencodertobuildisa2n-to-norbinaryencoder.

encoder（编码器）Binaryencoder

Y0Y1Y2I0I1I71000000000001000000001001000000100001000001100001000100000001001010000001011000000001111I0I1I2I3I4I5I6I7Y2Y1Y0Thetruthtablefora8-to-3binarydecoder2ninputsnoutputsencoder（编码器）Y0=I1+I3+I5+I7Y1=I2+I3+I6+I7Y2=I4+I5+I6+I7前提：任何时刻只有一个输入端有效。1000000000001000000001001000000100001000001100001000