数字逻辑课件6 2译码器

class

exersiseUse

the

duality,find

a

minimal

product-of-sumsexpression(和之积)for

thefollowing

logic

function

F.F

=

A,B,C,D

(

1,

3,

4,

5,

6,

7,

12,

14,

15

)static-1

hazard

static-0

hazard静态-1型冒险主要存在于

“与－或”电路中AFA静态-0型冒险FSteady

–state

is

1.F

=

(A·A’)’

=

A+A’Steady

–state

is

0.F

=

(A+A’)’

=

A·A’主要存在于

“或－与”电路中Review

of

LastClass静态冒险(P225)Review

of

LastClass6.1 Documentation

Standard文档标准

Signal

Name

and

Active

Level信号名和有效电平

Bubble-to-BubbleLogicDesign“圈到圈”逻辑设计Review

of

LastClass6.2

Circuit

Timing

电路定时

Propagation Delay

传播延迟

Timing

Analysis

定时图、

Timing Diagram

定时分析Standard

MSI

functions中规模集成电路Decoder

译码器Encoder

编码器Multiplexer

多路复用器

parity

circuit

奇偶校验

Comparator

比较器Adder

subtractor

加法器\减法器使能输入编码

输出编码6.4

decoder译码器6.4 decoder

(P384)

A

decoder

is

a

multiple-input(多输入),multiple-output(多输出)logic

circuit

thatconverts

coded

inputs

into

coded

outputs,where

the

input

and

output

codes

aredifferent.The

input

code

generally

hasfewer

bits

than

the

output

code,and

thereis

a

one-to-onemapping(一对一映射)frominput

code

words

into

output

code

words.In

a

one-to-one

mapping,each

inputcodeword

produces

a

different

output

codeword.使能The

most

commonly

used

input

code

is

ann-bit

binary

code,

where

an

n-bit

wordrepresents

one

of

2n

different

coded

values

.

The

most

commonly

used

outputcode

isa1-out-of-m

code,

which

containsm

bits,

where

one

bit

is

asserted

at

anytime.输入编码

输出编码6.4

Decoder（译码器）P3846.4.1Binary

Decoder

(二进制译码器)n-to-

2n

decoder

The

most

common

decoder

circuit

isan

n-to-2n

decoder

or

binary

decoder.Such

a

decoder

has

an

n-bit

binary

inputcode

and

a

1-out-of-2n

output

code.6.4.1Binary

Decoder

(二进制译码器)n-to-

2n

decoder2-to-4decoderY0Y1Y2Y3I0I1ENn位二进制码输入编码

输出编码使能2n中取1码inputsEN

I1I0Y3outputsY2

Y1Y00XX00001000001101001011001001111000The

truth

table

fora

2-to-4

binary

decoderYi

=

EN

·

mi当输入使能端(EN)有效时Yi

=

mi6.4.1Binary

Decoder

(二进制译码器)n-to-

2n

decoder2-to-4decoderY0Y1Y2Y3I0I1ENn位二进制码输入编码

输出编码使能2n中取1码0

X

X

0

0

0

01

0

0

0

0

0

11

0

1

0

0

1

01

1

0

0

1

0

01

1

1

1

0

0

0The

truth

table

fora

2-to-4

binary

decoderinputs

outputsEN

I1

I0

Y3

Y2

Y1

Y0Yi

=

EN

·

mi当输入使能端(EN)有效时Yi

=

miDon’t

carenotation(无关符号)2-to-4 decoder

logic

diagram.Example

1 :Position

encoding

fora3-bit

mechanical

encoding

diskExample

2:Whatis the

BCD

decoder’s

structrure?I3I2I1I0ENY0Y9THE

IMPORTANCE

OF74-SERIES

LOGIC

(P342)we’ll

look

at

commonly

used

74-series

ICs

thatperform

well

structured

logic

functions.

These

partsare

important

building

blocks

in

a

digital

designer’stoolbox

.Even

when

you

design

for

PLDs,

FPGAs,

or

ASICs,understanding

74-series

MSI

functions

is

important.In

PLD-based

design,

standard

MSI

functions

can

beused

as

a

starting

point

for

developing

logicequations

for

more

specialized

functions.

And

inFPGA

and

ASIC

design,

the

basic

building

blocks

(or“standard

cells”

or

“macros”)

provided

by

the

FPGAor

ASIC

manufacturer

may

actually

be

defined

as

74-series

MSI

functions,

even

to

the

extent

of

havingsimilar

descriptive

numbers.6.4.2

Logic

Symbols

for

Larger-Scale

ElementsWith

respect

toactive

levels,

it’s

important

touse

a

consistentconvention

tonaming

theinternal

signalsand

external

pins.G1G2A-LG2B-LY0-LCY7-LAB5.4.4

The

74x138

3-to-8

Decoder

The

74x138

is

a

commercially

availableMSI

3-to-8decoder. the

74x138

hasactive-low

outputs.(P387)Logic

diagramfor

the

74x138Function

table(功能表)I1I0Y0Y1Y2Y3LLLHHHLHHLHHHLHHLHHHHHHL低位高位G1G2A_LG2B_LENEN

=

G1

·

G2A

·

G2B=

G1

·

G2A_L’

·

G2B_L’Yi

=

EN

·

miYi_L

=

Yi’

=

(

EN

·

mi

)’Y0_LY1_LY2_LY3_LY4_LY5_LY6_LY7_LEN74x139Truth

table?Example

3:The

74x139

Dual

2-to-4

DecoderWhat

is

the

equationfor

the

externaloutput

signal

1Y0-L?74x139Truth

tableExample

3:The

74x139

Dual

2-to-4

Decoder1Y0-L=1G’

·(1B’

·1A’)’74x139ENHowtodesignthe4-to-16decoder?6.4.4 Cascading

Binary

Decoders(级联二进制译码器）(P390)N0N1N2N3EN_L+5VD7_LD8_LD15_LY0

D0_LY7G1G2AG2BABCY0Y7G1G2AG2BABCU1U2思路：16个输出需要

片74x138？任何时刻只有一片在工作。4个输入中，哪些位控制片选哪些位控制输入Example

4:design

the

4-to-16

decoderConsider:

How

to

make

a

5-to-32

Decoder

with3-to-8

Decoder?(思考：用74x138设计5-32

译码器)(32个输出需要多少片74x138？)(控制任何时刻只有一片工作)——(利用使能端)Consider:

How

to

make

a

5-to-32

Decoderwith3-to-8Decoder?(思考：用74x138设计5-32

译码器)Control

inputs

of

three

low-order

bits

of

a

5-bitcode

word(5个输入的低3位控制输入)Control

chips

of

two

high-order

bits

of

a

5-bitcode

word(5个输入的高2位控制片选)Example

5:design

the

5-to-32

decoderN4N3N2N1N0DEC0-7DEC8-15DEC16-23

DEC24-310001101174x139(P391)补充：用译码器和逻辑门实现逻辑函数当使能端有效时，Yi=mi对低电平有效输出：Yi_L=Yi’当使能端有效时，Yi_L=mi’=MiF

=

(X,Y,Z)

(0,3,6,7)=

(X,Y,Z)

(1,2,4,5)G1G2AG2BABCY0Y1Y2Y3Y4Y5Y6Y7对于二进制译码器：Yi=EN

·

mi74x138用译码器和逻辑门实现逻辑函数G1G2AG2BZ

AY

BX

CY0Y1Y2Y3Y4Y5Y6Y774x138F+5VF

=

(X,Y,Z)

(0,3,6,7)当使能端有效时Yi

=

mi用译码器和逻辑门实现逻辑函数G1G2AG2BZ

AY

BX

CY0Y1Y2Y3Y4Y5Y6Y774x138+5VFF

=

(X,Y,Z)

(0,3,6,7)=

M1

·

M2

·

M4

·

M5=

m1’

·

m2’

·

m4’

·

m5’F

=

(X,Y,Z)

(

1,

2,

4,

5

)G1G2AG2BZ

AY

BX

CY0Y1Y2Y3Y4Y5Y6Y774x138+5VFBCD

Decoder(二－十进制译码器)Inputs

:

4-bit

BCD

codeOutputs

:1-out-of

10

CodeY0Y9I0I1I2I3多余的6个状态如何处理？输出均无效：拒绝“翻译”作为任意项处理——电路内部结构简单二-十进制译码器1

1

1

1

1

1

1

1

1

11

1

1

1

1

1

1

1

1

11

1

1

1

1

1

1

1

1

11

1

1

1

1

1

1

1

1

11

1

1

1

1

1

1

1

1

11

1

1

1

1

1

1

1

1

1I3I2I1I0Y0_LY9_L000000000110000111100001100110001010101010111111111101111111111011111111110111111111101111111111011111111110111111111101111111111011111111110123456789伪码1010101111110001任意项111011116.4.8

Seven-Segment

Decoders(七段显示译码器)(P408)公共阴极abcefgd

pNormally

use

(常用的有)：Light-Emitting

Diodes（LED,半导体数码管）Liquid-Crystal

Display（LCD,液晶数码管