嵌入式系统原理与应用 第3版 附录一 2410addr.a（或2410addr.inc）文件

附录一2410addr.a（或2410addr.inc）文件

GBLLBIG_ENDIAN__

BIG_ENDIAN__SETL{FALSE}

;=================

;Memorycontrol

;=================

BWSCONEQU0x48000000;Buswidth&waitstatus

BANKCON0EQU0x48000004;BootROMcontrol

BANKCON1EQU0x48000008;BANK1control

BANKCON2EQU0x4800000c;BANK2cControl

BANKCON3EQU0x48000010;BANK3control

BANKCON4EQU0x48000014;BANK4control

BANKCON5EQU0x48000018;BANK5control

BANKCON6EQU0x4800001c;BANK6control

BANKCON7EQU0x48000020;BANK7control

REFRESHEQU0x48000024;DRAM/SDRAMrefresh

BANKSIZEEQU0x48000028;FlexibleBankSize

MRSRB6EQU0x4800002c;ModeregistersetforSDRAM

MRSRB7EQU0x48000030;ModeregistersetforSDRAM

;=================

;USBHost

;=================

;=================

;INTERRUPT

;=================

SRCPNDEQU0x4a000000;Interruptrequeststatus

INTMODEQU0x4a000004;Interruptmodecontrol

INTMSKEQU0x4a000008;Interruptmaskcontrol

PRIORITYEQU0x4a00000c;IRQprioritycontrol<--May06,2002SOP

INTPNDEQU0x4a000010;Interruptrequeststatus

INTOFFSETEQU0x4a000014;Interruotrequestsourceoffset

SUBSRCPNDEQU0x4a000018;Subsourcepending

INTSUBMSKEQU0x4a00001c;Interruptsubmask

;=================

;DMA

;=================

DISRC0EQU0x4b000000;DMA0Initialsource

DISRCC0EQU0x4b000004;DMA0Initialsourcecontrol

DIDST0EQU0x4b000008;DMA0InitialDestination

DIDSTC0EQU0x4b00000c;DMA0InitialDestinationcontrol

DCON0EQU0x4b000010;DMA0Control

DSTAT0EQU0x4b000014;DMA0Status

DCSRC0EQU0x4b000018;DMA0Currentsource

DCDST0EQU0x4b00001c;DMA0Currentdestination

DMASKTRIG0EQU0x4b000020;DMA0Masktrigger

DISRC1EQU0x4b000040;DMA1Initialsource

DISRCC1EQU0x4b000044;DMA1Initialsourcecontrol

DIDST1EQU0x4b000048;DMA1InitialDestination

DIDSTC1EQU0x4b00004c;DMA1InitialDestinationcontrol

DCON1EQU0x4b000050;DMA1Control

DSTAT1EQU0x4b000054;DMA1Status

DCSRC1EQU0x4b000058;DMA1Currentsource

DCDST1EQU0x4b00005c;DMA1Currentdestination

DMASKTRIG1EQU0x4b000060;DMA1Masktrigger

DISRC2EQU0x4b000080;DMA2Initialsource

DISRCC2EQU0x4b000084;DMA2Initialsourcecontrol

DIDST2EQU0x4b000088;DMA2InitialDestination

DIDSTC2EQU0x4b00008c;DMA2InitialDestinationcontrol

DCON2EQU0x4b000090;DMA2Control

DSTAT2EQU0x4b000094;DMA2Status

DCSRC2EQU0x4b000098;DMA2Currentsource

DCDST2EQU0x4b00009c;DMA2Currentdestination

DMASKTRIG2EQU0x4b0000a0;DMA2Masktrigger

DISRC3EQU0x4b0000c0;DMA3Initialsource

DISRCC3EQU0x4b0000c4;DMA3Initialsourcecontrol

DIDST3EQU0x4b0000c8;DMA3InitialDestination

DIDSTC3EQU0x4b0000cc;DMA3InitialDestinationcontrol

DCON3EQU0x4b0000d0;DMA3Control

DSTAT3EQU0x4b0000d4;DMA3Status

DCSRC3EQU0x4b0000d8;DMA3Currentsource

DCDST3EQU0x4b0000dc;DMA3Currentdestination

DMASKTRIG3EQU0x4b0000e0;DMA3Masktrigger

;==========================

;CLOCK&POWERMANAGEMENT

;==========================

LOCKTIMEEQU0x4c000000;PLLlocktimecounter

MPLLCONEQU0x4c000004;MPLLControl

UPLLCONEQU0x4c000008;UPLLControl

CLKCONEQU0x4c00000c;Clockgeneratorcontrol

CLKSLOWEQU0x4c000010;Slowclockcontrol

CLKDIVNEQU0x4c000014;Clockdividercontrol

;=================

;LCDCONTROLLER

;=================

LCDCON1EQU0x4d000000;LCDcontrol1

LCDCON2EQU0x4d000004;LCDcontrol2

LCDCON3EQU0x4d000008;LCDcontrol3

LCDCON4EQU0x4d00000c;LCDcontrol4

LCDCON5EQU0x4d000010;LCDcontrol5

LCDSADDR1EQU0x4d000014;STN/TFTFramebufferstartaddress1

LCDSADDR2EQU0x4d000018;STN/TFTFramebufferstartaddress2

LCDSADDR3EQU0x4d00001c;STN/TFTVirtualscreenaddressset

REDLUTEQU0x4d000020;STNRedlookuptable

GREENLUTEQU0x4d000024;STNGreenlookuptable

BLUELUTEQU0x4d000028;STNBluelookuptable

DITHMODEEQU0x4d00004c;STNDitheringmode

TPALEQU0x4d000050;TFTTemporarypalette

LCDINTPNDEQU0x4d000054;LCDInterruptpending

LCDSRCPNDEQU0x4d000058;LCDInterruptsource

LCDINTMSKEQU0x4d00005c;LCDInterruptmask

LPCSELEQU0x4d000060;LPC3600Control

;=================

;NANDflash

;=================

NFCONFEQU0x4e000000;NANDFlashconfiguration

NFCMDEQU0x4e000004;NADDFlashcommand

NFADDREQU0x4e000008;NANDFlashaddress

NFDATAEQU0x4e00000c;NANDFlashdata

NFSTATEQU0x4e000010;NANDFlashoperationstatus

NFECCEQU0x4e000014;NANDFlashECC

;=================

;UART

;=================

ULCON0EQU0x50000000;UART0Linecontrol

UCON0EQU0x50000004;UART0Control

UFCON0EQU0x50000008;UART0FIFOcontrol

UMCON0EQU0x5000000c;UART0Modemcontrol

UTRSTAT0EQU0x50000010;UART0Tx/Rxstatus

UERSTAT0EQU0x50000014;UART0Rxerrorstatus

UFSTAT0EQU0x50000018;UART0FIFOstatus

UMSTAT0EQU0x5000001c;UART0Modemstatus

UBRDIV0EQU0x50000028;UART0Baudratedivisor

ULCON1EQU0x50004000;UART1Linecontrol

UCON1EQU0x50004004;UART1Control

UFCON1EQU0x50004008;UART1FIFOcontrol

UMCON1EQU0x5000400c;UART1Modemcontrol

UTRSTAT1EQU0x50004010;UART1Tx/Rxstatus

UERSTAT1EQU0x50004014;UART1Rxerrorstatus

UFSTAT1EQU0x50004018;UART1FIFOstatus

UMSTAT1EQU0x5000401c;UART1Modemstatus

UBRDIV1EQU0x50004028;UART1Baudratedivisor

ULCON2EQU0x50008000;UART2Linecontrol

UCON2EQU0x50008004;UART2Control

UFCON2EQU0x50008008;UART2FIFOcontrol

UMCON2EQU0x5000800c;UART2Modemcontrol

UTRSTAT2EQU0x50008010;UART2Tx/Rxstatus

UERSTAT2EQU0x50008014;UART2Rxerrorstatus

UFSTAT2EQU0x50008018;UART2FIFOstatus

UMSTAT2EQU0x5000801c;UART2Modemstatus

UBRDIV2EQU0x50008028;UART2Baudratedivisor

[BIG_ENDIAN__

UTXH0EQU0x50000023;UART0TransmissionHold

URXH0EQU0x50000027;UART0Receivebuffer

UTXH1EQU0x50004023;UART1TransmissionHold

URXH1EQU0x50004027;UART1Receivebuffer

UTXH2EQU0x50008023;UART2TransmissionHold

URXH2EQU0x50008027;UART2Receivebuffer

|;LittleEndian

UTXH0EQU0x50000020;UART0TransmissionHold

URXH0EQU0x50000024;UART0Receivebuffer

UTXH1EQU0x50004020;UART1TransmissionHold

URXH1EQU0x50004024;UART1Receivebuffer

UTXH2EQU0x50008020;UART2TransmissionHold

URXH2EQU0x50008024;UART2Receivebuffer

]

;=================

;PWMTIMER

;=================

TCFG0EQU0x51000000;Timer0configuration

TCFG1EQU0x51000004;Timer1configuration

TCONEQU0x51000008;Timercontrol

TCNTB0EQU0x5100000c;Timercountbuffer0

TCMPB0EQU0x51000010;Timercomparebuffer0

TCNTO0EQU0x51000014;Timercountobservation0

TCNTB1EQU0x51000018;Timercountbuffer1

TCMPB1EQU0x5100001c;Timercomparebuffer1

TCNTO1EQU0x51000020;Timercountobservation1

TCNTB2EQU0x51000024;Timercountbuffer2

TCMPB2EQU0x51000028;Timercomparebuffer2

TCNTO2EQU0x5100002c;Timercountobservation2

TCNTB3EQU0x51000030;Timercountbuffer3

TCMPB3EQU0x51000034;Timercomparebuffer3

TCNTO3EQU0x51000038;Timercountobservation3

TCNTB4EQU0x5100003c;Timercountbuffer4

TCNTO4EQU0x51000040;Timercountobservation4

;=================

;USBDEVICE

;=================

[BIG_ENDIAN__

FUNC_ADDR_REGEQU0x52000143;Functionaddress

PWR_REGEQU0x52000147;Powermanagement

EP_INT_REGEQU0x5200014b;EPInterruptpendingandclear

USB_INT_REGEQU0x5200015b;USBInterruptpendingandclear

EP_INT_EN_REGEQU0x5200015f;Interruptenable

USB_INT_EN_REGEQU0x5200016f

FRAME_NUM1_REGEQU0x52000173;Framenumberlowerbyte

FRAME_NUM2_REGEQU0x52000177;Framenumberlowerbyte

INDEX_REGEQU0x5200017b;Registerindex

MAXP_REGEQU0x52000183;Endpointmaxpacket

EP0_CSREQU0x52000187;Endpoint0status

IN_CSR1_REGEQU0x52000187;Inendpointcontrolstatus

IN_CSR2_REGEQU0x5200018b

OUT_CSR1_REGEQU0x52000193;Outendpointcontrolstatus

OUT_CSR2_REGEQU0x52000197

OUT_FIFO_CNT1_REGEQU0x5200019b;Endpointoutwritecount

OUT_FIFO_CNT2_REGEQU0x5200019f

EP0_FIFOEQU0x520001c3;Endpoint0FIFO

EP1_FIFOEQU0x520001c7;Endpoint1FIFO

EP2_FIFOEQU0x520001cb;Endpoint2FIFO

EP3_FIFOEQU0x520001cf;Endpoint3FIFO

EP4_FIFOEQU0x520001d3;Endpoint4FIFO

EP1_DMA_CONEQU0x52000203;EP1DMAinterfacecontrol

EP1_DMA_UNITEQU0x52000207;EP1DMATxunitcounter

EP1_DMA_FIFOEQU0x5200020b;EP1DMATxFIFOcounter

EP1_DMA_TTC_LEQU0x5200020f;EP1DMAtotalTxcounter

EP1_DMA_TTC_MEQU0x52000213

EP1_DMA_TTC_HEQU0x52000217

EP2_DMA_CONEQU0x5200021b;EP2DMAinterfacecontrol

EP2_DMA_UNITEQU0x5200021f;EP2DMATxunitcounter

EP2_DMA_FIFOEQU0x52000223;EP2DMATxFIFOcounter

EP2_DMA_TTC_LEQU0x52000227;EP2DMAtotalTxcounter

EP2_DMA_TTC_MEQU0x5200022b

EP2_DMA_TTC_HEQU0x5200022f

EP3_DMA_CONEQU0x52000243;EP3DMAinterfacecontrol

EP3_DMA_UNITEQU0x52000247;EP3DMATxunitcounter

EP3_DMA_FIFOEQU0x5200024b;EP3DMATxFIFOcounter

EP3_DMA_TTC_LEQU0x5200024f;EP3DMAtotalTxcounter

EP3_DMA_TTC_MEQU0x52000253

EP3_DMA_TTC_HEQU0x52000257

EP4_DMA_CONEQU0x5200025b;EP4DMAinterfacecontrol

EP4_DMA_UNITEQU0x5200025f;EP4DMATxunitcounter

EP4_DMA_FIFOEQU0x52000263;EP4DMATxFIFOcounter

EP4_DMA_TTC_LEQU0x52000267;EP4DMAtotalTxcounter

EP4_DMA_TTC_MEQU0x5200026b

EP4_DMA_TTC_HEQU0x5200026f

|;LittleEndian

FUNC_ADDR_REGEQU0x52000140;Functionaddress

PWR_REGEQU0x52000144;Powermanagement

EP_INT_REGEQU0x52000148;EPInterruptpendingandclear

USB_INT_REGEQU0x52000158;USBInterruptpendingandclear

EP_INT_EN_REGEQU0x5200015c;Interruptenable

USB_INT_EN_REGEQU0x5200016c

FRAME_NUM1_REGEQU0x52000170;Framenumberlowerbyte

FRAME_NUM2_REGEQU0x52000174;Framenumberlowerbyte

INDEX_REGEQU0x52000178;Registerindex

MAXP_REGEQU0x52000180;Endpointmaxpacket

EP0_CSREQU0x52000184;Endpoint0status

IN_CSR1_REGEQU0x52000184;Inendpointcontrolstatus

IN_CSR2_REGEQU0x52000188

OUT_CSR1_REGEQU0x52000190;Outendpointcontrolstatus

OUT_CSR2_REGEQU0x52000194

OUT_FIFO_CNT1_REGEQU0x52000198;Endpointoutwritecount

OUT_FIFO_CNT2_REGEQU0x5200019c

EP0_FIFOEQU0x520001c0;Endpoint0FIFO

EP1_FIFOEQU0x520001c4;Endpoint1FIFO

EP2_FIFOEQU0x520001c8;Endpoint2FIFO

EP3_FIFOEQU0x520001cc;Endpoint3FIFO

EP4_FIFOEQU0x520001d0;Endpoint4FIFO

EP1_DMA_CONEQU0x52000200;EP1DMAinterfacecontrol

EP1_DMA_UNITEQU0x52000204;EP1DMATxunitcounter

EP1_DMA_FIFOEQU0x52000208;EP1DMATxFIFOcounter

EP1_DMA_TTC_LEQU0x5200020c;EP1DMAtotalTxcounter

EP1_DMA_TTC_MEQU0x52000210

EP1_DMA_TTC_HEQU0x52000214

EP2_DMA_CONEQU0x52000218;EP2DMAinterfacecontrol

EP2_DMA_UNITEQU0x5200021c;EP2DMATxunitcounter

EP2_DMA_FIFOEQU0x52000220;EP2DMATxFIFOcounter

EP2_DMA_TTC_LEQU0x52000224;EP2DMAtotalTxcounter

EP2_DMA_TTC_MEQU0x52000228

EP2_DMA_TTC_HEQU0x5200022c

EP3_DMA_CONEQU0x52000240;EP3DMAinterfacecontrol

EP3_DMA_UNITEQU0x52000244;EP3DMATxunitcounter

EP3_DMA_FIFOEQU0x52000248;EP3DMATxFIFOcounter

EP3_DMA_TTC_LEQU0x5200024c;EP3DMAtotalTxcounter

EP3_DMA_TTC_MEQU0x52000250

EP3_DMA_TTC_HEQU0x52000254

EP4_DMA_CONEQU0x52000258;EP4DMAinterfacecontrol

EP4_DMA_UNITEQU0x5200025c;EP4DMATxunitcounter

EP4_DMA_FIFOEQU0x52000260;EP4DMATxFIFOcounter

EP4_DMA_TTC_LEQU0x52000264;EP4DMAtotalTxcounter

EP4_DMA_TTC_MEQU0x52000268

EP4_DMA_TTC_HEQU0x5200026c

]

;=================

;WATCHDOGTIMER

;=================

WTCONEQU0x53000000;Watch-dogtimermode

WTDATEQU0x53000004;Watch-dogtimerdata

WTCNTEQU0x53000008;Eatch-dogtimercount

;=================

;IIC

;=================

IICCONEQU0x54000000;IICcontrol

IICSTATEQU0x54000004;IICstatus

IICADDEQU0x54000008;IICaddress

IICDSEQU0x5400000c;IICdatashift

;=================

;IIS

;=================

IISCONEQU0x55000000;IISControl

IISMODEQU0x55000004;IISMode

IISPSREQU0x55000008;IISPrescaler

IISFCONEQU0x5500000c;IISFIFOcontrol

[BIG_ENDIAN__

IISFIFOEQU0x55000012;IISFIFOentry

|;LittleEndian

IISFIFOEQU0x55000010;IISFIFOentry

]

;=================

;I/OPORT

;=================

GPACONEQU0x56000000;PortAcontrol

GPADATEQU0x56000004;PortAdata

GPBCONEQU0x56000010;PortBcontrol

GPBDATEQU0x56000014;PortBdata

GPBUPEQU0x56000018;Pull-upcontrolB

GPCCONEQU0x56000020;PortCcontrol

GPCDATEQU0x56000024;PortCdata

GPCUPEQU0x56000028;Pull-upcontrolC

GPDCONEQU0x56000030;PortDcontrol

GPDDATEQU0x56000034;PortDdata

GPDUPEQU0x56000038;Pull-upcontrolD

GPECONEQU0x56000040;PortEcontrol

GPEDATEQU0x56000044;PortEdata

GPEUPEQU0x56000048;Pull-upcontrolE

GPFCONEQU0x56000050;PortFcontrol

GPFDATEQU0x56000054;PortFdata

GPFUPEQU0x56000058;Pull-upcontrolF

GPGCONEQU0x56000060;PortGcontrol

GPGDATEQU0x56000064;PortGdata

GPGUPEQU0x56000068;Pull-upcontrolG

GPHCONEQU0x56000070;PortHcontrol

GPHDATEQU0x56000074;PortHdata

GPHUPEQU0x56000078;Pull-upcontrolH

MISCCREQU0x56000080;Miscellaneouscontrol

DCKCONEQU0x56000084;DCLK0/1control

EXTINT0EQU0x56000088;Externalinterruptcontrolregister0

EXTINT1EQU0x5600008c;Externalinterruptcontrolregister1

EXTINT2EQU0x56000090;Externalinterruptcontrolregister2

EINTFLT0EQU0x56000094;Reserved

EINTFLT1EQU0x56000098;Reserved

EINTFLT2EQU0x5600009c;Externalinterruptfiltercontrolregister2

EINTFLT3EQU0x560000a0;Externalinterruptfiltercontrolregister3

EINTMASKEQU0x560000a4;Externalinterruptmask

EINTPENDEQU0x560000a8;Externalinterruptpending

GSTATUS0EQU0x560000ac;Externalpinstatus

GSTATUS1EQU0x560000b0;ChipID(0x32410000)

GSTATUS2EQU0x560000b4;Resettype

GSTATUS3EQU0x560000b8;Saveddata0(32-bit)beforeenteringPOWER_OFFmode

GSTATUS4EQU0x560000bc;Saveddata1(32-bit)beforeenteringPOWER_OFFmode

;=================

;RTC

;=================

[BIG_ENDIAN__

RTCCONEQU0x57000043;RTCcontrol

TICNTEQU0x57000047;Ticktimecount

RTCALMEQU0x57000053;RTCalarmcontrol

ALMSECEQU0x57000057;Alarmsecond

ALMMINEQU0x5700005b;Alarmminute

ALMHOUREQU0x5700005f;AlarmHour

ALMDATEEQU0x57000063;Alarmday<--May06,2002SOP

ALMMONEQU0x57000067;Alarmmonth

ALMYEAREQU0x5700006b;Alarmyear

RTCRSTEQU0x5700006f;RTCroundreset

BCDSECEQU0x57000073;BCDsecond

BCDMINEQU0x57000077;BCDminute

BCDHOUREQU0x5700007b;BCDhour

BCDDATEEQU0x5700007f;BCDday<--May06,2002SOP

BCDDAYEQU0x57000083;BCDdate<--May06,2002SOP

BCDMONEQU0x57000087;BCDmonth

BCDYEAREQU0x5700008b;BCDyear

|;LittleEndian

RTCCONEQU0x57000040;RTCcontrol

TICNTEQU0x57000044;Ticktimecount

RTCALMEQU0x57000050;RTCalarmcontrol

ALMSECEQU0x57000054;Alarmsecond

ALMMINEQU0x57000058;Alarmminute

ALMHOUREQU0x5700005c;AlarmHour

ALMDATEEQU0x57000060;Alarmday<--May06,2002SOP

ALMMONEQU0x57000064;Alarmmonth

ALMYEAREQU0x57000068;Alarmyear

RTCRSTEQU0x5700006c;RTCroundreset

BCDSECEQU0x57000070;BCDsecond

BCDMINEQU0x57000074;BCDminute

BCDHOUREQU0x57000078;BCDhour

BCDDATEEQU0x5700007c;BCDday<--May06,2002SOP

BCDDAYEQU0x57000080;BCDdate<--May06,2002SOP

BCDMONEQU0x57000084;BCDmonth

BCDYEAREQU0x57000088;BCDyear

];RTC

;=================

;ADC

;=================

ADCCONEQU0x58000000;ADCcontrol

ADCTSCEQU0x58000004;ADCtouchscreencontrol

ADCDLYEQU0x58000008;ADCstartorIntervalDelay

ADCDAT0EQU0x5800000c;ADCconversiondata0

ADCDAT1EQU0x58000010;ADCconversiondata1

;=================

;SPI

;=================

SPCON0EQU0x59000000;SPI0control

SPSTA0EQU0x59000004;SPI0status

SPPIN0EQU0x59000008;SPI0pincontrol

SPPRE0EQU0x5900000c;SPI0baudrateprescaler

SPTDAT0EQU0x59000010;SPI0Txdata

SPRDAT0EQU0x59000014;SPI0Rxdata

SPCON1EQU0x59000020;SPI1control

SPSTA1EQU0x59000024;SPI1status

SPPIN1EQU0x59000028;SPI1pincontrol

SPPRE1EQU0x5900002c;SPI1baudrateprescaler

SPTDAT1EQU0x59000030;SPI1Txdata

SPRDAT1EQU0x59000034;SPI1Rxdata

;=================

;SDInterface

;=================

SDICONEQU0x5a000000;SDIcontrol

SDIPREEQU0x5a000000;SDIbaudrateprescaler

SDICmdArgEQU0x5a000000;SDIcommandargument

SDICmdConEQU0x5a000000;SDIcommandcontrol

SDICmdStaEQU0x5a000000;SDIcommandstatus

SDIRSP0EQU0x5a000000;SDIresponse0

SDIRSP1EQU0x5a000000;SDIresponse1

SDIRSP2EQU0x5a000000;SDIresponse2

SDIRSP3EQU0x5a000000;SDIresponse3

SDIDTimerEQU0x5a000000;SDIdata/busytimer

SDIBSizeEQU0x5a000000;SDIblocksize

SDIDatConEQU0x5a000000;SDIdatacontrol

SDIDatCntEQU0x5a000000;SDIdataremaincounter

SDIDatStaEQU0x5a000000;SDIdatastatus

SDIFSTAEQU0x5a000000;SDIFIFOstatus

SDIIntMskEQU0x5a000000;SDIinterruptmask

[BIG_ENDIAN__

SDIDATEQU0x5a00003f;SDIdata

|;LittleEndian

SDIDATEQU0x5a00003c;SDIdata

];SDInterface

;=================

;ISR

;=================

pISR_RESETEQU(_ISR_STARTADDRESS+0x0)

pISR_UNDEFEQU(_ISR_STARTADDRESS+0x4)

pISR_SWIEQU(_ISR_STARTADDRESS+0x8)

pISR_PABORTEQU(_ISR_STARTADDRESS+0xc)

pISR_DABORTEQU(_ISR_STARTADDRESS+0x10)

pISR_RESERVEDEQU(_ISR_STARTADDRESS+0x14)

pISR_IRQEQU(_ISR_STARTADDRESS+0x18)

pISR_FIQEQU(_ISR_STARTADDRESS+0x1c)

pISR_EINT0EQU(_ISR_STARTADDRESS+0x20)

pISR_EINT1EQU(_ISR_STA